| Index: embios/trunk/init.c |
| — | — | @@ -41,10 +41,12 @@ |
| 42 | 42 | #include "disk.h"
|
| 43 | 43 | #endif
|
| 44 | 44 |
|
| | 45 | +
|
| 45 | 46 | static const char welcomestring[] INITCONST_ATTR = "emBIOS v" VERSION " r" VERSION_SVN "\n\n";
|
| 46 | 47 | static const char initthreadname[] INITCONST_ATTR = "Initialisation thread";
|
| 47 | 48 | static uint32_t initstack[0x400] INITBSS_ATTR;
|
| 48 | 49 |
|
| | 50 | +
|
| 49 | 51 | void initthread() INITCODE_ATTR;
|
| 50 | 52 | void initthread()
|
| 51 | 53 | {
|
| Index: embios/trunk/clockgates.h |
| — | — | @@ -0,0 +1,34 @@ |
| | 2 | +//
|
| | 3 | +//
|
| | 4 | +// Copyright 2010 TheSeven
|
| | 5 | +//
|
| | 6 | +//
|
| | 7 | +// This file is part of emBIOS.
|
| | 8 | +//
|
| | 9 | +// emBIOS is free software: you can redistribute it and/or
|
| | 10 | +// modify it under the terms of the GNU General Public License as
|
| | 11 | +// published by the Free Software Foundation, either version 2 of the
|
| | 12 | +// License, or (at your option) any later version.
|
| | 13 | +//
|
| | 14 | +// emBIOS is distributed in the hope that it will be useful,
|
| | 15 | +// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| | 16 | +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
| | 17 | +// See the GNU General Public License for more details.
|
| | 18 | +//
|
| | 19 | +// You should have received a copy of the GNU General Public License along
|
| | 20 | +// with emBIOS. If not, see <http://www.gnu.org/licenses/>.
|
| | 21 | +//
|
| | 22 | +//
|
| | 23 | +
|
| | 24 | +
|
| | 25 | +#ifndef __CLOCKGATES_H__
|
| | 26 | +#define __CLOCKGATES_H__
|
| | 27 | +
|
| | 28 | +
|
| | 29 | +#include "global.h"
|
| | 30 | +
|
| | 31 | +
|
| | 32 | +void clockgate_enable(int gate, bool enable);
|
| | 33 | +
|
| | 34 | +
|
| | 35 | +#endif |
| \ No newline at end of file |
| Index: embios/trunk/SOURCES |
| — | — | @@ -11,6 +11,7 @@ |
| 12 | 12 | target/ipodnano2g/nand.c
|
| 13 | 13 | target/ipodnano2g/ftl.c
|
| 14 | 14 | target/ipodnano2g/storage_nand.c
|
| | 15 | +target/ipodnano2g/clockgates.c
|
| 15 | 16 | usb/synopsysotg.c
|
| 16 | 17 | #endif
|
| 17 | 18 |
|
| — | — | @@ -23,6 +24,7 @@ |
| 24 | 25 | target/ipodnano4g/power.c
|
| 25 | 26 | target/ipodnano4g/accel.c
|
| 26 | 27 | target/ipodnano4g/backlight.c
|
| | 28 | +target/ipodnano4g/clockgates.c
|
| 27 | 29 | usb/synopsysotg.c
|
| 28 | 30 | #endif
|
| 29 | 31 |
|
| Index: embios/trunk/target/ipodnano2g/clockgates.c |
| — | — | @@ -0,0 +1,32 @@ |
| | 2 | +//
|
| | 3 | +//
|
| | 4 | +// Copyright 2010 TheSeven
|
| | 5 | +//
|
| | 6 | +//
|
| | 7 | +// This file is part of emBIOS.
|
| | 8 | +//
|
| | 9 | +// emBIOS is free software: you can redistribute it and/or
|
| | 10 | +// modify it under the terms of the GNU General Public License as
|
| | 11 | +// published by the Free Software Foundation, either version 2 of the
|
| | 12 | +// License, or (at your option) any later version.
|
| | 13 | +//
|
| | 14 | +// emBIOS is distributed in the hope that it will be useful,
|
| | 15 | +// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| | 16 | +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
| | 17 | +// See the GNU General Public License for more details.
|
| | 18 | +//
|
| | 19 | +// You should have received a copy of the GNU General Public License along
|
| | 20 | +// with emBIOS. If not, see <http://www.gnu.org/licenses/>.
|
| | 21 | +//
|
| | 22 | +//
|
| | 23 | +
|
| | 24 | +
|
| | 25 | +#include "global.h"
|
| | 26 | +#include "s5l8720.h"
|
| | 27 | +
|
| | 28 | +
|
| | 29 | +void clockgate_enable(int gate, bool enable)
|
| | 30 | +{
|
| | 31 | + if (enable) PWRCON(gate >> 5) &= ~(1 << (gate & 0x1f));
|
| | 32 | + else PWRCON(gate >> 5) |= 1 << (gate & 0x1f);
|
| | 33 | +}
|
| Index: embios/trunk/target/ipodnano2g/s5l8701.h |
| — | — | @@ -37,13 +37,12 @@ |
| 38 | 38 | #define PLL2LCNT (*((volatile uint32_t*)(0x3C50001C)))
|
| 39 | 39 | #define PLLLOCK (*((volatile uint32_t*)(0x3C500020)))
|
| 40 | 40 | #define PLLCON (*((volatile uint32_t*)(0x3C500024)))
|
| 41 | | -#define PWRCON (*((volatile uint32_t*)(0x3C500028)))
|
| 42 | 41 | #define PWRMODE (*((volatile uint32_t*)(0x3C50002C)))
|
| 43 | 42 | #define SWRCON (*((volatile uint32_t*)(0x3C500030)))
|
| 44 | 43 | #define RSTSR (*((volatile uint32_t*)(0x3C500034)))
|
| 45 | 44 | #define DSPCLKMD (*((volatile uint32_t*)(0x3C500038)))
|
| 46 | 45 | #define CLKCON2 (*((volatile uint32_t*)(0x3C50003C)))
|
| 47 | | -#define PWRCONEXT (*((volatile uint32_t*)(0x3C500040)))
|
| | 46 | +#define PWRCON(i) (*((volatile uint32_t*)(0x3C500000 + ((i) == 1 ? 0x28 : 0x40))))
|
| 48 | 47 |
|
| 49 | 48 |
|
| 50 | 49 | /////ICU/////
|
| — | — | @@ -285,6 +284,11 @@ |
| 286 | 285 | #define IICDS (*((volatile uint32_t*)(0x3C90000C)))
|
| 287 | 286 |
|
| 288 | 287 |
|
| | 288 | +/////CLOCK GATES/////
|
| | 289 | +#define CLOCKGATE_USB_1 14
|
| | 290 | +#define CLOCKGATE_USB_2 43
|
| | 291 | +
|
| | 292 | +
|
| 289 | 293 | /////INTERRUPTS/////
|
| 290 | 294 | #define IRQ_TIMER 5
|
| 291 | 295 | #define IRQ_DMA 10
|
| Index: embios/trunk/target/ipodnano4g/accel.c |
| — | — | @@ -26,5 +26,5 @@ |
| 27 | 27 | |
| 28 | 28 | int8_t accel_get_axis(uint8_t axis) |
| 29 | 29 | { |
| 30 | | - return i2crecvbyte(0, 0x3a, 0x29 + 2 * axis); |
| | 30 | + return i2c_recvbyte(0, 0x3a, 0x29 + 2 * axis); |
| 31 | 31 | } |
| Index: embios/trunk/target/ipodnano4g/i2c.c |
| — | — | @@ -28,21 +28,38 @@ |
| 29 | 29 |
|
| 30 | 30 |
|
| 31 | 31 | static struct mutex i2cmutex;
|
| 32 | | -static struct wakeup i2cwakeup;
|
| 33 | 32 |
|
| 34 | 33 |
|
| 35 | 34 | void i2c_init()
|
| 36 | 35 | {
|
| 37 | 36 | mutex_init(&i2cmutex);
|
| 38 | | - wakeup_init(&i2cwakeup);
|
| 39 | | -
|
| 40 | | - interrupt_enable(IRQ_IIC, true);
|
| 41 | 37 | }
|
| 42 | 38 |
|
| 43 | 39 | void i2c_send(uint32_t bus, uint32_t device, uint32_t address, const uint8_t* data, uint32_t length)
|
| 44 | 40 | {
|
| 45 | 41 | mutex_lock(&i2cmutex, TIMEOUT_BLOCK);
|
| 46 | | -
|
| | 42 | + IICDS(bus) = device & ~1;
|
| | 43 | + IICSTAT(bus) = 0xF0;
|
| | 44 | + IICCON(bus) = 0xB7;
|
| | 45 | + while ((IICCON(bus) & 0x10) == 0) yield();
|
| | 46 | + if (address >= 0)
|
| | 47 | + {
|
| | 48 | + /* write address */
|
| | 49 | + IICDS(bus) = address;
|
| | 50 | + IICCON(bus) = 0xB7;
|
| | 51 | + while ((IICCON(bus) & 0x10) == 0) yield();
|
| | 52 | + }
|
| | 53 | + /* write data */
|
| | 54 | + while (length--)
|
| | 55 | + {
|
| | 56 | + IICDS(bus) = *data++;
|
| | 57 | + IICCON(bus) = 0xB7;
|
| | 58 | + while ((IICCON(bus) & 0x10) == 0) yield();
|
| | 59 | + }
|
| | 60 | + /* STOP */
|
| | 61 | + IICSTAT(bus) = 0xD0;
|
| | 62 | + IICCON(bus) = 0xB7;
|
| | 63 | + while ((IICSTAT(bus) & (1 << 5)) != 0) yield();
|
| 47 | 64 | mutex_unlock(&i2cmutex);
|
| 48 | 65 | }
|
| 49 | 66 |
|
| — | — | @@ -49,7 +66,33 @@ |
| 50 | 67 | void i2c_recv(uint32_t bus, uint32_t device, uint32_t address, uint8_t* data, uint32_t length)
|
| 51 | 68 | {
|
| 52 | 69 | mutex_lock(&i2cmutex, TIMEOUT_BLOCK);
|
| 53 | | -
|
| | 70 | + if (address >= 0)
|
| | 71 | + {
|
| | 72 | + /* START */
|
| | 73 | + IICDS(bus) = device & ~1;
|
| | 74 | + IICSTAT(bus) = 0xF0;
|
| | 75 | + IICCON(bus) = 0xB7;
|
| | 76 | + while ((IICCON(bus) & 0x10) == 0) yield();
|
| | 77 | + /* write address */
|
| | 78 | + IICDS(bus) = address;
|
| | 79 | + IICCON(bus) = 0xB7;
|
| | 80 | + while ((IICCON(bus) & 0x10) == 0) yield();
|
| | 81 | + }
|
| | 82 | + /* (repeated) START */
|
| | 83 | + IICDS(bus) = device | 1;
|
| | 84 | + IICSTAT(bus) = 0xB0;
|
| | 85 | + IICCON(bus) = 0xB7;
|
| | 86 | + while ((IICCON(bus) & 0x10) == 0) yield();
|
| | 87 | + while (length--)
|
| | 88 | + {
|
| | 89 | + IICCON(bus) = (length == 0) ? 0x37 : 0xB7; /* NACK or ACK */
|
| | 90 | + while ((IICCON(bus) & 0x10) == 0) yield();
|
| | 91 | + *data++ = IICDS(bus);
|
| | 92 | + }
|
| | 93 | + /* STOP */
|
| | 94 | + IICSTAT(bus) = 0x90;
|
| | 95 | + IICCON(bus) = 0xB7;
|
| | 96 | + while ((IICSTAT(bus) & (1 << 5)) != 0) yield();
|
| 54 | 97 | mutex_unlock(&i2cmutex);
|
| 55 | 98 | }
|
| 56 | 99 |
|
| — | — | @@ -66,9 +109,3 @@ |
| 67 | 110 | i2c_recv(bus, device, address, buf, 1);
|
| 68 | 111 | return buf[0];
|
| 69 | 112 | }
|
| 70 | | -
|
| 71 | | -void INT_IIC()
|
| 72 | | -{
|
| 73 | | -
|
| 74 | | - wakeup_signal(&i2cwakeup);
|
| 75 | | -}
|
| Index: embios/trunk/target/ipodnano4g/clockgates.c |
| — | — | @@ -0,0 +1,32 @@ |
| | 2 | +//
|
| | 3 | +//
|
| | 4 | +// Copyright 2010 TheSeven
|
| | 5 | +//
|
| | 6 | +//
|
| | 7 | +// This file is part of emBIOS.
|
| | 8 | +//
|
| | 9 | +// emBIOS is free software: you can redistribute it and/or
|
| | 10 | +// modify it under the terms of the GNU General Public License as
|
| | 11 | +// published by the Free Software Foundation, either version 2 of the
|
| | 12 | +// License, or (at your option) any later version.
|
| | 13 | +//
|
| | 14 | +// emBIOS is distributed in the hope that it will be useful,
|
| | 15 | +// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| | 16 | +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
| | 17 | +// See the GNU General Public License for more details.
|
| | 18 | +//
|
| | 19 | +// You should have received a copy of the GNU General Public License along
|
| | 20 | +// with emBIOS. If not, see <http://www.gnu.org/licenses/>.
|
| | 21 | +//
|
| | 22 | +//
|
| | 23 | +
|
| | 24 | +
|
| | 25 | +#include "global.h"
|
| | 26 | +#include "s5l8720.h"
|
| | 27 | +
|
| | 28 | +
|
| | 29 | +void clockgate_enable(int gate, bool enable)
|
| | 30 | +{
|
| | 31 | + if (enable) PWRCON(gate >> 5) &= ~(1 << (gate & 0x1f));
|
| | 32 | + else PWRCON(gate >> 5) |= 1 << (gate & 0x1f);
|
| | 33 | +}
|
| Index: embios/trunk/target/ipodnano4g/s5l8720.h |
| — | — | @@ -27,211 +27,15 @@ |
| 28 | 28 | #include "global.h"
|
| 29 | 29 |
|
| 30 | 30 |
|
| 31 | | -/////CLKCON/////
|
| 32 | | -#define CLKCON (*((volatile uint32_t*)(0x3C500000)))
|
| 33 | | -#define PLL0PMS (*((volatile uint32_t*)(0x3C500004)))
|
| 34 | | -#define PLL1PMS (*((volatile uint32_t*)(0x3C500008)))
|
| 35 | | -#define PLL2PMS (*((volatile uint32_t*)(0x3C50000C)))
|
| 36 | | -#define PLL0LCNT (*((volatile uint32_t*)(0x3C500014)))
|
| 37 | | -#define PLL1LCNT (*((volatile uint32_t*)(0x3C500018)))
|
| 38 | | -#define PLL2LCNT (*((volatile uint32_t*)(0x3C50001C)))
|
| 39 | | -#define PLLLOCK (*((volatile uint32_t*)(0x3C500020)))
|
| 40 | | -#define PLLCON (*((volatile uint32_t*)(0x3C500024)))
|
| 41 | | -#define PWRCON (*((volatile uint32_t*)(0x3C500028)))
|
| 42 | | -#define PWRMODE (*((volatile uint32_t*)(0x3C50002C)))
|
| 43 | | -#define SWRCON (*((volatile uint32_t*)(0x3C500030)))
|
| 44 | | -#define RSTSR (*((volatile uint32_t*)(0x3C500034)))
|
| 45 | | -#define DSPCLKMD (*((volatile uint32_t*)(0x3C500038)))
|
| 46 | | -#define CLKCON2 (*((volatile uint32_t*)(0x3C50003C)))
|
| 47 | | -#define PWRCONEXT (*((volatile uint32_t*)(0x3C500040)))
|
| | 31 | +/////SYSCON/////
|
| | 32 | +#define PWRCON(i) (*((volatile uint32_t*)(0x3C500000 \
|
| | 33 | + + ((i) == 4 ? 0x6C : \
|
| | 34 | + ((i) == 3 ? 0x68 : \
|
| | 35 | + ((i) == 2 ? 0x58 : \
|
| | 36 | + ((i) == 1 ? 0x4C : \
|
| | 37 | + 0x48)))))))
|
| 48 | 38 |
|
| 49 | 39 |
|
| 50 | | -/////GPIO/////
|
| 51 | | -#define PCON0 (*((volatile uint32_t*)(0x3CF00000)))
|
| 52 | | -#define PDAT0 (*((volatile uint32_t*)(0x3CF00004)))
|
| 53 | | -#define PCON1 (*((volatile uint32_t*)(0x3CF00010)))
|
| 54 | | -#define PDAT1 (*((volatile uint32_t*)(0x3CF00014)))
|
| 55 | | -#define PCON2 (*((volatile uint32_t*)(0x3CF00020)))
|
| 56 | | -#define PDAT2 (*((volatile uint32_t*)(0x3CF00024)))
|
| 57 | | -#define PCON3 (*((volatile uint32_t*)(0x3CF00030)))
|
| 58 | | -#define PDAT3 (*((volatile uint32_t*)(0x3CF00034)))
|
| 59 | | -#define PCON4 (*((volatile uint32_t*)(0x3CF00040)))
|
| 60 | | -#define PDAT4 (*((volatile uint32_t*)(0x3CF00044)))
|
| 61 | | -#define PCON5 (*((volatile uint32_t*)(0x3CF00050)))
|
| 62 | | -#define PDAT5 (*((volatile uint32_t*)(0x3CF00054)))
|
| 63 | | -#define PUNK5 (*((volatile uint32_t*)(0x3CF0005C)))
|
| 64 | | -#define PCON6 (*((volatile uint32_t*)(0x3CF00060)))
|
| 65 | | -#define PDAT6 (*((volatile uint32_t*)(0x3CF00064)))
|
| 66 | | -#define PCON7 (*((volatile uint32_t*)(0x3CF00070)))
|
| 67 | | -#define PDAT7 (*((volatile uint32_t*)(0x3CF00074)))
|
| 68 | | -#define PCON10 (*((volatile uint32_t*)(0x3CF000A0)))
|
| 69 | | -#define PDAT10 (*((volatile uint32_t*)(0x3CF000A4)))
|
| 70 | | -#define PCON11 (*((volatile uint32_t*)(0x3CF000B0)))
|
| 71 | | -#define PDAT11 (*((volatile uint32_t*)(0x3CF000B4)))
|
| 72 | | -#define PCON15 (*((volatile uint32_t*)(0x3CF000F0)))
|
| 73 | | -#define PUNK15 (*((volatile uint32_t*)(0x3CF000FC)))
|
| 74 | | -
|
| 75 | | -
|
| 76 | | -/////IODMA/////
|
| 77 | | -#define DMABASE0 (*((volatile uint32_t*)(0x38400000)))
|
| 78 | | -#define DMACON0 (*((volatile uint32_t*)(0x38400004)))
|
| 79 | | -#define DMATCNT0 (*((volatile uint32_t*)(0x38400008)))
|
| 80 | | -#define DMACADDR0 (*((volatile uint32_t*)(0x3840000C)))
|
| 81 | | -#define DMACTCNT0 (*((volatile uint32_t*)(0x38400010)))
|
| 82 | | -#define DMACOM0 (*((volatile uint32_t*)(0x38400014)))
|
| 83 | | -#define DMANOF0 (*((volatile uint32_t*)(0x38400018)))
|
| 84 | | -#define DMABASE1 (*((volatile uint32_t*)(0x38400020)))
|
| 85 | | -#define DMACON1 (*((volatile uint32_t*)(0x38400024)))
|
| 86 | | -#define DMATCNT1 (*((volatile uint32_t*)(0x38400028)))
|
| 87 | | -#define DMACADDR1 (*((volatile uint32_t*)(0x3840002C)))
|
| 88 | | -#define DMACTCNT1 (*((volatile uint32_t*)(0x38400030)))
|
| 89 | | -#define DMACOM1 (*((volatile uint32_t*)(0x38400034)))
|
| 90 | | -#define DMABASE2 (*((volatile uint32_t*)(0x38400040)))
|
| 91 | | -#define DMACON2 (*((volatile uint32_t*)(0x38400044)))
|
| 92 | | -#define DMATCNT2 (*((volatile uint32_t*)(0x38400048)))
|
| 93 | | -#define DMACADDR2 (*((volatile uint32_t*)(0x3840004C)))
|
| 94 | | -#define DMACTCNT2 (*((volatile uint32_t*)(0x38400050)))
|
| 95 | | -#define DMACOM2 (*((volatile uint32_t*)(0x38400054)))
|
| 96 | | -#define DMABASE3 (*((volatile uint32_t*)(0x38400060)))
|
| 97 | | -#define DMACON3 (*((volatile uint32_t*)(0x38400064)))
|
| 98 | | -#define DMATCNT3 (*((volatile uint32_t*)(0x38400068)))
|
| 99 | | -#define DMACADDR3 (*((volatile uint32_t*)(0x3840006C)))
|
| 100 | | -#define DMACTCNT3 (*((volatile uint32_t*)(0x38400070)))
|
| 101 | | -#define DMACOM3 (*((volatile uint32_t*)(0x38400074)))
|
| 102 | | -#define DMABASE4 (*((volatile uint32_t*)(0x38400080)))
|
| 103 | | -#define DMACON4 (*((volatile uint32_t*)(0x38400084)))
|
| 104 | | -#define DMATCNT4 (*((volatile uint32_t*)(0x38400088)))
|
| 105 | | -#define DMACADDR4 (*((volatile uint32_t*)(0x3840008C)))
|
| 106 | | -#define DMACTCNT4 (*((volatile uint32_t*)(0x38400090)))
|
| 107 | | -#define DMACOM4 (*((volatile uint32_t*)(0x38400094)))
|
| 108 | | -#define DMABASE5 (*((volatile uint32_t*)(0x384000A0)))
|
| 109 | | -#define DMACON5 (*((volatile uint32_t*)(0x384000A4)))
|
| 110 | | -#define DMATCNT5 (*((volatile uint32_t*)(0x384000A8)))
|
| 111 | | -#define DMACADDR5 (*((volatile uint32_t*)(0x384000AC)))
|
| 112 | | -#define DMACTCNT5 (*((volatile uint32_t*)(0x384000B0)))
|
| 113 | | -#define DMACOM5 (*((volatile uint32_t*)(0x384000B4)))
|
| 114 | | -#define DMABASE6 (*((volatile uint32_t*)(0x384000C0)))
|
| 115 | | -#define DMACON6 (*((volatile uint32_t*)(0x384000C4)))
|
| 116 | | -#define DMATCNT6 (*((volatile uint32_t*)(0x384000C8)))
|
| 117 | | -#define DMACADDR6 (*((volatile uint32_t*)(0x384000CC)))
|
| 118 | | -#define DMACTCNT6 (*((volatile uint32_t*)(0x384000D0)))
|
| 119 | | -#define DMACOM6 (*((volatile uint32_t*)(0x384000D4)))
|
| 120 | | -#define DMABASE7 (*((volatile uint32_t*)(0x384000E0)))
|
| 121 | | -#define DMACON7 (*((volatile uint32_t*)(0x384000E4)))
|
| 122 | | -#define DMATCNT7 (*((volatile uint32_t*)(0x384000E8)))
|
| 123 | | -#define DMACADDR7 (*((volatile uint32_t*)(0x384000EC)))
|
| 124 | | -#define DMACTCNT7 (*((volatile uint32_t*)(0x384000F0)))
|
| 125 | | -#define DMACOM7 (*((volatile uint32_t*)(0x384000F4)))
|
| 126 | | -#define DMABASE8 (*((volatile uint32_t*)(0x38400100)))
|
| 127 | | -#define DMACON8 (*((volatile uint32_t*)(0x38400104)))
|
| 128 | | -#define DMATCNT8 (*((volatile uint32_t*)(0x38400108)))
|
| 129 | | -#define DMACADDR8 (*((volatile uint32_t*)(0x3840010C)))
|
| 130 | | -#define DMACTCNT8 (*((volatile uint32_t*)(0x38400110)))
|
| 131 | | -#define DMACOM8 (*((volatile uint32_t*)(0x38400114)))
|
| 132 | | -#define DMAALLST (*((volatile uint32_t*)(0x38400180)))
|
| 133 | | -#define DMAALLST2 (*((volatile uint32_t*)(0x38400184)))
|
| 134 | | -#define DMACON_DEVICE_SHIFT 30
|
| 135 | | -#define DMACON_DIRECTION_SHIFT 29
|
| 136 | | -#define DMACON_DATA_SIZE_SHIFT 22
|
| 137 | | -#define DMACON_BURST_LEN_SHIFT 19
|
| 138 | | -#define DMACOM_START 4
|
| 139 | | -#define DMACOM_CLEARBOTHDONE 7
|
| 140 | | -#define DMAALLST_WCOM0 (1 << 0)
|
| 141 | | -#define DMAALLST_HCOM0 (1 << 1)
|
| 142 | | -#define DMAALLST_DMABUSY0 (1 << 2)
|
| 143 | | -#define DMAALLST_HOLD_SKIP (1 << 3)
|
| 144 | | -#define DMAALLST_WCOM1 (1 << 4)
|
| 145 | | -#define DMAALLST_HCOM1 (1 << 5)
|
| 146 | | -#define DMAALLST_DMABUSY1 (1 << 6)
|
| 147 | | -#define DMAALLST_WCOM2 (1 << 8)
|
| 148 | | -#define DMAALLST_HCOM2 (1 << 9)
|
| 149 | | -#define DMAALLST_DMABUSY2 (1 << 10)
|
| 150 | | -#define DMAALLST_WCOM3 (1 << 12)
|
| 151 | | -#define DMAALLST_HCOM3 (1 << 13)
|
| 152 | | -#define DMAALLST_DMABUSY3 (1 << 14)
|
| 153 | | -#define DMAALLST_CHAN0_MASK (0xF << 0)
|
| 154 | | -#define DMAALLST_CHAN1_MASK (0xF << 4)
|
| 155 | | -#define DMAALLST_CHAN2_MASK (0xF << 8)
|
| 156 | | -#define DMAALLST_CHAN3_MASK (0xF << 12)
|
| 157 | | -
|
| 158 | | -
|
| 159 | | -/////FMC/////
|
| 160 | | -#define FMCTRL0 (*((volatile uint32_t*)(0x39400000)))
|
| 161 | | -#define FMCTRL1 (*((volatile uint32_t*)(0x39400004)))
|
| 162 | | -#define FMCMD (*((volatile uint32_t*)(0x39400008)))
|
| 163 | | -#define FMADDR0 (*((volatile uint32_t*)(0x3940000C)))
|
| 164 | | -#define FMADDR1 (*((volatile uint32_t*)(0x39400010)))
|
| 165 | | -#define FMANUM (*((volatile uint32_t*)(0x3940002C)))
|
| 166 | | -#define FMDNUM (*((volatile uint32_t*)(0x39400030)))
|
| 167 | | -#define FMCSTAT (*((volatile uint32_t*)(0x39400048)))
|
| 168 | | -#define FMFIFO (*((volatile uint32_t*)(0x39400080)))
|
| 169 | | -#define RS_ECC_CTRL (*((volatile uint32_t*)(0x39400100)))
|
| 170 | | -#define FMCTRL0_ENABLEDMA (1 << 10)
|
| 171 | | -#define FMCTRL0_UNK1 (1 << 11)
|
| 172 | | -#define FMCTRL1_DOTRANSADDR (1 << 0)
|
| 173 | | -#define FMCTRL1_DOREADDATA (1 << 1)
|
| 174 | | -#define FMCTRL1_DOWRITEDATA (1 << 2)
|
| 175 | | -#define FMCTRL1_CLEARWFIFO (1 << 6)
|
| 176 | | -#define FMCTRL1_CLEARRFIFO (1 << 7)
|
| 177 | | -#define FMCSTAT_RBB (1 << 0)
|
| 178 | | -#define FMCSTAT_RBBDONE (1 << 1)
|
| 179 | | -#define FMCSTAT_CMDDONE (1 << 2)
|
| 180 | | -#define FMCSTAT_ADDRDONE (1 << 3)
|
| 181 | | -#define FMCSTAT_BANK0READY (1 << 4)
|
| 182 | | -#define FMCSTAT_BANK1READY (1 << 5)
|
| 183 | | -#define FMCSTAT_BANK2READY (1 << 6)
|
| 184 | | -#define FMCSTAT_BANK3READY (1 << 7)
|
| 185 | | -
|
| 186 | | -
|
| 187 | | -/////ECC/////
|
| 188 | | -#define ECC_DATA_PTR (*((volatile uint32_t*)(0x39E00004)))
|
| 189 | | -#define ECC_SPARE_PTR (*((volatile uint32_t*)(0x39E00008)))
|
| 190 | | -#define ECC_CTRL (*((volatile uint32_t*)(0x39E0000C)))
|
| 191 | | -#define ECC_RESULT (*((volatile uint32_t*)(0x39E00010)))
|
| 192 | | -#define ECC_UNK1 (*((volatile uint32_t*)(0x39E00014)))
|
| 193 | | -#define ECC_INT_CLR (*((volatile uint32_t*)(0x39E00040)))
|
| 194 | | -#define ECCCTRL_STARTDECODING (1 << 0)
|
| 195 | | -#define ECCCTRL_STARTENCODING (1 << 1)
|
| 196 | | -#define ECCCTRL_STARTDECNOSYND (1 << 2)
|
| 197 | | -
|
| 198 | | -
|
| 199 | | -/////CLICKWHEEL/////
|
| 200 | | -#define WHEEL00 (*((volatile uint32_t*)(0x3C200000)))
|
| 201 | | -#define WHEEL04 (*((volatile uint32_t*)(0x3C200004)))
|
| 202 | | -#define WHEEL08 (*((volatile uint32_t*)(0x3C200008)))
|
| 203 | | -#define WHEEL0C (*((volatile uint32_t*)(0x3C20000C)))
|
| 204 | | -#define WHEEL10 (*((volatile uint32_t*)(0x3C200010)))
|
| 205 | | -#define WHEELINT (*((volatile uint32_t*)(0x3C200014)))
|
| 206 | | -#define WHEELRX (*((volatile uint32_t*)(0x3C200018)))
|
| 207 | | -#define WHEELTX (*((volatile uint32_t*)(0x3C20001C)))
|
| 208 | | -
|
| 209 | | -
|
| 210 | | -/////AES/////
|
| 211 | | -#define AESCONTROL (*((volatile uint32_t*)(0x39800000)))
|
| 212 | | -#define AESGO (*((volatile uint32_t*)(0x39800004)))
|
| 213 | | -#define AESUNKREG0 (*((volatile uint32_t*)(0x39800008)))
|
| 214 | | -#define AESSTATUS (*((volatile uint32_t*)(0x3980000C)))
|
| 215 | | -#define AESUNKREG1 (*((volatile uint32_t*)(0x39800010)))
|
| 216 | | -#define AESKEYLEN (*((volatile uint32_t*)(0x39800014)))
|
| 217 | | -#define AESOUTSIZE (*((volatile uint32_t*)(0x39800018)))
|
| 218 | | -#define AESOUTADDR (*((volatile uint32_t*)(0x39800020)))
|
| 219 | | -#define AESINSIZE (*((volatile uint32_t*)(0x39800024)))
|
| 220 | | -#define AESINADDR (*((volatile uint32_t*)(0x39800028)))
|
| 221 | | -#define AESAUXSIZE (*((volatile uint32_t*)(0x3980002C)))
|
| 222 | | -#define AESAUXADDR (*((volatile uint32_t*)(0x39800030)))
|
| 223 | | -#define AESSIZE3 (*((volatile uint32_t*)(0x39800034)))
|
| 224 | | -#define AESKEY ((volatile uint32_t*)(0x3980004C))
|
| 225 | | -#define AESTYPE (*((volatile uint32_t*)(0x3980006C)))
|
| 226 | | -#define AESIV ((volatile uint32_t*)(0x39800074))
|
| 227 | | -#define AESTYPE2 (*((volatile uint32_t*)(0x39800088)))
|
| 228 | | -#define AESUNKREG2 (*((volatile uint32_t*)(0x3980008C)))
|
| 229 | | -
|
| 230 | | -/////HASH/////
|
| 231 | | -#define HASHCTRL (*((volatile uint32_t*)(0x3C600000)))
|
| 232 | | -#define HASHRESULT ((volatile uint32_t*)(0x3C600020))
|
| 233 | | -#define HASHDATAIN ((volatile uint32_t*)(0x3C600040))
|
| 234 | | -
|
| 235 | | -
|
| 236 | 40 | /////TIMER/////
|
| 237 | 41 | #define TACON (*((volatile uint32_t*)(0x3C700000)))
|
| 238 | 42 | #define TACMD (*((volatile uint32_t*)(0x3C700004)))
|
| — | — | @@ -291,10 +95,10 @@ |
| 292 | 96 |
|
| 293 | 97 |
|
| 294 | 98 | /////I2C/////
|
| 295 | | -#define IICCON (*((volatile uint32_t*)(0x3C900000)))
|
| 296 | | -#define IICSTAT (*((volatile uint32_t*)(0x3C900004)))
|
| 297 | | -#define IICADD (*((volatile uint32_t*)(0x3C900008)))
|
| 298 | | -#define IICDS (*((volatile uint32_t*)(0x3C90000C)))
|
| | 99 | +#define IICCON(bus) (*((volatile uint32_t*)(0x3C600000 + 0x300000 * (bus))))
|
| | 100 | +#define IICSTAT(bus) (*((volatile uint32_t*)(0x3C600004 + 0x300000 * (bus))))
|
| | 101 | +#define IICADD(bus) (*((volatile uint32_t*)(0x3C600008 + 0x300000 * (bus))))
|
| | 102 | +#define IICDS(bus) (*((volatile uint32_t*)(0x3C60000C + 0x300000 * (bus))))
|
| 299 | 103 |
|
| 300 | 104 |
|
| 301 | 105 | /////INTERRUPTS/////
|
| — | — | @@ -468,9 +272,16 @@ |
| 469 | 273 | #define VIC1VECTPRIORITY30 (*((volatile uint32_t*)(0x38E01278)))
|
| 470 | 274 | #define VIC1VECTPRIORITY31 (*((volatile uint32_t*)(0x38E0127C)))
|
| 471 | 275 | #define VIC1ADDRESS (*((volatile uint32_t*)(0x38E01F00)))
|
| | 276 | +
|
| | 277 | +
|
| | 278 | +/////CLOCK GATES/////
|
| | 279 | +#define CLOCKGATE_USB_1 2
|
| | 280 | +#define CLOCKGATE_USB_2 35
|
| | 281 | +
|
| | 282 | +
|
| | 283 | +/////INTERRUPTS/////
|
| 472 | 284 | #define IRQ_TIMER 8
|
| 473 | 285 | #define IRQ_USB_FUNC 19
|
| 474 | | -#define IRQ_IIC 0
|
| 475 | 286 |
|
| 476 | 287 |
|
| 477 | 288 | #endif
|
| Index: embios/trunk/usb/synopsysotg.c |
| — | — | @@ -32,6 +32,7 @@ |
| 33 | 33 | #include "synopsysotg.h"
|
| 34 | 34 | #include "util.h"
|
| 35 | 35 | #include "interrupt.h"
|
| | 36 | +#include "clockgates.h"
|
| 36 | 37 |
|
| 37 | 38 |
|
| 38 | 39 | struct ep_type
|
| — | — | @@ -357,8 +358,8 @@ |
| 358 | 359 | wakeup_init(&endpoints[i].complete);
|
| 359 | 360 |
|
| 360 | 361 | /* Enable USB clock */
|
| 361 | | - PWRCON &= ~0x4000;
|
| 362 | | - PWRCONEXT &= ~0x800;
|
| | 362 | + clockgate_enable(CLOCKGATE_USB_1, true);
|
| | 363 | + clockgate_enable(CLOCKGATE_USB_2, true);
|
| 363 | 364 | PCGCCTL = 0;
|
| 364 | 365 |
|
| 365 | 366 | /* unmask irq */
|
