| Index: embios/branches/4g_compat/init.c |
| — | — | @@ -28,6 +28,8 @@ |
| 29 | 29 |
|
| 30 | 30 | static const char welcomestring[] INITCONST_ATTR = "emBIOS v" VERSION "\n";
|
| 31 | 31 |
|
| | 32 | +#include "s5l8720.h"
|
| | 33 | +
|
| 32 | 34 | void init() INITCODE_ATTR;
|
| 33 | 35 | void init()
|
| 34 | 36 | {
|
| — | — | @@ -36,10 +38,7 @@ |
| 37 | 39 | cputs(1, welcomestring);
|
| 38 | 40 | while(1)
|
| 39 | 41 | {
|
| 40 | | - uint8_t x = accel_get_axis(0);
|
| 41 | | - uint8_t y = accel_get_axis(1);
|
| 42 | | - uint8_t z = accel_get_axis(2);
|
| 43 | | - cprintf(1, "x:%d y:%d z:%d\n", x, y, z);
|
| | 42 | + cprintf(1, "TBCNT: %d \n", TBCNT);
|
| 44 | 43 | }
|
| 45 | 44 |
|
| 46 | 45 | }
|
| Index: embios/branches/4g_compat/target/ipodnano4g/timer.c |
| — | — | @@ -29,5 +29,30 @@ |
| 30 | 30 |
|
| 31 | 31 | void setup_tick()
|
| 32 | 32 | {
|
| | 33 | + int cycles = SYSTEM_TICK / 100;
|
| | 34 | +
|
| | 35 | + TACMD = (1 << 1); /* TA_CLR */
|
| | 36 | + TBCMD = (1 << 1); /* TB_CLR */
|
| | 37 | + TCCMD = (1 << 1); /* TC_CLR */
|
| | 38 | + TDCMD = (1 << 1); /* TD_CLR */
|
| | 39 | + TECMD = (1 << 1); /* TE_CLR */
|
| | 40 | + TFCMD = (1 << 1); /* TF_CLR */
|
| | 41 | + TGCMD = (1 << 1); /* TG_CLR */
|
| | 42 | + THCMD = (1 << 1); /* TH_CLR */
|
| | 43 | +
|
| | 44 | + /* configure timer for 10 kHz */
|
| | 45 | + TBPRE = 208 - 1; /* prescaler */
|
| | 46 | + TBCON = (0 << 13) | /* TB_INT1_EN */
|
| | 47 | + (1 << 12) | /* TB_INT0_EN */
|
| | 48 | + (0 << 11) | /* TB_START */
|
| | 49 | + (3 << 8) | /* TB_CS = PCLK / 64 */
|
| | 50 | + (0 << 4); /* TB_MODE_SEL = interval mode */
|
| | 51 | + TBDATA0 = cycles; /* set interval period */
|
| | 52 | + TBCMD = (1 << 0); /* TB_EN */
|
| 33 | 53 | }
|
| 34 | 54 |
|
| | 55 | +void INT_TIMERB(void)
|
| | 56 | +{
|
| | 57 | + TBCON = TBCON;
|
| | 58 | + scheduler_switch(-1);
|
| | 59 | +}
|
| Index: embios/branches/4g_compat/target/ipodnano4g/crt0.S |
| — | — | @@ -84,7 +84,7 @@ |
| 85 | 85 | ldr sp, =_abortstackend
|
| 86 | 86 | msr cpsr_c, #0xdb
|
| 87 | 87 | ldr sp, =_abortstackend
|
| 88 | | - msr cpsr_c, #0xd3
|
| | 88 | + msr cpsr_c, #0xdf
|
| 89 | 89 | ldr sp, =_initstackend
|
| 90 | 90 | bl init
|
| 91 | 91 | bl context_switch
|
| Index: embios/branches/4g_compat/target/ipodnano4g/s5l8720.h |
| — | — | @@ -269,6 +269,30 @@ |
| 270 | 270 | #define TDDATA1 (*((volatile uint32_t*)(0x3C70006C)))
|
| 271 | 271 | #define TDPRE (*((volatile uint32_t*)(0x3C700070)))
|
| 272 | 272 | #define TDCNT (*((volatile uint32_t*)(0x3C700074)))
|
| | 273 | +#define TECON (*((volatile uint32_t*)(0x3C7000A0)))
|
| | 274 | +#define TECMD (*((volatile uint32_t*)(0x3C7000A4)))
|
| | 275 | +#define TEDATA0 (*((volatile uint32_t*)(0x3C7000A8)))
|
| | 276 | +#define TEDATA1 (*((volatile uint32_t*)(0x3C7000AC)))
|
| | 277 | +#define TEPRE (*((volatile uint32_t*)(0x3C7000B0)))
|
| | 278 | +#define TECNT (*((volatile uint32_t*)(0x3C7000B4)))
|
| | 279 | +#define TFCON (*((volatile uint32_t*)(0x3C7000C0)))
|
| | 280 | +#define TFCMD (*((volatile uint32_t*)(0x3C7000C4)))
|
| | 281 | +#define TFDATA0 (*((volatile uint32_t*)(0x3C7000C8)))
|
| | 282 | +#define TFDATA1 (*((volatile uint32_t*)(0x3C7000CC)))
|
| | 283 | +#define TFPRE (*((volatile uint32_t*)(0x3C7000D0)))
|
| | 284 | +#define TFCNT (*((volatile uint32_t*)(0x3C7000D4)))
|
| | 285 | +#define TGCON (*((volatile uint32_t*)(0x3C7000E0)))
|
| | 286 | +#define TGCMD (*((volatile uint32_t*)(0x3C7000E4)))
|
| | 287 | +#define TGDATA0 (*((volatile uint32_t*)(0x3C7000E8)))
|
| | 288 | +#define TGDATA1 (*((volatile uint32_t*)(0x3C7000EC)))
|
| | 289 | +#define TGPRE (*((volatile uint32_t*)(0x3C7000F0)))
|
| | 290 | +#define TGCNT (*((volatile uint32_t*)(0x3C7000F4)))
|
| | 291 | +#define THCON (*((volatile uint32_t*)(0x3C700100)))
|
| | 292 | +#define THCMD (*((volatile uint32_t*)(0x3C700104)))
|
| | 293 | +#define THDATA0 (*((volatile uint32_t*)(0x3C700108)))
|
| | 294 | +#define THDATA1 (*((volatile uint32_t*)(0x3C70010C)))
|
| | 295 | +#define THPRE (*((volatile uint32_t*)(0x3C700110)))
|
| | 296 | +#define THCNT (*((volatile uint32_t*)(0x3C700114)))
|
| 273 | 297 | uint64_t read_5usec_timer();
|
| 274 | 298 | #define FIVE_USEC_TIMER (read_5usec_timer()) /* 64bit 5usec timer */
|
| 275 | 299 |
|
| Index: embios/branches/4g_compat/target/ipodnano4g/interrupt.c |
| — | — | @@ -38,6 +38,10 @@ |
| 39 | 39 | default_interrupt(INT_TIMERB);
|
| 40 | 40 | default_interrupt(INT_TIMERC);
|
| 41 | 41 | default_interrupt(INT_TIMERD);
|
| | 42 | +default_interrupt(INT_TIMERE);
|
| | 43 | +default_interrupt(INT_TIMERF);
|
| | 44 | +default_interrupt(INT_TIMERG);
|
| | 45 | +default_interrupt(INT_TIMERH);
|
| 42 | 46 | default_interrupt(INT_DMA0);
|
| 43 | 47 | default_interrupt(INT_DMA1);
|
| 44 | 48 | default_interrupt(INT_DMA2);
|
| — | — | @@ -80,7 +84,7 @@ |
| 81 | 85 |
|
| 82 | 86 | static void (* const timervector[])(void) IDATA_ATTR =
|
| 83 | 87 | {
|
| 84 | | - INT_TIMERA,INT_TIMERB,INT_TIMERC,INT_TIMERD
|
| | 88 | + INT_TIMERA,INT_TIMERB,INT_TIMERC,INT_TIMERD,INT_TIMERE,INT_TIMERF,INT_TIMERG,INT_TIMERH
|
| 85 | 89 | };
|
| 86 | 90 |
|
| 87 | 91 | void INT_TIMER(void) ICODE_ATTR;
|
| — | — | @@ -90,6 +94,10 @@ |
| 91 | 95 | if (TBCON & 0x00038000) timervector[1]();
|
| 92 | 96 | if (TCCON & 0x00038000) timervector[2]();
|
| 93 | 97 | if (TDCON & 0x00038000) timervector[3]();
|
| | 98 | + if (TECON & 0x00038000) timervector[4]();
|
| | 99 | + if (TFCON & 0x00038000) timervector[5]();
|
| | 100 | + if (TGCON & 0x00038000) timervector[6]();
|
| | 101 | + if (THCON & 0x00038000) timervector[7]();
|
| 94 | 102 | }
|
| 95 | 103 |
|
| 96 | 104 | static void (* const dmavector[])(void) IDATA_ATTR =
|
