| Index: embios/trunk/target/ipodclassic/storage_ata.c |
| — | — | @@ -41,15 +41,15 @@ |
| 42 | 42 |
|
| 43 | 43 | static uint16_t ata_read_cbr(uint32_t volatile* reg)
|
| 44 | 44 | {
|
| 45 | | - while (!(ATA_PIO_READY & 2)) sleep(0);
|
| | 45 | + while (!(ATA_PIO_READY & 2)) yield();
|
| 46 | 46 | volatile uint32_t dummy = *reg;
|
| 47 | | - while (!(ATA_PIO_READY & 1)) sleep(0);
|
| | 47 | + while (!(ATA_PIO_READY & 1)) yield();
|
| 48 | 48 | return ATA_PIO_RDATA;
|
| 49 | 49 | }
|
| 50 | 50 |
|
| 51 | 51 | static void ata_write_cbr(uint32_t volatile* reg, uint16_t data)
|
| 52 | 52 | {
|
| 53 | | - while (!(ATA_PIO_READY & 2)) sleep(0);
|
| | 53 | + while (!(ATA_PIO_READY & 2)) yield();
|
| 54 | 54 | *reg = data;
|
| 55 | 55 | }
|
| 56 | 56 |
|
| — | — | @@ -61,7 +61,6 @@ |
| 62 | 62 | uint8_t csd = ata_read_cbr(&ATA_PIO_CSD);
|
| 63 | 63 | if (!(csd & BIT(7))) return 0;
|
| 64 | 64 | if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(0);
|
| 65 | | - sleep(100);
|
| 66 | 65 | }
|
| 67 | 66 | }
|
| 68 | 67 |
|
| — | — | @@ -74,7 +73,6 @@ |
| 75 | 74 | uint8_t dad = ata_read_cbr(&ATA_PIO_DAD);
|
| 76 | 75 | if (dad & BIT(6)) return 0;
|
| 77 | 76 | if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(1);
|
| 78 | | - sleep(100);
|
| 79 | 77 | }
|
| 80 | 78 | }
|
| 81 | 79 |
|
| — | — | @@ -88,7 +86,6 @@ |
| 89 | 87 | if (dad & BIT(0)) RET_ERR(1);
|
| 90 | 88 | if ((dad & (BIT(7) | BIT(3))) == BIT(3)) return 0;
|
| 91 | 89 | if (TIMEOUT_EXPIRED(startusec, timeout)) RET_ERR(2);
|
| 92 | | - sleep(100);
|
| 93 | 90 | }
|
| 94 | 91 | }
|
| 95 | 92 |
|
| — | — | @@ -120,6 +117,17 @@ |
| 121 | 118 | ata_last_activity_value = USEC_TIMER;
|
| 122 | 119 | }
|
| 123 | 120 |
|
| | 121 | +int ata_set_feature(uint32_t feature, uint32_t param)
|
| | 122 | +{
|
| | 123 | + PASS_RC(ata_wait_for_rdy(500000), 1, 0);
|
| | 124 | + ata_write_cbr(&ATA_PIO_DVR, 0);
|
| | 125 | + ata_write_cbr(&ATA_PIO_FED, 3);
|
| | 126 | + ata_write_cbr(&ATA_PIO_SCR, param);
|
| | 127 | + ata_write_cbr(&ATA_PIO_CSD, feature);
|
| | 128 | + PASS_RC(ata_wait_for_rdy(500000), 1, 1);
|
| | 129 | + return 0;
|
| | 130 | +}
|
| | 131 | +
|
| 124 | 132 | int ata_power_up()
|
| 125 | 133 | {
|
| 126 | 134 | ata_set_active();
|
| — | — | @@ -200,12 +208,9 @@ |
| 201 | 209 | }
|
| 202 | 210 | }
|
| 203 | 211 | ata_dma = param ? true : false;
|
| 204 | | - PASS_RC(ata_wait_for_rdy(500000), 2, 1);
|
| 205 | | - ata_write_cbr(&ATA_PIO_DVR, 0);
|
| 206 | | - ata_write_cbr(&ATA_PIO_FED, 3);
|
| 207 | | - ata_write_cbr(&ATA_PIO_SCR, param);
|
| 208 | | - ata_write_cbr(&ATA_PIO_CSD, 0xef);
|
| 209 | | - PASS_RC(ata_wait_for_rdy(500000), 2, 2);
|
| | 212 | + PASS_RC(ata_set_feature(0xef, param), 2, 1);
|
| | 213 | + if (ata_identify_data[82] & BIT(5)) PASS_RC(ata_set_feature(2, 0), 2, 2);
|
| | 214 | + if (ata_identify_data[82] & BIT(6)) PASS_RC(ata_set_feature(0x55, 0), 2, 3);
|
| 210 | 215 | ATA_PIO_TIME = piotime;
|
| 211 | 216 | ATA_MDMA_TIME = mdmatime;
|
| 212 | 217 | ATA_UDMA_TIME = udmatime;
|
| — | — | @@ -223,7 +228,7 @@ |
| 224 | 229 | ata_wait_for_rdy(1000000);
|
| 225 | 230 | sleep(30000);
|
| 226 | 231 | ATA_CONTROL = 0;
|
| 227 | | - while (!(ATA_CONTROL & BIT(1))) sleep(0);
|
| | 232 | + while (!(ATA_CONTROL & BIT(1))) yield();
|
| 228 | 233 | clockgate_enable(5, false);
|
| 229 | 234 | i2c_sendbyte(0, 0xe6, 0x1b, 0);
|
| 230 | 235 | }
|
| — | — | @@ -238,7 +243,7 @@ |
| 239 | 244 | ATA_COMMAND = BIT(1);
|
| 240 | 245 | while (count)
|
| 241 | 246 | {
|
| 242 | | - uint32_t cnt = MIN(32, count);
|
| | 247 | + uint32_t cnt = MIN(ata_lba48 ? 8192 : 32, count);
|
| 243 | 248 | PASS_RC(ata_wait_for_rdy(100000), 2, 0);
|
| 244 | 249 | ata_write_cbr(&ATA_PIO_DVR, 0);
|
| 245 | 250 | if (ata_lba48)
|
