| Index: umsboot/usb/synopsysotg.c |
| — | — | @@ -66,7 +66,7 @@ |
| 67 | 67 | DOEPCTL0 = 0x8000; /* EP0 OUT ACTIVE */
|
| 68 | 68 | DOEPTSIZ0 = 0x20080040; /* EP0 OUT Transfer Size:
|
| 69 | 69 | 64 Bytes, 1 Packet, 1 Setup Packet */
|
| 70 | | - DOEPDMA0 = (uint32_t)&ctrlreq;
|
| | 70 | + DOEPDMA0 = &ctrlreq;
|
| 71 | 71 | DOEPCTL0 |= 0x84000000; /* EP0 OUT ENABLE CLEARNAK */
|
| 72 | 72 | if (reinit)
|
| 73 | 73 | {
|
| — | — | @@ -128,18 +128,19 @@ |
| 129 | 129 |
|
| 130 | 130 | static void usb_reset(void)
|
| 131 | 131 | {
|
| 132 | | - volatile int i;
|
| 133 | | -
|
| 134 | 132 | DCTL = 0x802; /* Soft Disconnect */
|
| 135 | 133 |
|
| 136 | 134 | OPHYPWR = 0; /* PHY: Power up */
|
| | 135 | + udelay(10);
|
| 137 | 136 | OPHYUNK1 = 1;
|
| 138 | 137 | OPHYUNK2 = 0xE3F;
|
| 139 | | - OPHYCLK = SYNOPSYSOTG_CLOCK;
|
| 140 | 138 | ORSTCON = 1; /* PHY: Assert Software Reset */
|
| 141 | 139 | udelay(10);
|
| 142 | 140 | ORSTCON = 0; /* PHY: Deassert Software Reset */
|
| | 141 | + udelay(10);
|
| 143 | 142 | OPHYUNK3 = 0x600;
|
| | 143 | + OPHYCLK = SYNOPSYSOTG_CLOCK;
|
| | 144 | + udelay(400);
|
| 144 | 145 |
|
| 145 | 146 | GRSTCTL = 1; /* OTG: Assert Software Reset */
|
| 146 | 147 | while (GRSTCTL & 1); /* Wait for OTG to ack reset */
|
| — | — | @@ -189,7 +190,6 @@ |
| 190 | 191 | {
|
| 191 | 192 | if (epints & 1) /* Transfer completed */
|
| 192 | 193 | {
|
| 193 | | - invalidate_dcache();
|
| 194 | 194 | int bytes = endpoints[i].size - (DIEPTSIZ(i) & 0x3FFFF);
|
| 195 | 195 | if (endpoints[i].busy)
|
| 196 | 196 | {
|
| — | — | @@ -219,7 +219,6 @@ |
| 220 | 220 | {
|
| 221 | 221 | if (epints & 1) /* Transfer completed */
|
| 222 | 222 | {
|
| 223 | | - invalidate_dcache();
|
| 224 | 223 | int bytes = endpoints[i].size - (DOEPTSIZ(i) & 0x3FFFF);
|
| 225 | 224 | if (endpoints[i].busy)
|
| 226 | 225 | {
|
| — | — | @@ -241,7 +240,7 @@ |
| 242 | 241 | if (!i)
|
| 243 | 242 | {
|
| 244 | 243 | DOEPTSIZ0 = 0x20080040;
|
| 245 | | - DOEPDMA0 = (uint32_t)&ctrlreq;
|
| | 244 | + DOEPDMA0 = &ctrlreq;
|
| 246 | 245 | DOEPCTL0 |= 0x84000000;
|
| 247 | 246 | }
|
| 248 | 247 | DOEPINT(i) = epints;
|
| — | — | @@ -265,12 +264,12 @@ |
| 266 | 265 | if (!length)
|
| 267 | 266 | {
|
| 268 | 267 | DIEPTSIZ(ep) = 1 << 19; /* one empty packet */
|
| 269 | | - DIEPDMA(ep) = 0x10000000; /* dummy address */
|
| | 268 | + DIEPDMA(ep) = NULL; /* dummy address */
|
| 270 | 269 | }
|
| 271 | 270 | else
|
| 272 | 271 | {
|
| 273 | 272 | DIEPTSIZ(ep) = length | (packets << 19);
|
| 274 | | - DIEPDMA(ep) = (uint32_t)ptr;
|
| | 273 | + DIEPDMA(ep) = ptr;
|
| 275 | 274 | }
|
| 276 | 275 | clean_dcache();
|
| 277 | 276 | DIEPCTL(ep) |= 0x84000000; /* EPx OUT ENABLE CLEARNAK */
|
| — | — | @@ -287,14 +286,14 @@ |
| 288 | 287 | if (!length)
|
| 289 | 288 | {
|
| 290 | 289 | DOEPTSIZ(ep) = 1 << 19; /* one empty packet */
|
| 291 | | - DOEPDMA(ep) = 0x10000000; /* dummy address */
|
| | 290 | + DOEPDMA(ep) = NULL; /* dummy address */
|
| 292 | 291 | }
|
| 293 | 292 | else
|
| 294 | 293 | {
|
| 295 | 294 | DOEPTSIZ(ep) = length | (packets << 19);
|
| 296 | | - DOEPDMA(ep) = (uint32_t)ptr;
|
| | 295 | + DOEPDMA(ep) = ptr;
|
| 297 | 296 | }
|
| 298 | | - clean_dcache();
|
| | 297 | + invalidate_dcache();
|
| 299 | 298 | DOEPCTL(ep) |= 0x84000000; /* EPx OUT ENABLE CLEARNAK */
|
| 300 | 299 | }
|
| 301 | 300 |
|
| — | — | @@ -361,9 +360,11 @@ |
| 362 | 361 | {
|
| 363 | 362 | DCTL = 0x802; /* Soft Disconnect */
|
| 364 | 363 |
|
| 365 | | - ORSTCON = 1; /* Put the PHY into reset (needed to get current down) */
|
| | 364 | + OPHYPWR = 0xF; /* PHY: Power down */
|
| | 365 | + udelay(10);
|
| | 366 | + ORSTCON = 7; /* Put the PHY into reset (needed to get current down) */
|
| | 367 | + udelay(10);
|
| 366 | 368 | PCGCCTL = 1; /* Shut down PHY clock */
|
| 367 | | - OPHYPWR = 0xF; /* PHY: Power down */
|
| 368 | 369 |
|
| 369 | 370 | clockgate_enable(CLOCKGATE_USB_1, false);
|
| 370 | 371 | clockgate_enable(CLOCKGATE_USB_2, false);
|
| Index: umsboot/usb/synopsysotg.h |
| — | — | @@ -31,328 +31,328 @@ |
| 32 | 32 | #ifdef TARGET_ipodnano2g
|
| 33 | 33 | #include "target/ipodnano2g/s5l8701.h"
|
| 34 | 34 | #endif
|
| 35 | | -#ifdef TARGET_ipodclassic
|
| | 35 | +#if defined(TARGET_ipodnano3g) || defined(TARGET_ipodclassic)
|
| 36 | 36 | #include "target/ipodclassic/s5l8702.h"
|
| 37 | 37 | #endif
|
| 38 | | -#ifdef TARGET_ipodnano4g
|
| | 38 | +#if defined(TARGET_ipodnano4g) || defined(TARGET_ipodtouch2g)
|
| 39 | 39 | #include "target/ipodnano4g/s5l8720.h"
|
| 40 | 40 | #endif
|
| 41 | 41 |
|
| 42 | 42 |
|
| 43 | 43 | /*** OTG PHY CONTROL REGISTERS ***/
|
| 44 | | -#define OPHYPWR (*((volatile uint32_t*)(PHYBASE + 0x000)))
|
| 45 | | -#define OPHYCLK (*((volatile uint32_t*)(PHYBASE + 0x004)))
|
| 46 | | -#define ORSTCON (*((volatile uint32_t*)(PHYBASE + 0x008)))
|
| 47 | | -#define OPHYUNK3 (*((volatile uint32_t*)(PHYBASE + 0x018)))
|
| 48 | | -#define OPHYUNK1 (*((volatile uint32_t*)(PHYBASE + 0x01c)))
|
| 49 | | -#define OPHYUNK2 (*((volatile uint32_t*)(PHYBASE + 0x044)))
|
| | 44 | +#define OPHYPWR (*((uint32_t volatile*)(PHYBASE + 0x000)))
|
| | 45 | +#define OPHYCLK (*((uint32_t volatile*)(PHYBASE + 0x004)))
|
| | 46 | +#define ORSTCON (*((uint32_t volatile*)(PHYBASE + 0x008)))
|
| | 47 | +#define OPHYUNK3 (*((uint32_t volatile*)(PHYBASE + 0x018)))
|
| | 48 | +#define OPHYUNK1 (*((uint32_t volatile*)(PHYBASE + 0x01c)))
|
| | 49 | +#define OPHYUNK2 (*((uint32_t volatile*)(PHYBASE + 0x044)))
|
| 50 | 50 |
|
| 51 | 51 | /*** OTG LINK CORE REGISTERS ***/
|
| 52 | 52 | /* Core Global Registers */
|
| 53 | | -#define GOTGCTL (*((volatile uint32_t*)(OTGBASE + 0x000)))
|
| 54 | | -#define GOTGINT (*((volatile uint32_t*)(OTGBASE + 0x004)))
|
| 55 | | -#define GAHBCFG (*((volatile uint32_t*)(OTGBASE + 0x008)))
|
| 56 | | -#define GUSBCFG (*((volatile uint32_t*)(OTGBASE + 0x00C)))
|
| 57 | | -#define GRSTCTL (*((volatile uint32_t*)(OTGBASE + 0x010)))
|
| 58 | | -#define GINTSTS (*((volatile uint32_t*)(OTGBASE + 0x014)))
|
| 59 | | -#define GINTMSK (*((volatile uint32_t*)(OTGBASE + 0x018)))
|
| 60 | | -#define GRXSTSR (*((volatile uint32_t*)(OTGBASE + 0x01C)))
|
| 61 | | -#define GRXSTSP (*((volatile uint32_t*)(OTGBASE + 0x020)))
|
| 62 | | -#define GRXFSIZ (*((volatile uint32_t*)(OTGBASE + 0x024)))
|
| 63 | | -#define GNPTXFSIZ (*((volatile uint32_t*)(OTGBASE + 0x028)))
|
| 64 | | -#define GNPTXSTS (*((volatile uint32_t*)(OTGBASE + 0x02C)))
|
| 65 | | -#define HPTXFSIZ (*((volatile uint32_t*)(OTGBASE + 0x100)))
|
| 66 | | -#define DPTXFSIZ(x) (*((volatile uint32_t*)(OTGBASE + 0x100 + 4 * (x))))
|
| 67 | | -#define DPTXFSIZ1 (*((volatile uint32_t*)(OTGBASE + 0x104)))
|
| 68 | | -#define DPTXFSIZ2 (*((volatile uint32_t*)(OTGBASE + 0x108)))
|
| 69 | | -#define DPTXFSIZ3 (*((volatile uint32_t*)(OTGBASE + 0x10C)))
|
| 70 | | -#define DPTXFSIZ4 (*((volatile uint32_t*)(OTGBASE + 0x110)))
|
| 71 | | -#define DPTXFSIZ5 (*((volatile uint32_t*)(OTGBASE + 0x114)))
|
| 72 | | -#define DPTXFSIZ6 (*((volatile uint32_t*)(OTGBASE + 0x118)))
|
| 73 | | -#define DPTXFSIZ7 (*((volatile uint32_t*)(OTGBASE + 0x11C)))
|
| 74 | | -#define DPTXFSIZ8 (*((volatile uint32_t*)(OTGBASE + 0x120)))
|
| 75 | | -#define DPTXFSIZ9 (*((volatile uint32_t*)(OTGBASE + 0x124)))
|
| 76 | | -#define DPTXFSIZ10 (*((volatile uint32_t*)(OTGBASE + 0x128)))
|
| 77 | | -#define DPTXFSIZ11 (*((volatile uint32_t*)(OTGBASE + 0x12C)))
|
| 78 | | -#define DPTXFSIZ12 (*((volatile uint32_t*)(OTGBASE + 0x130)))
|
| 79 | | -#define DPTXFSIZ13 (*((volatile uint32_t*)(OTGBASE + 0x134)))
|
| 80 | | -#define DPTXFSIZ14 (*((volatile uint32_t*)(OTGBASE + 0x138)))
|
| 81 | | -#define DPTXFSIZ15 (*((volatile uint32_t*)(OTGBASE + 0x13C)))
|
| | 53 | +#define GOTGCTL (*((uint32_t volatile*)(OTGBASE + 0x000)))
|
| | 54 | +#define GOTGINT (*((uint32_t volatile*)(OTGBASE + 0x004)))
|
| | 55 | +#define GAHBCFG (*((uint32_t volatile*)(OTGBASE + 0x008)))
|
| | 56 | +#define GUSBCFG (*((uint32_t volatile*)(OTGBASE + 0x00C)))
|
| | 57 | +#define GRSTCTL (*((uint32_t volatile*)(OTGBASE + 0x010)))
|
| | 58 | +#define GINTSTS (*((uint32_t volatile*)(OTGBASE + 0x014)))
|
| | 59 | +#define GINTMSK (*((uint32_t volatile*)(OTGBASE + 0x018)))
|
| | 60 | +#define GRXSTSR (*((uint32_t volatile*)(OTGBASE + 0x01C)))
|
| | 61 | +#define GRXSTSP (*((uint32_t volatile*)(OTGBASE + 0x020)))
|
| | 62 | +#define GRXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x024)))
|
| | 63 | +#define GNPTXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x028)))
|
| | 64 | +#define GNPTXSTS (*((uint32_t volatile*)(OTGBASE + 0x02C)))
|
| | 65 | +#define HPTXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x100)))
|
| | 66 | +#define DPTXFSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x100 + 4 * (x))))
|
| | 67 | +#define DPTXFSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x104)))
|
| | 68 | +#define DPTXFSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x108)))
|
| | 69 | +#define DPTXFSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x10C)))
|
| | 70 | +#define DPTXFSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x110)))
|
| | 71 | +#define DPTXFSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x114)))
|
| | 72 | +#define DPTXFSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x118)))
|
| | 73 | +#define DPTXFSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x11C)))
|
| | 74 | +#define DPTXFSIZ8 (*((uint32_t volatile*)(OTGBASE + 0x120)))
|
| | 75 | +#define DPTXFSIZ9 (*((uint32_t volatile*)(OTGBASE + 0x124)))
|
| | 76 | +#define DPTXFSIZ10 (*((uint32_t volatile*)(OTGBASE + 0x128)))
|
| | 77 | +#define DPTXFSIZ11 (*((uint32_t volatile*)(OTGBASE + 0x12C)))
|
| | 78 | +#define DPTXFSIZ12 (*((uint32_t volatile*)(OTGBASE + 0x130)))
|
| | 79 | +#define DPTXFSIZ13 (*((uint32_t volatile*)(OTGBASE + 0x134)))
|
| | 80 | +#define DPTXFSIZ14 (*((uint32_t volatile*)(OTGBASE + 0x138)))
|
| | 81 | +#define DPTXFSIZ15 (*((uint32_t volatile*)(OTGBASE + 0x13C)))
|
| 82 | 82 |
|
| 83 | 83 | /*** HOST MODE REGISTERS ***/
|
| 84 | 84 | /* Host Global Registers */
|
| 85 | | -#define HCFG (*((volatile uint32_t*)(OTGBASE + 0x400)))
|
| 86 | | -#define HFIR (*((volatile uint32_t*)(OTGBASE + 0x404)))
|
| 87 | | -#define HFNUM (*((volatile uint32_t*)(OTGBASE + 0x408)))
|
| 88 | | -#define HPTXSTS (*((volatile uint32_t*)(OTGBASE + 0x410)))
|
| 89 | | -#define HAINT (*((volatile uint32_t*)(OTGBASE + 0x414)))
|
| 90 | | -#define HAINTMSK (*((volatile uint32_t*)(OTGBASE + 0x418)))
|
| | 85 | +#define HCFG (*((uint32_t volatile*)(OTGBASE + 0x400)))
|
| | 86 | +#define HFIR (*((uint32_t volatile*)(OTGBASE + 0x404)))
|
| | 87 | +#define HFNUM (*((uint32_t volatile*)(OTGBASE + 0x408)))
|
| | 88 | +#define HPTXSTS (*((uint32_t volatile*)(OTGBASE + 0x410)))
|
| | 89 | +#define HAINT (*((uint32_t volatile*)(OTGBASE + 0x414)))
|
| | 90 | +#define HAINTMSK (*((uint32_t volatile*)(OTGBASE + 0x418)))
|
| 91 | 91 |
|
| 92 | 92 | /* Host Port Control and Status Registers */
|
| 93 | | -#define HPRT (*((volatile uint32_t*)(OTGBASE + 0x440)))
|
| | 93 | +#define HPRT (*((uint32_t volatile*)(OTGBASE + 0x440)))
|
| 94 | 94 |
|
| 95 | 95 | /* Host Channel-Specific Registers */
|
| 96 | | -#define HCCHAR(x) (*((volatile uint32_t*)(OTGBASE + 0x500 + 0x20 * (x))))
|
| 97 | | -#define HCSPLT(x) (*((volatile uint32_t*)(OTGBASE + 0x504 + 0x20 * (x))))
|
| 98 | | -#define HCINT(x) (*((volatile uint32_t*)(OTGBASE + 0x508 + 0x20 * (x))))
|
| 99 | | -#define HCINTMSK(x) (*((volatile uint32_t*)(OTGBASE + 0x50C + 0x20 * (x))))
|
| 100 | | -#define HCTSIZ(x) (*((volatile uint32_t*)(OTGBASE + 0x510 + 0x20 * (x))))
|
| 101 | | -#define HCDMA(x) (*((volatile uint32_t*)(OTGBASE + 0x514 + 0x20 * (x))))
|
| 102 | | -#define HCCHAR0 (*((volatile uint32_t*)(OTGBASE + 0x500)))
|
| 103 | | -#define HCSPLT0 (*((volatile uint32_t*)(OTGBASE + 0x504)))
|
| 104 | | -#define HCINT0 (*((volatile uint32_t*)(OTGBASE + 0x508)))
|
| 105 | | -#define HCINTMSK0 (*((volatile uint32_t*)(OTGBASE + 0x50C)))
|
| 106 | | -#define HCTSIZ0 (*((volatile uint32_t*)(OTGBASE + 0x510)))
|
| 107 | | -#define HCDMA0 (*((volatile uint32_t*)(OTGBASE + 0x514)))
|
| 108 | | -#define HCCHAR1 (*((volatile uint32_t*)(OTGBASE + 0x520)))
|
| 109 | | -#define HCSPLT1 (*((volatile uint32_t*)(OTGBASE + 0x524)))
|
| 110 | | -#define HCINT1 (*((volatile uint32_t*)(OTGBASE + 0x528)))
|
| 111 | | -#define HCINTMSK1 (*((volatile uint32_t*)(OTGBASE + 0x52C)))
|
| 112 | | -#define HCTSIZ1 (*((volatile uint32_t*)(OTGBASE + 0x530)))
|
| 113 | | -#define HCDMA1 (*((volatile uint32_t*)(OTGBASE + 0x534)))
|
| 114 | | -#define HCCHAR2 (*((volatile uint32_t*)(OTGBASE + 0x540)))
|
| 115 | | -#define HCSPLT2 (*((volatile uint32_t*)(OTGBASE + 0x544)))
|
| 116 | | -#define HCINT2 (*((volatile uint32_t*)(OTGBASE + 0x548)))
|
| 117 | | -#define HCINTMSK2 (*((volatile uint32_t*)(OTGBASE + 0x54C)))
|
| 118 | | -#define HCTSIZ2 (*((volatile uint32_t*)(OTGBASE + 0x550)))
|
| 119 | | -#define HCDMA2 (*((volatile uint32_t*)(OTGBASE + 0x554)))
|
| 120 | | -#define HCCHAR3 (*((volatile uint32_t*)(OTGBASE + 0x560)))
|
| 121 | | -#define HCSPLT3 (*((volatile uint32_t*)(OTGBASE + 0x564)))
|
| 122 | | -#define HCINT3 (*((volatile uint32_t*)(OTGBASE + 0x568)))
|
| 123 | | -#define HCINTMSK3 (*((volatile uint32_t*)(OTGBASE + 0x56C)))
|
| 124 | | -#define HCTSIZ3 (*((volatile uint32_t*)(OTGBASE + 0x570)))
|
| 125 | | -#define HCDMA3 (*((volatile uint32_t*)(OTGBASE + 0x574)))
|
| 126 | | -#define HCCHAR4 (*((volatile uint32_t*)(OTGBASE + 0x580)))
|
| 127 | | -#define HCSPLT4 (*((volatile uint32_t*)(OTGBASE + 0x584)))
|
| 128 | | -#define HCINT4 (*((volatile uint32_t*)(OTGBASE + 0x588)))
|
| 129 | | -#define HCINTMSK4 (*((volatile uint32_t*)(OTGBASE + 0x58C)))
|
| 130 | | -#define HCTSIZ4 (*((volatile uint32_t*)(OTGBASE + 0x590)))
|
| 131 | | -#define HCDMA4 (*((volatile uint32_t*)(OTGBASE + 0x594)))
|
| 132 | | -#define HCCHAR5 (*((volatile uint32_t*)(OTGBASE + 0x5A0)))
|
| 133 | | -#define HCSPLT5 (*((volatile uint32_t*)(OTGBASE + 0x5A4)))
|
| 134 | | -#define HCINT5 (*((volatile uint32_t*)(OTGBASE + 0x5A8)))
|
| 135 | | -#define HCINTMSK5 (*((volatile uint32_t*)(OTGBASE + 0x5AC)))
|
| 136 | | -#define HCTSIZ5 (*((volatile uint32_t*)(OTGBASE + 0x5B0)))
|
| 137 | | -#define HCDMA5 (*((volatile uint32_t*)(OTGBASE + 0x5B4)))
|
| 138 | | -#define HCCHAR6 (*((volatile uint32_t*)(OTGBASE + 0x5C0)))
|
| 139 | | -#define HCSPLT6 (*((volatile uint32_t*)(OTGBASE + 0x5C4)))
|
| 140 | | -#define HCINT6 (*((volatile uint32_t*)(OTGBASE + 0x5C8)))
|
| 141 | | -#define HCINTMSK6 (*((volatile uint32_t*)(OTGBASE + 0x5CC)))
|
| 142 | | -#define HCTSIZ6 (*((volatile uint32_t*)(OTGBASE + 0x5D0)))
|
| 143 | | -#define HCDMA6 (*((volatile uint32_t*)(OTGBASE + 0x5D4)))
|
| 144 | | -#define HCCHAR7 (*((volatile uint32_t*)(OTGBASE + 0x5E0)))
|
| 145 | | -#define HCSPLT7 (*((volatile uint32_t*)(OTGBASE + 0x5E4)))
|
| 146 | | -#define HCINT7 (*((volatile uint32_t*)(OTGBASE + 0x5E8)))
|
| 147 | | -#define HCINTMSK7 (*((volatile uint32_t*)(OTGBASE + 0x5EC)))
|
| 148 | | -#define HCTSIZ7 (*((volatile uint32_t*)(OTGBASE + 0x5F0)))
|
| 149 | | -#define HCDMA7 (*((volatile uint32_t*)(OTGBASE + 0x5F4)))
|
| 150 | | -#define HCCHAR8 (*((volatile uint32_t*)(OTGBASE + 0x600)))
|
| 151 | | -#define HCSPLT8 (*((volatile uint32_t*)(OTGBASE + 0x604)))
|
| 152 | | -#define HCINT8 (*((volatile uint32_t*)(OTGBASE + 0x608)))
|
| 153 | | -#define HCINTMSK8 (*((volatile uint32_t*)(OTGBASE + 0x60C)))
|
| 154 | | -#define HCTSIZ8 (*((volatile uint32_t*)(OTGBASE + 0x610)))
|
| 155 | | -#define HCDMA8 (*((volatile uint32_t*)(OTGBASE + 0x614)))
|
| 156 | | -#define HCCHAR9 (*((volatile uint32_t*)(OTGBASE + 0x620)))
|
| 157 | | -#define HCSPLT9 (*((volatile uint32_t*)(OTGBASE + 0x624)))
|
| 158 | | -#define HCINT9 (*((volatile uint32_t*)(OTGBASE + 0x628)))
|
| 159 | | -#define HCINTMSK9 (*((volatile uint32_t*)(OTGBASE + 0x62C)))
|
| 160 | | -#define HCTSIZ9 (*((volatile uint32_t*)(OTGBASE + 0x630)))
|
| 161 | | -#define HCDMA9 (*((volatile uint32_t*)(OTGBASE + 0x634)))
|
| 162 | | -#define HCCHAR10 (*((volatile uint32_t*)(OTGBASE + 0x640)))
|
| 163 | | -#define HCSPLT10 (*((volatile uint32_t*)(OTGBASE + 0x644)))
|
| 164 | | -#define HCINT10 (*((volatile uint32_t*)(OTGBASE + 0x648)))
|
| 165 | | -#define HCINTMSK10 (*((volatile uint32_t*)(OTGBASE + 0x64C)))
|
| 166 | | -#define HCTSIZ10 (*((volatile uint32_t*)(OTGBASE + 0x650)))
|
| 167 | | -#define HCDMA10 (*((volatile uint32_t*)(OTGBASE + 0x654)))
|
| 168 | | -#define HCCHAR11 (*((volatile uint32_t*)(OTGBASE + 0x660)))
|
| 169 | | -#define HCSPLT11 (*((volatile uint32_t*)(OTGBASE + 0x664)))
|
| 170 | | -#define HCINT11 (*((volatile uint32_t*)(OTGBASE + 0x668)))
|
| 171 | | -#define HCINTMSK11 (*((volatile uint32_t*)(OTGBASE + 0x66C)))
|
| 172 | | -#define HCTSIZ11 (*((volatile uint32_t*)(OTGBASE + 0x670)))
|
| 173 | | -#define HCDMA11 (*((volatile uint32_t*)(OTGBASE + 0x674)))
|
| 174 | | -#define HCCHAR12 (*((volatile uint32_t*)(OTGBASE + 0x680)))
|
| 175 | | -#define HCSPLT12 (*((volatile uint32_t*)(OTGBASE + 0x684)))
|
| 176 | | -#define HCINT12 (*((volatile uint32_t*)(OTGBASE + 0x688)))
|
| 177 | | -#define HCINTMSK12 (*((volatile uint32_t*)(OTGBASE + 0x68C)))
|
| 178 | | -#define HCTSIZ12 (*((volatile uint32_t*)(OTGBASE + 0x690)))
|
| 179 | | -#define HCDMA12 (*((volatile uint32_t*)(OTGBASE + 0x694)))
|
| 180 | | -#define HCCHAR13 (*((volatile uint32_t*)(OTGBASE + 0x6A0)))
|
| 181 | | -#define HCSPLT13 (*((volatile uint32_t*)(OTGBASE + 0x6A4)))
|
| 182 | | -#define HCINT13 (*((volatile uint32_t*)(OTGBASE + 0x6A8)))
|
| 183 | | -#define HCINTMSK13 (*((volatile uint32_t*)(OTGBASE + 0x6AC)))
|
| 184 | | -#define HCTSIZ13 (*((volatile uint32_t*)(OTGBASE + 0x6B0)))
|
| 185 | | -#define HCDMA13 (*((volatile uint32_t*)(OTGBASE + 0x6B4)))
|
| 186 | | -#define HCCHAR14 (*((volatile uint32_t*)(OTGBASE + 0x6C0)))
|
| 187 | | -#define HCSPLT14 (*((volatile uint32_t*)(OTGBASE + 0x6C4)))
|
| 188 | | -#define HCINT14 (*((volatile uint32_t*)(OTGBASE + 0x6C8)))
|
| 189 | | -#define HCINTMSK14 (*((volatile uint32_t*)(OTGBASE + 0x6CC)))
|
| 190 | | -#define HCTSIZ14 (*((volatile uint32_t*)(OTGBASE + 0x6D0)))
|
| 191 | | -#define HCDMA14 (*((volatile uint32_t*)(OTGBASE + 0x6D4)))
|
| 192 | | -#define HCCHAR15 (*((volatile uint32_t*)(OTGBASE + 0x6E0)))
|
| 193 | | -#define HCSPLT15 (*((volatile uint32_t*)(OTGBASE + 0x6E4)))
|
| 194 | | -#define HCINT15 (*((volatile uint32_t*)(OTGBASE + 0x6E8)))
|
| 195 | | -#define HCINTMSK15 (*((volatile uint32_t*)(OTGBASE + 0x6EC)))
|
| 196 | | -#define HCTSIZ15 (*((volatile uint32_t*)(OTGBASE + 0x6F0)))
|
| 197 | | -#define HCDMA15 (*((volatile uint32_t*)(OTGBASE + 0x6F4)))
|
| | 96 | +#define HCCHAR(x) (*((uint32_t volatile*)(OTGBASE + 0x500 + 0x20 * (x))))
|
| | 97 | +#define HCSPLT(x) (*((uint32_t volatile*)(OTGBASE + 0x504 + 0x20 * (x))))
|
| | 98 | +#define HCINT(x) (*((uint32_t volatile*)(OTGBASE + 0x508 + 0x20 * (x))))
|
| | 99 | +#define HCINTMSK(x) (*((uint32_t volatile*)(OTGBASE + 0x50C + 0x20 * (x))))
|
| | 100 | +#define HCTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x510 + 0x20 * (x))))
|
| | 101 | +#define HCDMA(x) (*((uint32_t volatile*)(OTGBASE + 0x514 + 0x20 * (x))))
|
| | 102 | +#define HCCHAR0 (*((uint32_t volatile*)(OTGBASE + 0x500)))
|
| | 103 | +#define HCSPLT0 (*((uint32_t volatile*)(OTGBASE + 0x504)))
|
| | 104 | +#define HCINT0 (*((uint32_t volatile*)(OTGBASE + 0x508)))
|
| | 105 | +#define HCINTMSK0 (*((uint32_t volatile*)(OTGBASE + 0x50C)))
|
| | 106 | +#define HCTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0x510)))
|
| | 107 | +#define HCDMA0 (*((uint32_t volatile*)(OTGBASE + 0x514)))
|
| | 108 | +#define HCCHAR1 (*((uint32_t volatile*)(OTGBASE + 0x520)))
|
| | 109 | +#define HCSPLT1 (*((uint32_t volatile*)(OTGBASE + 0x524)))
|
| | 110 | +#define HCINT1 (*((uint32_t volatile*)(OTGBASE + 0x528)))
|
| | 111 | +#define HCINTMSK1 (*((uint32_t volatile*)(OTGBASE + 0x52C)))
|
| | 112 | +#define HCTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x530)))
|
| | 113 | +#define HCDMA1 (*((uint32_t volatile*)(OTGBASE + 0x534)))
|
| | 114 | +#define HCCHAR2 (*((uint32_t volatile*)(OTGBASE + 0x540)))
|
| | 115 | +#define HCSPLT2 (*((uint32_t volatile*)(OTGBASE + 0x544)))
|
| | 116 | +#define HCINT2 (*((uint32_t volatile*)(OTGBASE + 0x548)))
|
| | 117 | +#define HCINTMSK2 (*((uint32_t volatile*)(OTGBASE + 0x54C)))
|
| | 118 | +#define HCTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x550)))
|
| | 119 | +#define HCDMA2 (*((uint32_t volatile*)(OTGBASE + 0x554)))
|
| | 120 | +#define HCCHAR3 (*((uint32_t volatile*)(OTGBASE + 0x560)))
|
| | 121 | +#define HCSPLT3 (*((uint32_t volatile*)(OTGBASE + 0x564)))
|
| | 122 | +#define HCINT3 (*((uint32_t volatile*)(OTGBASE + 0x568)))
|
| | 123 | +#define HCINTMSK3 (*((uint32_t volatile*)(OTGBASE + 0x56C)))
|
| | 124 | +#define HCTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x570)))
|
| | 125 | +#define HCDMA3 (*((uint32_t volatile*)(OTGBASE + 0x574)))
|
| | 126 | +#define HCCHAR4 (*((uint32_t volatile*)(OTGBASE + 0x580)))
|
| | 127 | +#define HCSPLT4 (*((uint32_t volatile*)(OTGBASE + 0x584)))
|
| | 128 | +#define HCINT4 (*((uint32_t volatile*)(OTGBASE + 0x588)))
|
| | 129 | +#define HCINTMSK4 (*((uint32_t volatile*)(OTGBASE + 0x58C)))
|
| | 130 | +#define HCTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x590)))
|
| | 131 | +#define HCDMA4 (*((uint32_t volatile*)(OTGBASE + 0x594)))
|
| | 132 | +#define HCCHAR5 (*((uint32_t volatile*)(OTGBASE + 0x5A0)))
|
| | 133 | +#define HCSPLT5 (*((uint32_t volatile*)(OTGBASE + 0x5A4)))
|
| | 134 | +#define HCINT5 (*((uint32_t volatile*)(OTGBASE + 0x5A8)))
|
| | 135 | +#define HCINTMSK5 (*((uint32_t volatile*)(OTGBASE + 0x5AC)))
|
| | 136 | +#define HCTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x5B0)))
|
| | 137 | +#define HCDMA5 (*((uint32_t volatile*)(OTGBASE + 0x5B4)))
|
| | 138 | +#define HCCHAR6 (*((uint32_t volatile*)(OTGBASE + 0x5C0)))
|
| | 139 | +#define HCSPLT6 (*((uint32_t volatile*)(OTGBASE + 0x5C4)))
|
| | 140 | +#define HCINT6 (*((uint32_t volatile*)(OTGBASE + 0x5C8)))
|
| | 141 | +#define HCINTMSK6 (*((uint32_t volatile*)(OTGBASE + 0x5CC)))
|
| | 142 | +#define HCTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x5D0)))
|
| | 143 | +#define HCDMA6 (*((uint32_t volatile*)(OTGBASE + 0x5D4)))
|
| | 144 | +#define HCCHAR7 (*((uint32_t volatile*)(OTGBASE + 0x5E0)))
|
| | 145 | +#define HCSPLT7 (*((uint32_t volatile*)(OTGBASE + 0x5E4)))
|
| | 146 | +#define HCINT7 (*((uint32_t volatile*)(OTGBASE + 0x5E8)))
|
| | 147 | +#define HCINTMSK7 (*((uint32_t volatile*)(OTGBASE + 0x5EC)))
|
| | 148 | +#define HCTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x5F0)))
|
| | 149 | +#define HCDMA7 (*((uint32_t volatile*)(OTGBASE + 0x5F4)))
|
| | 150 | +#define HCCHAR8 (*((uint32_t volatile*)(OTGBASE + 0x600)))
|
| | 151 | +#define HCSPLT8 (*((uint32_t volatile*)(OTGBASE + 0x604)))
|
| | 152 | +#define HCINT8 (*((uint32_t volatile*)(OTGBASE + 0x608)))
|
| | 153 | +#define HCINTMSK8 (*((uint32_t volatile*)(OTGBASE + 0x60C)))
|
| | 154 | +#define HCTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0x610)))
|
| | 155 | +#define HCDMA8 (*((uint32_t volatile*)(OTGBASE + 0x614)))
|
| | 156 | +#define HCCHAR9 (*((uint32_t volatile*)(OTGBASE + 0x620)))
|
| | 157 | +#define HCSPLT9 (*((uint32_t volatile*)(OTGBASE + 0x624)))
|
| | 158 | +#define HCINT9 (*((uint32_t volatile*)(OTGBASE + 0x628)))
|
| | 159 | +#define HCINTMSK9 (*((uint32_t volatile*)(OTGBASE + 0x62C)))
|
| | 160 | +#define HCTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0x630)))
|
| | 161 | +#define HCDMA9 (*((uint32_t volatile*)(OTGBASE + 0x634)))
|
| | 162 | +#define HCCHAR10 (*((uint32_t volatile*)(OTGBASE + 0x640)))
|
| | 163 | +#define HCSPLT10 (*((uint32_t volatile*)(OTGBASE + 0x644)))
|
| | 164 | +#define HCINT10 (*((uint32_t volatile*)(OTGBASE + 0x648)))
|
| | 165 | +#define HCINTMSK10 (*((uint32_t volatile*)(OTGBASE + 0x64C)))
|
| | 166 | +#define HCTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0x650)))
|
| | 167 | +#define HCDMA10 (*((uint32_t volatile*)(OTGBASE + 0x654)))
|
| | 168 | +#define HCCHAR11 (*((uint32_t volatile*)(OTGBASE + 0x660)))
|
| | 169 | +#define HCSPLT11 (*((uint32_t volatile*)(OTGBASE + 0x664)))
|
| | 170 | +#define HCINT11 (*((uint32_t volatile*)(OTGBASE + 0x668)))
|
| | 171 | +#define HCINTMSK11 (*((uint32_t volatile*)(OTGBASE + 0x66C)))
|
| | 172 | +#define HCTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0x670)))
|
| | 173 | +#define HCDMA11 (*((uint32_t volatile*)(OTGBASE + 0x674)))
|
| | 174 | +#define HCCHAR12 (*((uint32_t volatile*)(OTGBASE + 0x680)))
|
| | 175 | +#define HCSPLT12 (*((uint32_t volatile*)(OTGBASE + 0x684)))
|
| | 176 | +#define HCINT12 (*((uint32_t volatile*)(OTGBASE + 0x688)))
|
| | 177 | +#define HCINTMSK12 (*((uint32_t volatile*)(OTGBASE + 0x68C)))
|
| | 178 | +#define HCTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0x690)))
|
| | 179 | +#define HCDMA12 (*((uint32_t volatile*)(OTGBASE + 0x694)))
|
| | 180 | +#define HCCHAR13 (*((uint32_t volatile*)(OTGBASE + 0x6A0)))
|
| | 181 | +#define HCSPLT13 (*((uint32_t volatile*)(OTGBASE + 0x6A4)))
|
| | 182 | +#define HCINT13 (*((uint32_t volatile*)(OTGBASE + 0x6A8)))
|
| | 183 | +#define HCINTMSK13 (*((uint32_t volatile*)(OTGBASE + 0x6AC)))
|
| | 184 | +#define HCTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0x6B0)))
|
| | 185 | +#define HCDMA13 (*((uint32_t volatile*)(OTGBASE + 0x6B4)))
|
| | 186 | +#define HCCHAR14 (*((uint32_t volatile*)(OTGBASE + 0x6C0)))
|
| | 187 | +#define HCSPLT14 (*((uint32_t volatile*)(OTGBASE + 0x6C4)))
|
| | 188 | +#define HCINT14 (*((uint32_t volatile*)(OTGBASE + 0x6C8)))
|
| | 189 | +#define HCINTMSK14 (*((uint32_t volatile*)(OTGBASE + 0x6CC)))
|
| | 190 | +#define HCTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0x6D0)))
|
| | 191 | +#define HCDMA14 (*((uint32_t volatile*)(OTGBASE + 0x6D4)))
|
| | 192 | +#define HCCHAR15 (*((uint32_t volatile*)(OTGBASE + 0x6E0)))
|
| | 193 | +#define HCSPLT15 (*((uint32_t volatile*)(OTGBASE + 0x6E4)))
|
| | 194 | +#define HCINT15 (*((uint32_t volatile*)(OTGBASE + 0x6E8)))
|
| | 195 | +#define HCINTMSK15 (*((uint32_t volatile*)(OTGBASE + 0x6EC)))
|
| | 196 | +#define HCTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0x6F0)))
|
| | 197 | +#define HCDMA15 (*((uint32_t volatile*)(OTGBASE + 0x6F4)))
|
| 198 | 198 |
|
| 199 | 199 | /*** DEVICE MODE REGISTERS ***/
|
| 200 | 200 | /* Device Global Registers */
|
| 201 | | -#define DCFG (*((volatile uint32_t*)(OTGBASE + 0x800)))
|
| 202 | | -#define DCTL (*((volatile uint32_t*)(OTGBASE + 0x804)))
|
| 203 | | -#define DSTS (*((volatile uint32_t*)(OTGBASE + 0x808)))
|
| 204 | | -#define DIEPMSK (*((volatile uint32_t*)(OTGBASE + 0x810)))
|
| 205 | | -#define DOEPMSK (*((volatile uint32_t*)(OTGBASE + 0x814)))
|
| 206 | | -#define DAINT (*((volatile uint32_t*)(OTGBASE + 0x818)))
|
| 207 | | -#define DAINTMSK (*((volatile uint32_t*)(OTGBASE + 0x81C)))
|
| 208 | | -#define DTKNQR1 (*((volatile uint32_t*)(OTGBASE + 0x820)))
|
| 209 | | -#define DTKNQR2 (*((volatile uint32_t*)(OTGBASE + 0x824)))
|
| 210 | | -#define DVBUSDIS (*((volatile uint32_t*)(OTGBASE + 0x828)))
|
| 211 | | -#define DVBUSPULSE (*((volatile uint32_t*)(OTGBASE + 0x82C)))
|
| 212 | | -#define DTKNQR3 (*((volatile uint32_t*)(OTGBASE + 0x830)))
|
| 213 | | -#define DTKNQR4 (*((volatile uint32_t*)(OTGBASE + 0x834)))
|
| | 201 | +#define DCFG (*((uint32_t volatile*)(OTGBASE + 0x800)))
|
| | 202 | +#define DCTL (*((uint32_t volatile*)(OTGBASE + 0x804)))
|
| | 203 | +#define DSTS (*((uint32_t volatile*)(OTGBASE + 0x808)))
|
| | 204 | +#define DIEPMSK (*((uint32_t volatile*)(OTGBASE + 0x810)))
|
| | 205 | +#define DOEPMSK (*((uint32_t volatile*)(OTGBASE + 0x814)))
|
| | 206 | +#define DAINT (*((uint32_t volatile*)(OTGBASE + 0x818)))
|
| | 207 | +#define DAINTMSK (*((uint32_t volatile*)(OTGBASE + 0x81C)))
|
| | 208 | +#define DTKNQR1 (*((uint32_t volatile*)(OTGBASE + 0x820)))
|
| | 209 | +#define DTKNQR2 (*((uint32_t volatile*)(OTGBASE + 0x824)))
|
| | 210 | +#define DVBUSDIS (*((uint32_t volatile*)(OTGBASE + 0x828)))
|
| | 211 | +#define DVBUSPULSE (*((uint32_t volatile*)(OTGBASE + 0x82C)))
|
| | 212 | +#define DTKNQR3 (*((uint32_t volatile*)(OTGBASE + 0x830)))
|
| | 213 | +#define DTKNQR4 (*((uint32_t volatile*)(OTGBASE + 0x834)))
|
| 214 | 214 |
|
| 215 | 215 | /* Device Logical IN Endpoint-Specific Registers */
|
| 216 | | -#define DIEPCTL(x) (*((volatile uint32_t*)(OTGBASE + 0x900 + 0x20 * (x))))
|
| 217 | | -#define DIEPINT(x) (*((volatile uint32_t*)(OTGBASE + 0x908 + 0x20 * (x))))
|
| 218 | | -#define DIEPTSIZ(x) (*((volatile uint32_t*)(OTGBASE + 0x910 + 0x20 * (x))))
|
| 219 | | -#define DIEPDMA(x) (*((volatile uint32_t*)(OTGBASE + 0x914 + 0x20 * (x))))
|
| 220 | | -#define DIEPCTL0 (*((volatile uint32_t*)(OTGBASE + 0x900)))
|
| 221 | | -#define DIEPINT0 (*((volatile uint32_t*)(OTGBASE + 0x908)))
|
| 222 | | -#define DIEPTSIZ0 (*((volatile uint32_t*)(OTGBASE + 0x910)))
|
| 223 | | -#define DIEPDMA0 (*((volatile uint32_t*)(OTGBASE + 0x914)))
|
| 224 | | -#define DIEPCTL1 (*((volatile uint32_t*)(OTGBASE + 0x920)))
|
| 225 | | -#define DIEPINT1 (*((volatile uint32_t*)(OTGBASE + 0x928)))
|
| 226 | | -#define DIEPTSIZ1 (*((volatile uint32_t*)(OTGBASE + 0x930)))
|
| 227 | | -#define DIEPDMA1 (*((volatile uint32_t*)(OTGBASE + 0x934)))
|
| 228 | | -#define DIEPCTL2 (*((volatile uint32_t*)(OTGBASE + 0x940)))
|
| 229 | | -#define DIEPINT2 (*((volatile uint32_t*)(OTGBASE + 0x948)))
|
| 230 | | -#define DIEPTSIZ2 (*((volatile uint32_t*)(OTGBASE + 0x950)))
|
| 231 | | -#define DIEPDMA2 (*((volatile uint32_t*)(OTGBASE + 0x954)))
|
| 232 | | -#define DIEPCTL3 (*((volatile uint32_t*)(OTGBASE + 0x960)))
|
| 233 | | -#define DIEPINT3 (*((volatile uint32_t*)(OTGBASE + 0x968)))
|
| 234 | | -#define DIEPTSIZ3 (*((volatile uint32_t*)(OTGBASE + 0x970)))
|
| 235 | | -#define DIEPDMA3 (*((volatile uint32_t*)(OTGBASE + 0x974)))
|
| 236 | | -#define DIEPCTL4 (*((volatile uint32_t*)(OTGBASE + 0x980)))
|
| 237 | | -#define DIEPINT4 (*((volatile uint32_t*)(OTGBASE + 0x988)))
|
| 238 | | -#define DIEPTSIZ4 (*((volatile uint32_t*)(OTGBASE + 0x990)))
|
| 239 | | -#define DIEPDMA4 (*((volatile uint32_t*)(OTGBASE + 0x994)))
|
| 240 | | -#define DIEPCTL5 (*((volatile uint32_t*)(OTGBASE + 0x9A0)))
|
| 241 | | -#define DIEPINT5 (*((volatile uint32_t*)(OTGBASE + 0x9A8)))
|
| 242 | | -#define DIEPTSIZ5 (*((volatile uint32_t*)(OTGBASE + 0x9B0)))
|
| 243 | | -#define DIEPDMA5 (*((volatile uint32_t*)(OTGBASE + 0x9B4)))
|
| 244 | | -#define DIEPCTL6 (*((volatile uint32_t*)(OTGBASE + 0x9C0)))
|
| 245 | | -#define DIEPINT6 (*((volatile uint32_t*)(OTGBASE + 0x9C8)))
|
| 246 | | -#define DIEPTSIZ6 (*((volatile uint32_t*)(OTGBASE + 0x9D0)))
|
| 247 | | -#define DIEPDMA6 (*((volatile uint32_t*)(OTGBASE + 0x9D4)))
|
| 248 | | -#define DIEPCTL7 (*((volatile uint32_t*)(OTGBASE + 0x9E0)))
|
| 249 | | -#define DIEPINT7 (*((volatile uint32_t*)(OTGBASE + 0x9E8)))
|
| 250 | | -#define DIEPTSIZ7 (*((volatile uint32_t*)(OTGBASE + 0x9F0)))
|
| 251 | | -#define DIEPDMA7 (*((volatile uint32_t*)(OTGBASE + 0x9F4)))
|
| 252 | | -#define DIEPCTL8 (*((volatile uint32_t*)(OTGBASE + 0xA00)))
|
| 253 | | -#define DIEPINT8 (*((volatile uint32_t*)(OTGBASE + 0xA08)))
|
| 254 | | -#define DIEPTSIZ8 (*((volatile uint32_t*)(OTGBASE + 0xA10)))
|
| 255 | | -#define DIEPDMA8 (*((volatile uint32_t*)(OTGBASE + 0xA14)))
|
| 256 | | -#define DIEPCTL9 (*((volatile uint32_t*)(OTGBASE + 0xA20)))
|
| 257 | | -#define DIEPINT9 (*((volatile uint32_t*)(OTGBASE + 0xA28)))
|
| 258 | | -#define DIEPTSIZ9 (*((volatile uint32_t*)(OTGBASE + 0xA30)))
|
| 259 | | -#define DIEPDMA9 (*((volatile uint32_t*)(OTGBASE + 0xA34)))
|
| 260 | | -#define DIEPCTL10 (*((volatile uint32_t*)(OTGBASE + 0xA40)))
|
| 261 | | -#define DIEPINT10 (*((volatile uint32_t*)(OTGBASE + 0xA48)))
|
| 262 | | -#define DIEPTSIZ10 (*((volatile uint32_t*)(OTGBASE + 0xA50)))
|
| 263 | | -#define DIEPDMA10 (*((volatile uint32_t*)(OTGBASE + 0xA54)))
|
| 264 | | -#define DIEPCTL11 (*((volatile uint32_t*)(OTGBASE + 0xA60)))
|
| 265 | | -#define DIEPINT11 (*((volatile uint32_t*)(OTGBASE + 0xA68)))
|
| 266 | | -#define DIEPTSIZ11 (*((volatile uint32_t*)(OTGBASE + 0xA70)))
|
| 267 | | -#define DIEPDMA11 (*((volatile uint32_t*)(OTGBASE + 0xA74)))
|
| 268 | | -#define DIEPCTL12 (*((volatile uint32_t*)(OTGBASE + 0xA80)))
|
| 269 | | -#define DIEPINT12 (*((volatile uint32_t*)(OTGBASE + 0xA88)))
|
| 270 | | -#define DIEPTSIZ12 (*((volatile uint32_t*)(OTGBASE + 0xA90)))
|
| 271 | | -#define DIEPDMA12 (*((volatile uint32_t*)(OTGBASE + 0xA94)))
|
| 272 | | -#define DIEPCTL13 (*((volatile uint32_t*)(OTGBASE + 0xAA0)))
|
| 273 | | -#define DIEPINT13 (*((volatile uint32_t*)(OTGBASE + 0xAA8)))
|
| 274 | | -#define DIEPTSIZ13 (*((volatile uint32_t*)(OTGBASE + 0xAB0)))
|
| 275 | | -#define DIEPDMA13 (*((volatile uint32_t*)(OTGBASE + 0xAB4)))
|
| 276 | | -#define DIEPCTL14 (*((volatile uint32_t*)(OTGBASE + 0xAC0)))
|
| 277 | | -#define DIEPINT14 (*((volatile uint32_t*)(OTGBASE + 0xAC8)))
|
| 278 | | -#define DIEPTSIZ14 (*((volatile uint32_t*)(OTGBASE + 0xAD0)))
|
| 279 | | -#define DIEPDMA14 (*((volatile uint32_t*)(OTGBASE + 0xAD4)))
|
| 280 | | -#define DIEPCTL15 (*((volatile uint32_t*)(OTGBASE + 0xAE0)))
|
| 281 | | -#define DIEPINT15 (*((volatile uint32_t*)(OTGBASE + 0xAE8)))
|
| 282 | | -#define DIEPTSIZ15 (*((volatile uint32_t*)(OTGBASE + 0xAF0)))
|
| 283 | | -#define DIEPDMA15 (*((volatile uint32_t*)(OTGBASE + 0xAF4)))
|
| | 216 | +#define DIEPCTL(x) (*((uint32_t volatile*)(OTGBASE + 0x900 + 0x20 * (x))))
|
| | 217 | +#define DIEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0x908 + 0x20 * (x))))
|
| | 218 | +#define DIEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x910 + 0x20 * (x))))
|
| | 219 | +#define DIEPDMA(x) (*((const void* volatile*)(OTGBASE + 0x914 + 0x20 * (x))))
|
| | 220 | +#define DIEPCTL0 (*((uint32_t volatile*)(OTGBASE + 0x900)))
|
| | 221 | +#define DIEPINT0 (*((uint32_t volatile*)(OTGBASE + 0x908)))
|
| | 222 | +#define DIEPTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0x910)))
|
| | 223 | +#define DIEPDMA0 (*((const void* volatile*)(OTGBASE + 0x914)))
|
| | 224 | +#define DIEPCTL1 (*((uint32_t volatile*)(OTGBASE + 0x920)))
|
| | 225 | +#define DIEPINT1 (*((uint32_t volatile*)(OTGBASE + 0x928)))
|
| | 226 | +#define DIEPTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x930)))
|
| | 227 | +#define DIEPDMA1 (*((const void* volatile*)(OTGBASE + 0x934)))
|
| | 228 | +#define DIEPCTL2 (*((uint32_t volatile*)(OTGBASE + 0x940)))
|
| | 229 | +#define DIEPINT2 (*((uint32_t volatile*)(OTGBASE + 0x948)))
|
| | 230 | +#define DIEPTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x950)))
|
| | 231 | +#define DIEPDMA2 (*((const void* volatile*)(OTGBASE + 0x954)))
|
| | 232 | +#define DIEPCTL3 (*((uint32_t volatile*)(OTGBASE + 0x960)))
|
| | 233 | +#define DIEPINT3 (*((uint32_t volatile*)(OTGBASE + 0x968)))
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| | 234 | +#define DIEPTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x970)))
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| | 235 | +#define DIEPDMA3 (*((const void* volatile*)(OTGBASE + 0x974)))
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| | 236 | +#define DIEPCTL4 (*((uint32_t volatile*)(OTGBASE + 0x980)))
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| | 237 | +#define DIEPINT4 (*((uint32_t volatile*)(OTGBASE + 0x988)))
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| | 238 | +#define DIEPTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x990)))
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| | 239 | +#define DIEPDMA4 (*((const void* volatile*)(OTGBASE + 0x994)))
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| | 240 | +#define DIEPCTL5 (*((uint32_t volatile*)(OTGBASE + 0x9A0)))
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| | 241 | +#define DIEPINT5 (*((uint32_t volatile*)(OTGBASE + 0x9A8)))
|
| | 242 | +#define DIEPTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x9B0)))
|
| | 243 | +#define DIEPDMA5 (*((const void* volatile*)(OTGBASE + 0x9B4)))
|
| | 244 | +#define DIEPCTL6 (*((uint32_t volatile*)(OTGBASE + 0x9C0)))
|
| | 245 | +#define DIEPINT6 (*((uint32_t volatile*)(OTGBASE + 0x9C8)))
|
| | 246 | +#define DIEPTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x9D0)))
|
| | 247 | +#define DIEPDMA6 (*((const void* volatile*)(OTGBASE + 0x9D4)))
|
| | 248 | +#define DIEPCTL7 (*((uint32_t volatile*)(OTGBASE + 0x9E0)))
|
| | 249 | +#define DIEPINT7 (*((uint32_t volatile*)(OTGBASE + 0x9E8)))
|
| | 250 | +#define DIEPTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x9F0)))
|
| | 251 | +#define DIEPDMA7 (*((const void* volatile*)(OTGBASE + 0x9F4)))
|
| | 252 | +#define DIEPCTL8 (*((uint32_t volatile*)(OTGBASE + 0xA00)))
|
| | 253 | +#define DIEPINT8 (*((uint32_t volatile*)(OTGBASE + 0xA08)))
|
| | 254 | +#define DIEPTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0xA10)))
|
| | 255 | +#define DIEPDMA8 (*((const void* volatile*)(OTGBASE + 0xA14)))
|
| | 256 | +#define DIEPCTL9 (*((uint32_t volatile*)(OTGBASE + 0xA20)))
|
| | 257 | +#define DIEPINT9 (*((uint32_t volatile*)(OTGBASE + 0xA28)))
|
| | 258 | +#define DIEPTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0xA30)))
|
| | 259 | +#define DIEPDMA9 (*((const void* volatile*)(OTGBASE + 0xA34)))
|
| | 260 | +#define DIEPCTL10 (*((uint32_t volatile*)(OTGBASE + 0xA40)))
|
| | 261 | +#define DIEPINT10 (*((uint32_t volatile*)(OTGBASE + 0xA48)))
|
| | 262 | +#define DIEPTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0xA50)))
|
| | 263 | +#define DIEPDMA10 (*((const void* volatile*)(OTGBASE + 0xA54)))
|
| | 264 | +#define DIEPCTL11 (*((uint32_t volatile*)(OTGBASE + 0xA60)))
|
| | 265 | +#define DIEPINT11 (*((uint32_t volatile*)(OTGBASE + 0xA68)))
|
| | 266 | +#define DIEPTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0xA70)))
|
| | 267 | +#define DIEPDMA11 (*((const void* volatile*)(OTGBASE + 0xA74)))
|
| | 268 | +#define DIEPCTL12 (*((uint32_t volatile*)(OTGBASE + 0xA80)))
|
| | 269 | +#define DIEPINT12 (*((uint32_t volatile*)(OTGBASE + 0xA88)))
|
| | 270 | +#define DIEPTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0xA90)))
|
| | 271 | +#define DIEPDMA12 (*((const void* volatile*)(OTGBASE + 0xA94)))
|
| | 272 | +#define DIEPCTL13 (*((uint32_t volatile*)(OTGBASE + 0xAA0)))
|
| | 273 | +#define DIEPINT13 (*((uint32_t volatile*)(OTGBASE + 0xAA8)))
|
| | 274 | +#define DIEPTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0xAB0)))
|
| | 275 | +#define DIEPDMA13 (*((const void* volatile*)(OTGBASE + 0xAB4)))
|
| | 276 | +#define DIEPCTL14 (*((uint32_t volatile*)(OTGBASE + 0xAC0)))
|
| | 277 | +#define DIEPINT14 (*((uint32_t volatile*)(OTGBASE + 0xAC8)))
|
| | 278 | +#define DIEPTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0xAD0)))
|
| | 279 | +#define DIEPDMA14 (*((const void* volatile*)(OTGBASE + 0xAD4)))
|
| | 280 | +#define DIEPCTL15 (*((uint32_t volatile*)(OTGBASE + 0xAE0)))
|
| | 281 | +#define DIEPINT15 (*((uint32_t volatile*)(OTGBASE + 0xAE8)))
|
| | 282 | +#define DIEPTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0xAF0)))
|
| | 283 | +#define DIEPDMA15 (*((const void* volatile*)(OTGBASE + 0xAF4)))
|
| 284 | 284 |
|
| 285 | 285 | /* Device Logical OUT Endpoint-Specific Registers */
|
| 286 | | -#define DOEPCTL(x) (*((volatile uint32_t*)(OTGBASE + 0xB00 + 0x20 * (x))))
|
| 287 | | -#define DOEPINT(x) (*((volatile uint32_t*)(OTGBASE + 0xB08 + 0x20 * (x))))
|
| 288 | | -#define DOEPTSIZ(x) (*((volatile uint32_t*)(OTGBASE + 0xB10 + 0x20 * (x))))
|
| 289 | | -#define DOEPDMA(x) (*((volatile uint32_t*)(OTGBASE + 0xB14 + 0x20 * (x))))
|
| 290 | | -#define DOEPCTL0 (*((volatile uint32_t*)(OTGBASE + 0xB00)))
|
| 291 | | -#define DOEPINT0 (*((volatile uint32_t*)(OTGBASE + 0xB08)))
|
| 292 | | -#define DOEPTSIZ0 (*((volatile uint32_t*)(OTGBASE + 0xB10)))
|
| 293 | | -#define DOEPDMA0 (*((volatile uint32_t*)(OTGBASE + 0xB14)))
|
| 294 | | -#define DOEPCTL1 (*((volatile uint32_t*)(OTGBASE + 0xB20)))
|
| 295 | | -#define DOEPINT1 (*((volatile uint32_t*)(OTGBASE + 0xB28)))
|
| 296 | | -#define DOEPTSIZ1 (*((volatile uint32_t*)(OTGBASE + 0xB30)))
|
| 297 | | -#define DOEPDMA1 (*((volatile uint32_t*)(OTGBASE + 0xB34)))
|
| 298 | | -#define DOEPCTL2 (*((volatile uint32_t*)(OTGBASE + 0xB40)))
|
| 299 | | -#define DOEPINT2 (*((volatile uint32_t*)(OTGBASE + 0xB48)))
|
| 300 | | -#define DOEPTSIZ2 (*((volatile uint32_t*)(OTGBASE + 0xB50)))
|
| 301 | | -#define DOEPDMA2 (*((volatile uint32_t*)(OTGBASE + 0xB54)))
|
| 302 | | -#define DOEPCTL3 (*((volatile uint32_t*)(OTGBASE + 0xB60)))
|
| 303 | | -#define DOEPINT3 (*((volatile uint32_t*)(OTGBASE + 0xB68)))
|
| 304 | | -#define DOEPTSIZ3 (*((volatile uint32_t*)(OTGBASE + 0xB70)))
|
| 305 | | -#define DOEPDMA3 (*((volatile uint32_t*)(OTGBASE + 0xB74)))
|
| 306 | | -#define DOEPCTL4 (*((volatile uint32_t*)(OTGBASE + 0xB80)))
|
| 307 | | -#define DOEPINT4 (*((volatile uint32_t*)(OTGBASE + 0xB88)))
|
| 308 | | -#define DOEPTSIZ4 (*((volatile uint32_t*)(OTGBASE + 0xB90)))
|
| 309 | | -#define DOEPDMA4 (*((volatile uint32_t*)(OTGBASE + 0xB94)))
|
| 310 | | -#define DOEPCTL5 (*((volatile uint32_t*)(OTGBASE + 0xBA0)))
|
| 311 | | -#define DOEPINT5 (*((volatile uint32_t*)(OTGBASE + 0xBA8)))
|
| 312 | | -#define DOEPTSIZ5 (*((volatile uint32_t*)(OTGBASE + 0xBB0)))
|
| 313 | | -#define DOEPDMA5 (*((volatile uint32_t*)(OTGBASE + 0xBB4)))
|
| 314 | | -#define DOEPCTL6 (*((volatile uint32_t*)(OTGBASE + 0xBC0)))
|
| 315 | | -#define DOEPINT6 (*((volatile uint32_t*)(OTGBASE + 0xBC8)))
|
| 316 | | -#define DOEPTSIZ6 (*((volatile uint32_t*)(OTGBASE + 0xBD0)))
|
| 317 | | -#define DOEPDMA6 (*((volatile uint32_t*)(OTGBASE + 0xBD4)))
|
| 318 | | -#define DOEPCTL7 (*((volatile uint32_t*)(OTGBASE + 0xBE0)))
|
| 319 | | -#define DOEPINT7 (*((volatile uint32_t*)(OTGBASE + 0xBE8)))
|
| 320 | | -#define DOEPTSIZ7 (*((volatile uint32_t*)(OTGBASE + 0xBF0)))
|
| 321 | | -#define DOEPDMA7 (*((volatile uint32_t*)(OTGBASE + 0xBF4)))
|
| 322 | | -#define DOEPCTL8 (*((volatile uint32_t*)(OTGBASE + 0xC00)))
|
| 323 | | -#define DOEPINT8 (*((volatile uint32_t*)(OTGBASE + 0xC08)))
|
| 324 | | -#define DOEPTSIZ8 (*((volatile uint32_t*)(OTGBASE + 0xC10)))
|
| 325 | | -#define DOEPDMA8 (*((volatile uint32_t*)(OTGBASE + 0xC14)))
|
| 326 | | -#define DOEPCTL9 (*((volatile uint32_t*)(OTGBASE + 0xC20)))
|
| 327 | | -#define DOEPINT9 (*((volatile uint32_t*)(OTGBASE + 0xC28)))
|
| 328 | | -#define DOEPTSIZ9 (*((volatile uint32_t*)(OTGBASE + 0xC30)))
|
| 329 | | -#define DOEPDMA9 (*((volatile uint32_t*)(OTGBASE + 0xC34)))
|
| 330 | | -#define DOEPCTL10 (*((volatile uint32_t*)(OTGBASE + 0xC40)))
|
| 331 | | -#define DOEPINT10 (*((volatile uint32_t*)(OTGBASE + 0xC48)))
|
| 332 | | -#define DOEPTSIZ10 (*((volatile uint32_t*)(OTGBASE + 0xC50)))
|
| 333 | | -#define DOEPDMA10 (*((volatile uint32_t*)(OTGBASE + 0xC54)))
|
| 334 | | -#define DOEPCTL11 (*((volatile uint32_t*)(OTGBASE + 0xC60)))
|
| 335 | | -#define DOEPINT11 (*((volatile uint32_t*)(OTGBASE + 0xC68)))
|
| 336 | | -#define DOEPTSIZ11 (*((volatile uint32_t*)(OTGBASE + 0xC70)))
|
| 337 | | -#define DOEPDMA11 (*((volatile uint32_t*)(OTGBASE + 0xC74)))
|
| 338 | | -#define DOEPCTL12 (*((volatile uint32_t*)(OTGBASE + 0xC80)))
|
| 339 | | -#define DOEPINT12 (*((volatile uint32_t*)(OTGBASE + 0xC88)))
|
| 340 | | -#define DOEPTSIZ12 (*((volatile uint32_t*)(OTGBASE + 0xC90)))
|
| 341 | | -#define DOEPDMA12 (*((volatile uint32_t*)(OTGBASE + 0xC94)))
|
| 342 | | -#define DOEPCTL13 (*((volatile uint32_t*)(OTGBASE + 0xCA0)))
|
| 343 | | -#define DOEPINT13 (*((volatile uint32_t*)(OTGBASE + 0xCA8)))
|
| 344 | | -#define DOEPTSIZ13 (*((volatile uint32_t*)(OTGBASE + 0xCB0)))
|
| 345 | | -#define DOEPDMA13 (*((volatile uint32_t*)(OTGBASE + 0xCB4)))
|
| 346 | | -#define DOEPCTL14 (*((volatile uint32_t*)(OTGBASE + 0xCC0)))
|
| 347 | | -#define DOEPINT14 (*((volatile uint32_t*)(OTGBASE + 0xCC8)))
|
| 348 | | -#define DOEPTSIZ14 (*((volatile uint32_t*)(OTGBASE + 0xCD0)))
|
| 349 | | -#define DOEPDMA14 (*((volatile uint32_t*)(OTGBASE + 0xCD4)))
|
| 350 | | -#define DOEPCTL15 (*((volatile uint32_t*)(OTGBASE + 0xCE0)))
|
| 351 | | -#define DOEPINT15 (*((volatile uint32_t*)(OTGBASE + 0xCE8)))
|
| 352 | | -#define DOEPTSIZ15 (*((volatile uint32_t*)(OTGBASE + 0xCF0)))
|
| 353 | | -#define DOEPDMA15 (*((volatile uint32_t*)(OTGBASE + 0xCF4)))
|
| | 286 | +#define DOEPCTL(x) (*((uint32_t volatile*)(OTGBASE + 0xB00 + 0x20 * (x))))
|
| | 287 | +#define DOEPINT(x) (*((uint32_t volatile*)(OTGBASE + 0xB08 + 0x20 * (x))))
|
| | 288 | +#define DOEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0xB10 + 0x20 * (x))))
|
| | 289 | +#define DOEPDMA(x) (*((void* volatile*)(OTGBASE + 0xB14 + 0x20 * (x))))
|
| | 290 | +#define DOEPCTL0 (*((uint32_t volatile*)(OTGBASE + 0xB00)))
|
| | 291 | +#define DOEPINT0 (*((uint32_t volatile*)(OTGBASE + 0xB08)))
|
| | 292 | +#define DOEPTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0xB10)))
|
| | 293 | +#define DOEPDMA0 (*((void* volatile*)(OTGBASE + 0xB14)))
|
| | 294 | +#define DOEPCTL1 (*((uint32_t volatile*)(OTGBASE + 0xB20)))
|
| | 295 | +#define DOEPINT1 (*((uint32_t volatile*)(OTGBASE + 0xB28)))
|
| | 296 | +#define DOEPTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0xB30)))
|
| | 297 | +#define DOEPDMA1 (*((void* volatile*)(OTGBASE + 0xB34)))
|
| | 298 | +#define DOEPCTL2 (*((uint32_t volatile*)(OTGBASE + 0xB40)))
|
| | 299 | +#define DOEPINT2 (*((uint32_t volatile*)(OTGBASE + 0xB48)))
|
| | 300 | +#define DOEPTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0xB50)))
|
| | 301 | +#define DOEPDMA2 (*((void* volatile*)(OTGBASE + 0xB54)))
|
| | 302 | +#define DOEPCTL3 (*((uint32_t volatile*)(OTGBASE + 0xB60)))
|
| | 303 | +#define DOEPINT3 (*((uint32_t volatile*)(OTGBASE + 0xB68)))
|
| | 304 | +#define DOEPTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0xB70)))
|
| | 305 | +#define DOEPDMA3 (*((void* volatile*)(OTGBASE + 0xB74)))
|
| | 306 | +#define DOEPCTL4 (*((uint32_t volatile*)(OTGBASE + 0xB80)))
|
| | 307 | +#define DOEPINT4 (*((uint32_t volatile*)(OTGBASE + 0xB88)))
|
| | 308 | +#define DOEPTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0xB90)))
|
| | 309 | +#define DOEPDMA4 (*((void* volatile*)(OTGBASE + 0xB94)))
|
| | 310 | +#define DOEPCTL5 (*((uint32_t volatile*)(OTGBASE + 0xBA0)))
|
| | 311 | +#define DOEPINT5 (*((uint32_t volatile*)(OTGBASE + 0xBA8)))
|
| | 312 | +#define DOEPTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0xBB0)))
|
| | 313 | +#define DOEPDMA5 (*((void* volatile*)(OTGBASE + 0xBB4)))
|
| | 314 | +#define DOEPCTL6 (*((uint32_t volatile*)(OTGBASE + 0xBC0)))
|
| | 315 | +#define DOEPINT6 (*((uint32_t volatile*)(OTGBASE + 0xBC8)))
|
| | 316 | +#define DOEPTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0xBD0)))
|
| | 317 | +#define DOEPDMA6 (*((void* volatile*)(OTGBASE + 0xBD4)))
|
| | 318 | +#define DOEPCTL7 (*((uint32_t volatile*)(OTGBASE + 0xBE0)))
|
| | 319 | +#define DOEPINT7 (*((uint32_t volatile*)(OTGBASE + 0xBE8)))
|
| | 320 | +#define DOEPTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0xBF0)))
|
| | 321 | +#define DOEPDMA7 (*((void* volatile*)(OTGBASE + 0xBF4)))
|
| | 322 | +#define DOEPCTL8 (*((uint32_t volatile*)(OTGBASE + 0xC00)))
|
| | 323 | +#define DOEPINT8 (*((uint32_t volatile*)(OTGBASE + 0xC08)))
|
| | 324 | +#define DOEPTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0xC10)))
|
| | 325 | +#define DOEPDMA8 (*((void* volatile*)(OTGBASE + 0xC14)))
|
| | 326 | +#define DOEPCTL9 (*((uint32_t volatile*)(OTGBASE + 0xC20)))
|
| | 327 | +#define DOEPINT9 (*((uint32_t volatile*)(OTGBASE + 0xC28)))
|
| | 328 | +#define DOEPTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0xC30)))
|
| | 329 | +#define DOEPDMA9 (*((void* volatile*)(OTGBASE + 0xC34)))
|
| | 330 | +#define DOEPCTL10 (*((uint32_t volatile*)(OTGBASE + 0xC40)))
|
| | 331 | +#define DOEPINT10 (*((uint32_t volatile*)(OTGBASE + 0xC48)))
|
| | 332 | +#define DOEPTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0xC50)))
|
| | 333 | +#define DOEPDMA10 (*((void* volatile*)(OTGBASE + 0xC54)))
|
| | 334 | +#define DOEPCTL11 (*((uint32_t volatile*)(OTGBASE + 0xC60)))
|
| | 335 | +#define DOEPINT11 (*((uint32_t volatile*)(OTGBASE + 0xC68)))
|
| | 336 | +#define DOEPTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0xC70)))
|
| | 337 | +#define DOEPDMA11 (*((void* volatile*)(OTGBASE + 0xC74)))
|
| | 338 | +#define DOEPCTL12 (*((uint32_t volatile*)(OTGBASE + 0xC80)))
|
| | 339 | +#define DOEPINT12 (*((uint32_t volatile*)(OTGBASE + 0xC88)))
|
| | 340 | +#define DOEPTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0xC90)))
|
| | 341 | +#define DOEPDMA12 (*((void* volatile*)(OTGBASE + 0xC94)))
|
| | 342 | +#define DOEPCTL13 (*((uint32_t volatile*)(OTGBASE + 0xCA0)))
|
| | 343 | +#define DOEPINT13 (*((uint32_t volatile*)(OTGBASE + 0xCA8)))
|
| | 344 | +#define DOEPTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0xCB0)))
|
| | 345 | +#define DOEPDMA13 (*((void* volatile*)(OTGBASE + 0xCB4)))
|
| | 346 | +#define DOEPCTL14 (*((uint32_t volatile*)(OTGBASE + 0xCC0)))
|
| | 347 | +#define DOEPINT14 (*((uint32_t volatile*)(OTGBASE + 0xCC8)))
|
| | 348 | +#define DOEPTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0xCD0)))
|
| | 349 | +#define DOEPDMA14 (*((void* volatile*)(OTGBASE + 0xCD4)))
|
| | 350 | +#define DOEPCTL15 (*((uint32_t volatile*)(OTGBASE + 0xCE0)))
|
| | 351 | +#define DOEPINT15 (*((uint32_t volatile*)(OTGBASE + 0xCE8)))
|
| | 352 | +#define DOEPTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0xCF0)))
|
| | 353 | +#define DOEPDMA15 (*((void* volatile*)(OTGBASE + 0xCF4)))
|
| 354 | 354 |
|
| 355 | 355 | /* Power and Clock Gating Register */
|
| 356 | | -#define PCGCCTL (*((volatile uint32_t*)(OTGBASE + 0xE00)))
|
| | 356 | +#define PCGCCTL (*((uint32_t volatile*)(OTGBASE + 0xE00)))
|
| 357 | 357 |
|
| 358 | 358 |
|
| 359 | 359 | #endif
|
