| Index: emcore/trunk/target/ipodnano4g/mmu.c |
| — | — | @@ -28,6 +28,9 @@ |
| 29 | 29 | void clean_dcache()
|
| 30 | 30 | {
|
| 31 | 31 | asm volatile(
|
| | 32 | + "MOV R0, #0 \n\t"
|
| | 33 | + "MCR p15, 0, R0,c7,c10,0 \n\t"
|
| | 34 | + "MCR p15, 0, R0,c7,c10,4 \n\t"
|
| 32 | 35 | "MOV PC, LR \n\t"
|
| 33 | 36 | );
|
| 34 | 37 | }
|
| — | — | @@ -35,6 +38,9 @@ |
| 36 | 39 | void invalidate_dcache()
|
| 37 | 40 | {
|
| 38 | 41 | asm volatile(
|
| | 42 | + "MOV R0, #0 \n\t"
|
| | 43 | + "MCR p15, 0, R0,c7,c14,0 \n\t"
|
| | 44 | + "MCR p15, 0, R0,c7,c10,4 \n\t"
|
| 39 | 45 | "MOV PC, LR \n\t"
|
| 40 | 46 | );
|
| 41 | 47 | }
|
| — | — | @@ -42,6 +48,9 @@ |
| 43 | 49 | void invalidate_icache()
|
| 44 | 50 | {
|
| 45 | 51 | asm volatile(
|
| | 52 | + "MOV R0, #0 \n\t"
|
| | 53 | + "MCR p15, 0, R0,c7,c5,0 \n\t"
|
| | 54 | + "MCR p15, 0, R0,c7,c5,4 \n\t"
|
| 46 | 55 | "MOV PC, LR \n\t"
|
| 47 | 56 | );
|
| 48 | 57 | }
|
| Index: emcore/trunk/target/ipodnano4g/crt0.S |
| — | — | @@ -41,8 +41,51 @@ |
| 42 | 42 | .section .initcode,"ax",%progbits
|
| 43 | 43 | .global _start
|
| 44 | 44 | _start:
|
| 45 | | - ldr r0, =0x00450878
|
| 46 | | - mcr p15, 0, r0,c1,c0,0
|
| | 45 | + mrc p15, 0, r0,c1,c0
|
| | 46 | + bic r0, r0, #0x200
|
| | 47 | + orr r0, r0, #0x100
|
| | 48 | + mcr p15, 0, r0,c1,c0
|
| | 49 | + mov r0, #0x7fffffff
|
| | 50 | + mcr p15, 0, r0,c3,c0
|
| | 51 | + mov r0, #0x22000000
|
| | 52 | + orr r1, r0, #0x00000100
|
| | 53 | + orr r0, r0, #0x0003c000
|
| | 54 | + orr r1, r1, #0x000000fe
|
| | 55 | + add r2, r0, #0x200
|
| | 56 | + mov r3, #0
|
| | 57 | + str r1, [r0], #4
|
| | 58 | +.mmuloop1:
|
| | 59 | + str r3, [r0], #4
|
| | 60 | + cmp r0, r2
|
| | 61 | + bne .mmuloop1
|
| | 62 | + add r0, r0, #0x080
|
| | 63 | + add r2, r0, #0x580
|
| | 64 | +.mmuloop2:
|
| | 65 | + str r3, [r0], #4
|
| | 66 | + cmp r0, r2
|
| | 67 | + bne .mmuloop2
|
| | 68 | + add r0, r0, #0x4
|
| | 69 | + add r2, r0, #0x7c
|
| | 70 | +.mmuloop3:
|
| | 71 | + str r3, [r0], #4
|
| | 72 | + cmp r0, r2
|
| | 73 | + bne .mmuloop3
|
| | 74 | + add r0, r0, #0x4
|
| | 75 | + add r2, r0, #0x500
|
| | 76 | + add r2, r2, #0x7c
|
| | 77 | +.mmuloop4:
|
| | 78 | + str r3, [r0], #4
|
| | 79 | + cmp r0, r2
|
| | 80 | + bne .mmuloop4
|
| | 81 | + add r0, r0, #0x200
|
| | 82 | + add r2, r0, #0x3000
|
| | 83 | +.mmuloop5:
|
| | 84 | + str r3, [r0], #4
|
| | 85 | + cmp r0, r2
|
| | 86 | + bne .mmuloop5
|
| | 87 | + mrc p15, 0, r0,c1,c0
|
| | 88 | + orr r0, r0, #5
|
| | 89 | + mcr p15, 0, r0,c1,c0
|
| 47 | 90 | ldr r0, =_sramsource
|
| 48 | 91 | ldr r1, =_sramstart
|
| 49 | 92 | ldr r2, =_sramend
|
| — | — | @@ -72,17 +115,15 @@ |
| 73 | 116 | cmp r1, r0
|
| 74 | 117 | strhi r2, [r0], #4
|
| 75 | 118 | bhi .clearbss
|
| 76 | | - ldr r1, =0x38200000
|
| 77 | | - ldr r0, [r1]
|
| 78 | | - orr r0, r0, #1
|
| 79 | | - bic r0, r0, #0x10000
|
| 80 | | - str r0, [r1]
|
| 81 | 119 | mov r0, #0
|
| 82 | | - mcr p15, 0, r0,c7,c5,0
|
| 83 | | - add r1, r1, #0x00c00000
|
| | 120 | + mcr p15, 0, r0,c7,c10,0 @ clean data cache
|
| | 121 | + mcr p15, 0, r0,c7,c10,4 @ drain write buffer
|
| | 122 | + mcr p15, 0, r0,c7,c5,0 @ invalidate instruction cache
|
| | 123 | + mcr p15, 0, r0,c7,c5,4 @ flush prefetch buffer
|
| | 124 | + ldr r1, =0x38e00000
|
| 84 | 125 | add r2, r1, #0x00001000
|
| 85 | 126 | add r3, r1, #0x00002000
|
| 86 | | - sub r4, r0, #1
|
| | 127 | + mov r4, #-1
|
| 87 | 128 | str r4, [r1,#0x14]
|
| 88 | 129 | str r4, [r2,#0x14]
|
| 89 | 130 | str r4, [r1,#0xf00]
|
| — | — | @@ -89,12 +130,6 @@ |
| 90 | 131 | str r4, [r2,#0xf00]
|
| 91 | 132 | str r4, [r3,#0x08]
|
| 92 | 133 | str r4, [r3,#0x0c]
|
| 93 | | - str r0, [r1,#0x14]
|
| 94 | | - str r0, [r2,#0x14]
|
| 95 | | - mov r0, #0
|
| 96 | | - ldr r1, =0x3c500000
|
| 97 | | - str r0, [r1,#0x48]
|
| 98 | | - str r0, [r1,#0x4c]
|
| 99 | 134 | msr cpsr_c, #0xd2
|
| 100 | 135 | ldr sp, =_irqstackend
|
| 101 | 136 | msr cpsr_c, #0xd7
|
| — | — | @@ -127,6 +162,7 @@ |
| 128 | 163 | str r0, [r1]
|
| 129 | 164 | hang:
|
| 130 | 165 | msr cpsr_c, #0xd3
|
| | 166 | + mov r0, #0
|
| 131 | 167 | mcr p15, 0, r0,c7,c0,4
|
| 132 | 168 | b hang
|
| 133 | 169 | .size reset, .-reset
|
| — | — | @@ -192,7 +228,7 @@ |
| 193 | 229 | sub sp, sp, #0x44
|
| 194 | 230 | mov r0, #0
|
| 195 | 231 | adr r1, prefetch_abort_text
|
| 196 | | - mrc p15, 0, r3,c5,c0,1
|
| | 232 | + mrc p15, 0, r3,c5,c0
|
| 197 | 233 | mov r4, r3,lsr#4
|
| 198 | 234 | and r4, r4, #0xf
|
| 199 | 235 | and r5, r3, #0xf
|
| — | — | @@ -292,12 +328,7 @@ |
| 293 | 329 | .type read_usec_timer, %function
|
| 294 | 330 | read_usec_timer:
|
| 295 | 331 | ldr r0, val_3c700000
|
| 296 | | - ldr r1, [r0,#0x80]
|
| 297 | | - ldr r0, [r0,#0x84]
|
| 298 | | - mov r0, r0,lsr#5
|
| 299 | | - orr r0, r0, r1,lsl#27
|
| 300 | | - add r0, r0, r0,asr#2
|
| 301 | | - add r0, r0, r0,asr#6
|
| | 332 | + ldr r0, [r0,#0xb4]
|
| 302 | 333 | bx lr
|
| 303 | 334 | .size read_usec_timer, .-read_usec_timer
|
| 304 | 335 |
|
