freemyipod r720 - Code Review

Repository:	freemyipod
Revision:	< r719‎ \| r720 \| r721 >
Date:	23:39, 4 July 2011
Author:	theseven
Status:	new
Tags:
Comment:	emCORE: Fix SynopsysOTG driver bugs discovered by n1s
Modified paths:	/emcore/trunk/usb/synopsysotg.c (modified) (history)

Diff [purge]

Index: emcore/trunk/usb/synopsysotg.c
—	—	@@ -136,13 +136,16 @@
137	137	DCTL = 0x802; /* Soft Disconnect */
138	138
139	139	OPHYPWR = 0; /* PHY: Power up */
	140	+ udelay(10);
140	141	OPHYUNK1 = 1;
141	142	OPHYUNK2 = 0xE3F;
142		~~- OPHYCLK = SYNOPSYSOTG_CLOCK;~~
143	143	ORSTCON = 1; /* PHY: Assert Software Reset */
144	144	udelay(10);
145	145	ORSTCON = 0; /* PHY: Deassert Software Reset */
	146	+ udelay(10);
146	147	OPHYUNK3 = 0x600;
	148	+ OPHYCLK = SYNOPSYSOTG_CLOCK;
	149	+ sleep(400);
147	150
148	151	GRSTCTL = 1; /* OTG: Assert Software Reset */
149	152	while (GRSTCTL & 1); /* Wait for OTG to ack reset */
—	—	@@ -366,9 +369,11 @@
367	370	{
368	371	DCTL = 0x802; /* Soft Disconnect */
369	372
370		~~- ORSTCON = 1; /* Put the PHY into reset (needed to get current down) */~~
	373	+ OPHYPWR = 0xF; /* PHY: Power down */
	374	+ udelay(10);
	375	+ ORSTCON = 7; /* Put the PHY into reset (needed to get current down) */
	376	+ udelay(10);
371	377	PCGCCTL = 1; /* Shut down PHY clock */
372		~~- OPHYPWR = 0xF; /* PHY: Power down */~~
373	378
374	379	clockgate_enable(CLOCKGATE_USB_1, false);
375	380	clockgate_enable(CLOCKGATE_USB_2, false);