| Index: emcore/trunk/target/ipodnano4g/lcd.c |
| — | — | @@ -242,27 +242,27 @@ |
| 243 | 243 | __asm__ volatile(" mov r5, #0 \n"); |
| 244 | 244 | __asm__ volatile(" mov r7, r8 \n"); |
| 245 | 245 | __asm__ volatile("displaylcd_dither_x: \n"); // the lcd can accept one pixel every 25 clocks |
| 246 | | - __asm__ volatile(" ldr r0, [r3] \n"); // 1 cycle, 2 mem, r0 latency 4, r3 early
|
| | 246 | + __asm__ volatile(" ldr r0, [r3] \n"); // 1 cycle, 2 mem, r0 latency 4, r3 early |
| 247 | 247 | __asm__ volatile(" add r3, r3, r10 \n"); // 1 cycle |
| 248 | | - __asm__ volatile(" ldr r1, [r7,#4] \n"); // 1 cycle, 1 mem, r1 latency 3, r7 early
|
| | 248 | + __asm__ volatile(" ldr r1, [r7,#4] \n"); // 1 cycle, 1 mem, r1 latency 3, r7 early |
| 249 | 249 | __asm__ volatile(" subs lr, lr, #1 \n"); // 1 cycle |
| 250 | | - __asm__ volatile(" ssub8 r0, r0, r4 \n"); // 1 cycle
|
| 251 | | - __asm__ volatile(" sadd8 r1, r1, r5 \n"); // 1 cycle
|
| 252 | | - __asm__ volatile(" qadd8 r0, r0, r1 \n"); // 1 cycle, r0 latency 2
|
| 253 | | - // bubble (due to r0 latency)
|
| 254 | | - __asm__ volatile(" sadd8 r0, r0, r4 \n"); // 1 cycle
|
| 255 | | - __asm__ volatile(" str r0, [r9] \n"); // 1 cycle, 1 mem, r9 early
|
| 256 | | - __asm__ volatile(" bic r2, r0, r6 \n"); // 1 cycle
|
| 257 | | - __asm__ volatile(" and r1, r6, r0,lsr#6 \n"); // 1 cycle, r0 early
|
| 258 | | - __asm__ volatile(" orr r2, r2, r1 \n"); // 1 cycle
|
| 259 | | - __asm__ volatile(" mov r1, r5 \n"); // 1 cycle
|
| 260 | | - __asm__ volatile(" shsub8 r5, r0, r2 \n"); // 1 cycle
|
| 261 | | - __asm__ volatile(" shadd8 r1, r1, r5 \n"); // 1 cycle
|
| | 250 | + __asm__ volatile(" ssub8 r0, r0, r4 \n"); // 1 cycle |
| | 251 | + __asm__ volatile(" sadd8 r1, r1, r5 \n"); // 1 cycle |
| | 252 | + __asm__ volatile(" qadd8 r0, r0, r1 \n"); // 1 cycle, r0 latency 2 |
| | 253 | + // bubble (due to r0 latency) |
| | 254 | + __asm__ volatile(" sadd8 r0, r0, r4 \n"); // 1 cycle |
| | 255 | + __asm__ volatile(" str r0, [r9] \n"); // 1 cycle, 1 mem, r9 early |
| | 256 | + __asm__ volatile(" bic r2, r0, r6 \n"); // 1 cycle |
| | 257 | + __asm__ volatile(" and r1, r6, r0,lsr#6 \n"); // 1 cycle, r0 early |
| | 258 | + __asm__ volatile(" orr r2, r2, r1 \n"); // 1 cycle |
| | 259 | + __asm__ volatile(" mov r1, r5 \n"); // 1 cycle |
| | 260 | + __asm__ volatile(" shsub8 r5, r0, r2 \n"); // 1 cycle |
| | 261 | + __asm__ volatile(" shadd8 r1, r1, r5 \n"); // 1 cycle |
| 262 | 262 | __asm__ volatile(" str r1, [r7], #4 \n"); // 1 cycle, 1 mem, r7 early |
| 263 | | - __asm__ volatile(" nop \n"); // 2 cycles
|
| 264 | | - __asm__ volatile(" nop \n"); // 2 cycles
|
| 265 | | - __asm__ volatile(" nop \n"); // 2 cycles
|
| 266 | | - __asm__ volatile(" nop \n"); // 2 cycles
|
| | 263 | + __asm__ volatile(" nop \n"); // 2 cycles |
| | 264 | + __asm__ volatile(" nop \n"); // 2 cycles |
| | 265 | + __asm__ volatile(" nop \n"); // 2 cycles |
| | 266 | + __asm__ volatile(" nop \n"); // 2 cycles |
| 267 | 267 | __asm__ volatile(" bne displaylcd_dither_x \n"); |
| 268 | 268 | __asm__ volatile(" add r3, r3, r11 \n"); |
| 269 | 269 | __asm__ volatile(" subs r12, r12, #1 \n"); |
