| Index: emcore/trunk/panic.c |
| — | — | @@ -45,7 +45,7 @@ |
| 46 | 46 | current_thread->state = THREAD_DEFUNCT_ACK;
|
| 47 | 47 | current_thread->block_type = THREAD_DEFUNCT_PANIC;
|
| 48 | 48 | leave_critical_section(mode);
|
| 49 | | - yield();
|
| | 49 | + panic_recover();
|
| 50 | 50 | }
|
| 51 | 51 |
|
| 52 | 52 | void panic(enum panic_severity severity, const char* string)
|
| Index: emcore/trunk/target/ipodnano2g/crt0.S |
| — | — | @@ -144,41 +144,116 @@ |
| 145 | 145 |
|
| 146 | 146 | .type reset_handler, %function
|
| 147 | 147 | reset_handler:
|
| | 148 | + stmfd sp, {r10-r12}
|
| | 149 | + mov r10, sp
|
| | 150 | + mov r11, lr
|
| | 151 | + mrs r12, cpsr
|
| | 152 | + msr cpsr_c, #0xd7
|
| | 153 | + sub sp, sp, #0x44
|
| | 154 | + stmia sp!, {r0-r9}
|
| | 155 | + sub r0, r10, #0xc
|
| | 156 | + ldmia r0, {r0-r2}
|
| | 157 | + mov r3, r10
|
| | 158 | + mov r4, r11
|
| | 159 | + mov r5, r11
|
| | 160 | + mov r6, r12
|
| | 161 | + stmia sp!, {r0-r6}
|
| | 162 | + sub sp, sp, #0x44
|
| 148 | 163 | mov r0, #0
|
| 149 | 164 | adr r1, reset_text
|
| | 165 | + mov r2, r11
|
| 150 | 166 | b panic
|
| 151 | | -reset_text:
|
| 152 | | - .ascii "Hit reset vector!\0"
|
| 153 | 167 | .size reset_handler, .-reset_handler
|
| 154 | 168 |
|
| 155 | 169 | .type undef_instr_handler, %function
|
| 156 | 170 | undef_instr_handler:
|
| | 171 | + sub sp, sp, #0x44
|
| | 172 | + stmia sp!, {r0-r12}
|
| | 173 | + sub r2, lr, #4
|
| | 174 | + mrs r3, spsr
|
| | 175 | + mrs r4, cpsr
|
| | 176 | + orr r0, r3, #0xc0
|
| | 177 | + msr cpsr_c, r0
|
| | 178 | + mov r0, sp
|
| | 179 | + mov r1, lr
|
| | 180 | + msr cpsr_c, r4
|
| | 181 | + stmia sp!, {r0-r3}
|
| | 182 | + sub sp, sp, #0x44
|
| 157 | 183 | mov r0, #0
|
| 158 | 184 | adr r1, undef_instr_text
|
| 159 | | - sub r2, lr, #4
|
| | 185 | + ldr r3, [r2]
|
| 160 | 186 | b panicf
|
| 161 | 187 | .size undef_instr_handler, .-undef_instr_handler
|
| 162 | 188 |
|
| 163 | 189 | .type prefetch_abort_handler, %function
|
| 164 | 190 | prefetch_abort_handler:
|
| | 191 | + sub sp, sp, #0x44
|
| | 192 | + stmia sp!, {r0-r12}
|
| | 193 | + sub r2, lr, #4
|
| | 194 | + mrs r3, spsr
|
| | 195 | + mrs r4, cpsr
|
| | 196 | + orr r0, r3, #0xc0
|
| | 197 | + msr cpsr_c, r0
|
| | 198 | + mov r0, sp
|
| | 199 | + mov r1, lr
|
| | 200 | + msr cpsr_c, r4
|
| | 201 | + stmia sp!, {r0-r3}
|
| | 202 | + sub sp, sp, #0x44
|
| 165 | 203 | mov r0, #0
|
| 166 | 204 | adr r1, prefetch_abort_text
|
| 167 | | - sub r2, lr, #4
|
| | 205 | + mrc p15, 0, r3,c5,c0
|
| | 206 | + mov r4, r3,lsr#4
|
| | 207 | + and r4, r4, #0xf
|
| | 208 | + and r5, r3, #0xf
|
| | 209 | + stmfd sp!, {r4-r5}
|
| 168 | 210 | b panicf
|
| 169 | 211 | .size prefetch_abort_handler, .-prefetch_abort_handler
|
| 170 | 212 |
|
| 171 | 213 | .type data_abort_handler, %function
|
| 172 | 214 | data_abort_handler:
|
| | 215 | + sub sp, sp, #0x44
|
| | 216 | + stmia sp!, {r0-r12}
|
| | 217 | + sub r2, lr, #8
|
| | 218 | + mrs r3, spsr
|
| | 219 | + mrs r4, cpsr
|
| | 220 | + orr r0, r3, #0xc0
|
| | 221 | + msr cpsr_c, r0
|
| | 222 | + mov r0, sp
|
| | 223 | + mov r1, lr
|
| | 224 | + msr cpsr_c, r4
|
| | 225 | + stmia sp!, {r0-r3}
|
| | 226 | + sub sp, sp, #0x44
|
| 173 | 227 | mov r0, #0
|
| 174 | 228 | adr r1, data_abort_text
|
| 175 | | - sub r2, lr, #4
|
| | 229 | + mrc p15, 0, r3,c5,c0
|
| | 230 | + mov r4, r3,lsr#4
|
| | 231 | + and r4, r4, #0xf
|
| | 232 | + and r5, r3, #0xf
|
| | 233 | + mrc p15, 0, r6,c6,c0
|
| | 234 | + stmfd sp!, {r4-r6}
|
| 176 | 235 | b panicf
|
| 177 | 236 | .size data_abort_handler, .-data_abort_handler
|
| 178 | 237 |
|
| 179 | 238 | .type reserved_handler, %function
|
| 180 | 239 | reserved_handler:
|
| | 240 | + stmfd sp, {r10-r12}
|
| | 241 | + mov r10, sp
|
| | 242 | + mov r11, lr
|
| | 243 | + mrs r12, cpsr
|
| | 244 | + msr cpsr_c, #0xd7
|
| | 245 | + sub sp, sp, #0x44
|
| | 246 | + stmia sp!, {r0-r9}
|
| | 247 | + sub r0, r10, #0xc
|
| | 248 | + ldmia r0, {r0-r2}
|
| | 249 | + mov r3, r10
|
| | 250 | + mov r4, r11
|
| | 251 | + mov r5, r11
|
| | 252 | + mov r6, r12
|
| | 253 | + stmia sp!, {r0-r6}
|
| | 254 | + sub sp, sp, #0x44
|
| 181 | 255 | mov r0, #0
|
| 182 | 256 | adr r1, reserved_text
|
| | 257 | + mov r2, r11
|
| 183 | 258 | b panic
|
| 184 | 259 | .size reserved_handler, .-reserved_handler
|
| 185 | 260 |
|
| — | — | @@ -189,21 +264,24 @@ |
| 190 | 265 | b panic
|
| 191 | 266 | .size fiq_handler, .-fiq_handler
|
| 192 | 267 |
|
| | 268 | +prefetch_abort_text:
|
| | 269 | + .ascii "Prefetch abort at %08X!\nFSR: %08X (domain %d, fault %d)\0"
|
| | 270 | +
|
| | 271 | +reset_text:
|
| | 272 | + .ascii "Hit reset vector!\n(Last known PC: %08X)\0"
|
| | 273 | +
|
| 193 | 274 | undef_instr_text:
|
| 194 | | - .ascii "Undefined instruction at %08X!\0"
|
| | 275 | + .ascii "Undefined instruction at %08X!\n(Opcode: %08X)\0"
|
| 195 | 276 |
|
| 196 | | -prefetch_abort_text:
|
| 197 | | - .ascii "Prefetch abort at %08X!\0"
|
| 198 | | -
|
| 199 | 277 | data_abort_text:
|
| 200 | | - .ascii "Data abort at %08X!\0"
|
| | 278 | + .ascii "Data abort at %08X!\nFSR: %08X (domain %d, fault %d)\nAddress: %08X\0"
|
| 201 | 279 |
|
| 202 | | -reserved_text:
|
| 203 | | - .ascii "Hit reserved exception handler!\0"
|
| 204 | | -
|
| 205 | 280 | fiq_text:
|
| 206 | 281 | .ascii "Unhandled FIQ!\0"
|
| 207 | 282 |
|
| | 283 | +reserved_text:
|
| | 284 | + .ascii "Hit reserved exception handler!\n(Last known PC: %08X)\0"
|
| | 285 | +
|
| 208 | 286 | syscall_text:
|
| 209 | 287 | .ascii "Unhandled syscall!\0"
|
| 210 | 288 |
|
| Index: emcore/trunk/target/ipodnano3g/crt0.S |
| — | — | @@ -185,41 +185,116 @@ |
| 186 | 186 |
|
| 187 | 187 | .type reset_handler, %function
|
| 188 | 188 | reset_handler:
|
| | 189 | + stmfd sp, {r10-r12}
|
| | 190 | + mov r10, sp
|
| | 191 | + mov r11, lr
|
| | 192 | + mrs r12, cpsr
|
| | 193 | + msr cpsr_c, #0xd7
|
| | 194 | + sub sp, sp, #0x44
|
| | 195 | + stmia sp!, {r0-r9}
|
| | 196 | + sub r0, r10, #0xc
|
| | 197 | + ldmia r0, {r0-r2}
|
| | 198 | + mov r3, r10
|
| | 199 | + mov r4, r11
|
| | 200 | + mov r5, r11
|
| | 201 | + mov r6, r12
|
| | 202 | + stmia sp!, {r0-r6}
|
| | 203 | + sub sp, sp, #0x44
|
| 189 | 204 | mov r0, #0
|
| 190 | 205 | adr r1, reset_text
|
| | 206 | + mov r2, r11
|
| 191 | 207 | b panic
|
| 192 | | -reset_text:
|
| 193 | | - .ascii "Hit reset vector!\0"
|
| 194 | 208 | .size reset_handler, .-reset_handler
|
| 195 | 209 |
|
| 196 | 210 | .type undef_instr_handler, %function
|
| 197 | 211 | undef_instr_handler:
|
| | 212 | + sub sp, sp, #0x44
|
| | 213 | + stmia sp!, {r0-r12}
|
| | 214 | + sub r2, lr, #4
|
| | 215 | + mrs r3, spsr
|
| | 216 | + mrs r4, cpsr
|
| | 217 | + orr r0, r3, #0xc0
|
| | 218 | + msr cpsr_c, r0
|
| | 219 | + mov r0, sp
|
| | 220 | + mov r1, lr
|
| | 221 | + msr cpsr_c, r4
|
| | 222 | + stmia sp!, {r0-r3}
|
| | 223 | + sub sp, sp, #0x44
|
| 198 | 224 | mov r0, #0
|
| 199 | 225 | adr r1, undef_instr_text
|
| 200 | | - sub r2, lr, #4
|
| | 226 | + ldr r3, [r2]
|
| 201 | 227 | b panicf
|
| 202 | 228 | .size undef_instr_handler, .-undef_instr_handler
|
| 203 | 229 |
|
| 204 | 230 | .type prefetch_abort_handler, %function
|
| 205 | 231 | prefetch_abort_handler:
|
| | 232 | + sub sp, sp, #0x44
|
| | 233 | + stmia sp!, {r0-r12}
|
| | 234 | + sub r2, lr, #4
|
| | 235 | + mrs r3, spsr
|
| | 236 | + mrs r4, cpsr
|
| | 237 | + orr r0, r3, #0xc0
|
| | 238 | + msr cpsr_c, r0
|
| | 239 | + mov r0, sp
|
| | 240 | + mov r1, lr
|
| | 241 | + msr cpsr_c, r4
|
| | 242 | + stmia sp!, {r0-r3}
|
| | 243 | + sub sp, sp, #0x44
|
| 206 | 244 | mov r0, #0
|
| 207 | 245 | adr r1, prefetch_abort_text
|
| 208 | | - sub r2, lr, #4
|
| | 246 | + mrc p15, 0, r3,c5,c0
|
| | 247 | + mov r4, r3,lsr#4
|
| | 248 | + and r4, r4, #0xf
|
| | 249 | + and r5, r3, #0xf
|
| | 250 | + stmfd sp!, {r4-r5}
|
| 209 | 251 | b panicf
|
| 210 | 252 | .size prefetch_abort_handler, .-prefetch_abort_handler
|
| 211 | 253 |
|
| 212 | 254 | .type data_abort_handler, %function
|
| 213 | 255 | data_abort_handler:
|
| | 256 | + sub sp, sp, #0x44
|
| | 257 | + stmia sp!, {r0-r12}
|
| | 258 | + sub r2, lr, #8
|
| | 259 | + mrs r3, spsr
|
| | 260 | + mrs r4, cpsr
|
| | 261 | + orr r0, r3, #0xc0
|
| | 262 | + msr cpsr_c, r0
|
| | 263 | + mov r0, sp
|
| | 264 | + mov r1, lr
|
| | 265 | + msr cpsr_c, r4
|
| | 266 | + stmia sp!, {r0-r3}
|
| | 267 | + sub sp, sp, #0x44
|
| 214 | 268 | mov r0, #0
|
| 215 | 269 | adr r1, data_abort_text
|
| 216 | | - sub r2, lr, #4
|
| | 270 | + mrc p15, 0, r3,c5,c0
|
| | 271 | + mov r4, r3,lsr#4
|
| | 272 | + and r4, r4, #0xf
|
| | 273 | + and r5, r3, #0xf
|
| | 274 | + mrc p15, 0, r6,c6,c0
|
| | 275 | + stmfd sp!, {r4-r6}
|
| 217 | 276 | b panicf
|
| 218 | 277 | .size data_abort_handler, .-data_abort_handler
|
| 219 | 278 |
|
| 220 | 279 | .type reserved_handler, %function
|
| 221 | 280 | reserved_handler:
|
| | 281 | + stmfd sp, {r10-r12}
|
| | 282 | + mov r10, sp
|
| | 283 | + mov r11, lr
|
| | 284 | + mrs r12, cpsr
|
| | 285 | + msr cpsr_c, #0xd7
|
| | 286 | + sub sp, sp, #0x44
|
| | 287 | + stmia sp!, {r0-r9}
|
| | 288 | + sub r0, r10, #0xc
|
| | 289 | + ldmia r0, {r0-r2}
|
| | 290 | + mov r3, r10
|
| | 291 | + mov r4, r11
|
| | 292 | + mov r5, r11
|
| | 293 | + mov r6, r12
|
| | 294 | + stmia sp!, {r0-r6}
|
| | 295 | + sub sp, sp, #0x44
|
| 222 | 296 | mov r0, #0
|
| 223 | 297 | adr r1, reserved_text
|
| | 298 | + mov r2, r11
|
| 224 | 299 | b panic
|
| 225 | 300 | .size reserved_handler, .-reserved_handler
|
| 226 | 301 |
|
| — | — | @@ -230,21 +305,24 @@ |
| 231 | 306 | b panic
|
| 232 | 307 | .size fiq_handler, .-fiq_handler
|
| 233 | 308 |
|
| | 309 | +prefetch_abort_text:
|
| | 310 | + .ascii "Prefetch abort at %08X!\nFSR: %08X (domain %d, fault %d)\0"
|
| | 311 | +
|
| | 312 | +reset_text:
|
| | 313 | + .ascii "Hit reset vector!\n(Last known PC: %08X)\0"
|
| | 314 | +
|
| 234 | 315 | undef_instr_text:
|
| 235 | | - .ascii "Undefined instruction at %08X!\0"
|
| | 316 | + .ascii "Undefined instruction at %08X!\n(Opcode: %08X)\0"
|
| 236 | 317 |
|
| 237 | | -prefetch_abort_text:
|
| 238 | | - .ascii "Prefetch abort at %08X!\0"
|
| 239 | | -
|
| 240 | 318 | data_abort_text:
|
| 241 | | - .ascii "Data abort at %08X!\0"
|
| | 319 | + .ascii "Data abort at %08X!\nFSR: %08X (domain %d, fault %d)\nAddress: %08X\0"
|
| 242 | 320 |
|
| 243 | | -reserved_text:
|
| 244 | | - .ascii "Hit reserved exception handler!\0"
|
| 245 | | -
|
| 246 | 321 | fiq_text:
|
| 247 | 322 | .ascii "Unhandled FIQ!\0"
|
| 248 | 323 |
|
| | 324 | +reserved_text:
|
| | 325 | + .ascii "Hit reserved exception handler!\n(Last known PC: %08X)\0"
|
| | 326 | +
|
| 249 | 327 | syscall_text:
|
| 250 | 328 | .ascii "Unhandled syscall!\0"
|
| 251 | 329 |
|
| Index: emcore/trunk/target/ipodnano4g/crt0.S |
| — | — | @@ -134,41 +134,116 @@ |
| 135 | 135 |
|
| 136 | 136 | .type reset_handler, %function
|
| 137 | 137 | reset_handler:
|
| | 138 | + stmfd sp, {r10-r12}
|
| | 139 | + mov r10, sp
|
| | 140 | + mov r11, lr
|
| | 141 | + mrs r12, cpsr
|
| | 142 | + msr cpsr_c, #0xd7
|
| | 143 | + sub sp, sp, #0x44
|
| | 144 | + stmia sp!, {r0-r9}
|
| | 145 | + sub r0, r10, #0xc
|
| | 146 | + ldmia r0, {r0-r2}
|
| | 147 | + mov r3, r10
|
| | 148 | + mov r4, r11
|
| | 149 | + mov r5, r11
|
| | 150 | + mov r6, r12
|
| | 151 | + stmia sp!, {r0-r6}
|
| | 152 | + sub sp, sp, #0x44
|
| 138 | 153 | mov r0, #0
|
| 139 | 154 | adr r1, reset_text
|
| | 155 | + mov r2, r11
|
| 140 | 156 | b panic
|
| 141 | | -reset_text:
|
| 142 | | - .ascii "Hit reset vector!\0"
|
| 143 | 157 | .size reset_handler, .-reset_handler
|
| 144 | 158 |
|
| 145 | 159 | .type undef_instr_handler, %function
|
| 146 | 160 | undef_instr_handler:
|
| | 161 | + sub sp, sp, #0x44
|
| | 162 | + stmia sp!, {r0-r12}
|
| | 163 | + sub r2, lr, #4
|
| | 164 | + mrs r3, spsr
|
| | 165 | + mrs r4, cpsr
|
| | 166 | + orr r0, r3, #0xc0
|
| | 167 | + msr cpsr_c, r0
|
| | 168 | + mov r0, sp
|
| | 169 | + mov r1, lr
|
| | 170 | + msr cpsr_c, r4
|
| | 171 | + stmia sp!, {r0-r3}
|
| | 172 | + sub sp, sp, #0x44
|
| 147 | 173 | mov r0, #0
|
| 148 | 174 | adr r1, undef_instr_text
|
| 149 | | - sub r2, lr, #4
|
| | 175 | + ldr r3, [r2]
|
| 150 | 176 | b panicf
|
| 151 | 177 | .size undef_instr_handler, .-undef_instr_handler
|
| 152 | 178 |
|
| 153 | 179 | .type prefetch_abort_handler, %function
|
| 154 | 180 | prefetch_abort_handler:
|
| | 181 | + sub sp, sp, #0x44
|
| | 182 | + stmia sp!, {r0-r12}
|
| | 183 | + sub r2, lr, #4
|
| | 184 | + mrs r3, spsr
|
| | 185 | + mrs r4, cpsr
|
| | 186 | + orr r0, r3, #0xc0
|
| | 187 | + msr cpsr_c, r0
|
| | 188 | + mov r0, sp
|
| | 189 | + mov r1, lr
|
| | 190 | + msr cpsr_c, r4
|
| | 191 | + stmia sp!, {r0-r3}
|
| | 192 | + sub sp, sp, #0x44
|
| 155 | 193 | mov r0, #0
|
| 156 | 194 | adr r1, prefetch_abort_text
|
| 157 | | - sub r2, lr, #4
|
| | 195 | + mrc p15, 0, r3,c5,c0,1
|
| | 196 | + mov r4, r3,lsr#4
|
| | 197 | + and r4, r4, #0xf
|
| | 198 | + and r5, r3, #0xf
|
| | 199 | + stmfd sp!, {r4-r5}
|
| 158 | 200 | b panicf
|
| 159 | 201 | .size prefetch_abort_handler, .-prefetch_abort_handler
|
| 160 | 202 |
|
| 161 | 203 | .type data_abort_handler, %function
|
| 162 | 204 | data_abort_handler:
|
| | 205 | + sub sp, sp, #0x44
|
| | 206 | + stmia sp!, {r0-r12}
|
| | 207 | + sub r2, lr, #8
|
| | 208 | + mrs r3, spsr
|
| | 209 | + mrs r4, cpsr
|
| | 210 | + orr r0, r3, #0xc0
|
| | 211 | + msr cpsr_c, r0
|
| | 212 | + mov r0, sp
|
| | 213 | + mov r1, lr
|
| | 214 | + msr cpsr_c, r4
|
| | 215 | + stmia sp!, {r0-r3}
|
| | 216 | + sub sp, sp, #0x44
|
| 163 | 217 | mov r0, #0
|
| 164 | 218 | adr r1, data_abort_text
|
| 165 | | - sub r2, lr, #4
|
| | 219 | + mrc p15, 0, r3,c5,c0
|
| | 220 | + mov r4, r3,lsr#4
|
| | 221 | + and r4, r4, #0xf
|
| | 222 | + and r5, r3, #0xf
|
| | 223 | + mrc p15, 0, r6,c6,c0
|
| | 224 | + stmfd sp!, {r4-r6}
|
| 166 | 225 | b panicf
|
| 167 | 226 | .size data_abort_handler, .-data_abort_handler
|
| 168 | 227 |
|
| 169 | 228 | .type reserved_handler, %function
|
| 170 | 229 | reserved_handler:
|
| | 230 | + stmfd sp, {r10-r12}
|
| | 231 | + mov r10, sp
|
| | 232 | + mov r11, lr
|
| | 233 | + mrs r12, cpsr
|
| | 234 | + msr cpsr_c, #0xd7
|
| | 235 | + sub sp, sp, #0x44
|
| | 236 | + stmia sp!, {r0-r9}
|
| | 237 | + sub r0, r10, #0xc
|
| | 238 | + ldmia r0, {r0-r2}
|
| | 239 | + mov r3, r10
|
| | 240 | + mov r4, r11
|
| | 241 | + mov r5, r11
|
| | 242 | + mov r6, r12
|
| | 243 | + stmia sp!, {r0-r6}
|
| | 244 | + sub sp, sp, #0x44
|
| 171 | 245 | mov r0, #0
|
| 172 | 246 | adr r1, reserved_text
|
| | 247 | + mov r2, r11
|
| 173 | 248 | b panic
|
| 174 | 249 | .size reserved_handler, .-reserved_handler
|
| 175 | 250 |
|
| — | — | @@ -179,21 +254,24 @@ |
| 180 | 255 | b panic
|
| 181 | 256 | .size fiq_handler, .-fiq_handler
|
| 182 | 257 |
|
| | 258 | +prefetch_abort_text:
|
| | 259 | + .ascii "Prefetch abort at %08X!\nFSR: %08X (domain %d, fault %d)\0"
|
| | 260 | +
|
| | 261 | +reset_text:
|
| | 262 | + .ascii "Hit reset vector!\n(Last known PC: %08X)\0"
|
| | 263 | +
|
| 183 | 264 | undef_instr_text:
|
| 184 | | - .ascii "Undefined instruction at %08X!\0"
|
| | 265 | + .ascii "Undefined instruction at %08X!\n(Opcode: %08X)\0"
|
| 185 | 266 |
|
| 186 | | -prefetch_abort_text:
|
| 187 | | - .ascii "Prefetch abort at %08X!\0"
|
| 188 | | -
|
| 189 | 267 | data_abort_text:
|
| 190 | | - .ascii "Data abort at %08X!\0"
|
| | 268 | + .ascii "Data abort at %08X!\nFSR: %08X (domain %d, fault %d)\nAddress: %08X\0"
|
| 191 | 269 |
|
| 192 | | -reserved_text:
|
| 193 | | - .ascii "Hit reserved exception handler!\0"
|
| 194 | | -
|
| 195 | 270 | fiq_text:
|
| 196 | 271 | .ascii "Unhandled FIQ!\0"
|
| 197 | 272 |
|
| | 273 | +reserved_text:
|
| | 274 | + .ascii "Hit reserved exception handler!\n(Last known PC: %08X)\0"
|
| | 275 | +
|
| 198 | 276 | syscall_text:
|
| 199 | 277 | .ascii "Unhandled syscall!\0"
|
| 200 | 278 |
|
| Index: emcore/trunk/target/ipodclassic/crt0.S |
| — | — | @@ -185,41 +185,116 @@ |
| 186 | 186 |
|
| 187 | 187 | .type reset_handler, %function
|
| 188 | 188 | reset_handler:
|
| | 189 | + stmfd sp, {r10-r12}
|
| | 190 | + mov r10, sp
|
| | 191 | + mov r11, lr
|
| | 192 | + mrs r12, cpsr
|
| | 193 | + msr cpsr_c, #0xd7
|
| | 194 | + sub sp, sp, #0x44
|
| | 195 | + stmia sp!, {r0-r9}
|
| | 196 | + sub r0, r10, #0xc
|
| | 197 | + ldmia r0, {r0-r2}
|
| | 198 | + mov r3, r10
|
| | 199 | + mov r4, r11
|
| | 200 | + mov r5, r11
|
| | 201 | + mov r6, r12
|
| | 202 | + stmia sp!, {r0-r6}
|
| | 203 | + sub sp, sp, #0x44
|
| 189 | 204 | mov r0, #0
|
| 190 | 205 | adr r1, reset_text
|
| | 206 | + mov r2, r11
|
| 191 | 207 | b panic
|
| 192 | | -reset_text:
|
| 193 | | - .ascii "Hit reset vector!\0"
|
| 194 | 208 | .size reset_handler, .-reset_handler
|
| 195 | 209 |
|
| 196 | 210 | .type undef_instr_handler, %function
|
| 197 | 211 | undef_instr_handler:
|
| | 212 | + sub sp, sp, #0x44
|
| | 213 | + stmia sp!, {r0-r12}
|
| | 214 | + sub r2, lr, #4
|
| | 215 | + mrs r3, spsr
|
| | 216 | + mrs r4, cpsr
|
| | 217 | + orr r0, r3, #0xc0
|
| | 218 | + msr cpsr_c, r0
|
| | 219 | + mov r0, sp
|
| | 220 | + mov r1, lr
|
| | 221 | + msr cpsr_c, r4
|
| | 222 | + stmia sp!, {r0-r3}
|
| | 223 | + sub sp, sp, #0x44
|
| 198 | 224 | mov r0, #0
|
| 199 | 225 | adr r1, undef_instr_text
|
| 200 | | - sub r2, lr, #4
|
| | 226 | + ldr r3, [r2]
|
| 201 | 227 | b panicf
|
| 202 | 228 | .size undef_instr_handler, .-undef_instr_handler
|
| 203 | 229 |
|
| 204 | 230 | .type prefetch_abort_handler, %function
|
| 205 | 231 | prefetch_abort_handler:
|
| | 232 | + sub sp, sp, #0x44
|
| | 233 | + stmia sp!, {r0-r12}
|
| | 234 | + sub r2, lr, #4
|
| | 235 | + mrs r3, spsr
|
| | 236 | + mrs r4, cpsr
|
| | 237 | + orr r0, r3, #0xc0
|
| | 238 | + msr cpsr_c, r0
|
| | 239 | + mov r0, sp
|
| | 240 | + mov r1, lr
|
| | 241 | + msr cpsr_c, r4
|
| | 242 | + stmia sp!, {r0-r3}
|
| | 243 | + sub sp, sp, #0x44
|
| 206 | 244 | mov r0, #0
|
| 207 | 245 | adr r1, prefetch_abort_text
|
| 208 | | - sub r2, lr, #4
|
| | 246 | + mrc p15, 0, r3,c5,c0
|
| | 247 | + mov r4, r3,lsr#4
|
| | 248 | + and r4, r4, #0xf
|
| | 249 | + and r5, r3, #0xf
|
| | 250 | + stmfd sp!, {r4-r5}
|
| 209 | 251 | b panicf
|
| 210 | 252 | .size prefetch_abort_handler, .-prefetch_abort_handler
|
| 211 | 253 |
|
| 212 | 254 | .type data_abort_handler, %function
|
| 213 | 255 | data_abort_handler:
|
| | 256 | + sub sp, sp, #0x44
|
| | 257 | + stmia sp!, {r0-r12}
|
| | 258 | + sub r2, lr, #8
|
| | 259 | + mrs r3, spsr
|
| | 260 | + mrs r4, cpsr
|
| | 261 | + orr r0, r3, #0xc0
|
| | 262 | + msr cpsr_c, r0
|
| | 263 | + mov r0, sp
|
| | 264 | + mov r1, lr
|
| | 265 | + msr cpsr_c, r4
|
| | 266 | + stmia sp!, {r0-r3}
|
| | 267 | + sub sp, sp, #0x44
|
| 214 | 268 | mov r0, #0
|
| 215 | 269 | adr r1, data_abort_text
|
| 216 | | - sub r2, lr, #4
|
| | 270 | + mrc p15, 0, r3,c5,c0
|
| | 271 | + mov r4, r3,lsr#4
|
| | 272 | + and r4, r4, #0xf
|
| | 273 | + and r5, r3, #0xf
|
| | 274 | + mrc p15, 0, r6,c6,c0
|
| | 275 | + stmfd sp!, {r4-r6}
|
| 217 | 276 | b panicf
|
| 218 | 277 | .size data_abort_handler, .-data_abort_handler
|
| 219 | 278 |
|
| 220 | 279 | .type reserved_handler, %function
|
| 221 | 280 | reserved_handler:
|
| | 281 | + stmfd sp, {r10-r12}
|
| | 282 | + mov r10, sp
|
| | 283 | + mov r11, lr
|
| | 284 | + mrs r12, cpsr
|
| | 285 | + msr cpsr_c, #0xd7
|
| | 286 | + sub sp, sp, #0x44
|
| | 287 | + stmia sp!, {r0-r9}
|
| | 288 | + sub r0, r10, #0xc
|
| | 289 | + ldmia r0, {r0-r2}
|
| | 290 | + mov r3, r10
|
| | 291 | + mov r4, r11
|
| | 292 | + mov r5, r11
|
| | 293 | + mov r6, r12
|
| | 294 | + stmia sp!, {r0-r6}
|
| | 295 | + sub sp, sp, #0x44
|
| 222 | 296 | mov r0, #0
|
| 223 | 297 | adr r1, reserved_text
|
| | 298 | + mov r2, r11
|
| 224 | 299 | b panic
|
| 225 | 300 | .size reserved_handler, .-reserved_handler
|
| 226 | 301 |
|
| — | — | @@ -230,21 +305,24 @@ |
| 231 | 306 | b panic
|
| 232 | 307 | .size fiq_handler, .-fiq_handler
|
| 233 | 308 |
|
| | 309 | +prefetch_abort_text:
|
| | 310 | + .ascii "Prefetch abort at %08X!\nFSR: %08X (domain %d, fault %d)\0"
|
| | 311 | +
|
| | 312 | +reset_text:
|
| | 313 | + .ascii "Hit reset vector!\n(Last known PC: %08X)\0"
|
| | 314 | +
|
| 234 | 315 | undef_instr_text:
|
| 235 | | - .ascii "Undefined instruction at %08X!\0"
|
| | 316 | + .ascii "Undefined instruction at %08X!\n(Opcode: %08X)\0"
|
| 236 | 317 |
|
| 237 | | -prefetch_abort_text:
|
| 238 | | - .ascii "Prefetch abort at %08X!\0"
|
| 239 | | -
|
| 240 | 318 | data_abort_text:
|
| 241 | | - .ascii "Data abort at %08X!\0"
|
| | 319 | + .ascii "Data abort at %08X!\nFSR: %08X (domain %d, fault %d)\nAddress: %08X\0"
|
| 242 | 320 |
|
| 243 | | -reserved_text:
|
| 244 | | - .ascii "Hit reserved exception handler!\0"
|
| 245 | | -
|
| 246 | 321 | fiq_text:
|
| 247 | 322 | .ascii "Unhandled FIQ!\0"
|
| 248 | 323 |
|
| | 324 | +reserved_text:
|
| | 325 | + .ascii "Hit reserved exception handler!\n(Last known PC: %08X)\0"
|
| | 326 | +
|
| 249 | 327 | syscall_text:
|
| 250 | 328 | .ascii "Unhandled syscall!\0"
|
| 251 | 329 |
|
| Index: emcore/trunk/arm/contextswitch.S |
| — | — | @@ -23,8 +23,31 @@ |
| 24 | 24 | #define ASM_FILE
|
| 25 | 25 | #include "global.h"
|
| 26 | 26 |
|
| 27 | | -.section .icode.yield, "ax", %progbits
|
| | 27 | +.section .icode.contextswitch, "ax", %progbits
|
| 28 | 28 | .align 2
|
| | 29 | +.global panic_recover
|
| | 30 | +.type panic_recover, %function
|
| | 31 | +panic_recover:
|
| | 32 | + mrs r0, cpsr
|
| | 33 | + and r0, r0, #0x1f
|
| | 34 | + cmp r0, #0x17
|
| | 35 | + cmpne r0, #0x1b
|
| | 36 | + bne yield
|
| | 37 | + ldr sp, =_abortstackend - 0x44
|
| | 38 | + ldr r9, =current_thread
|
| | 39 | + ldr lr, [r9]
|
| | 40 | + ldmia sp!, {r0-r7}
|
| | 41 | + stmia lr!, {r0-r7}
|
| | 42 | + ldmia sp!, {r0-r8}
|
| | 43 | + stmia lr!, {r0-r8}
|
| | 44 | + msr cpsr_c, #0xd2
|
| | 45 | + bl scheduler_pause_accounting
|
| | 46 | + adr lr, resume_thread
|
| | 47 | + mov r0, #0
|
| | 48 | + mov r1, r9
|
| | 49 | + b scheduler_switch
|
| | 50 | +.size panic_recover, .-panic_recover
|
| | 51 | +
|
| 29 | 52 | .global yield
|
| 30 | 53 | .type yield, %function
|
| 31 | 54 | yield:
|
| Index: emcore/trunk/contextswitch.h |
| — | — | @@ -29,6 +29,7 @@ |
| 30 | 30 |
|
| 31 | 31 |
|
| 32 | 32 | void handle_irq(void) __attribute__((noreturn)) ICODE_ATTR;
|
| | 33 | +void panic_recover() ICODE_ATTR;
|
| 33 | 34 | void yield() ICODE_ATTR;
|
| 34 | 35 | void resume_thread(void) __attribute__((noreturn)) ICODE_ATTR;
|
| 35 | 36 | uint32_t enter_critical_section(void) ICODE_ATTR;
|
