| Index: embios/trunk/target/ipodnano2g/clockgates.c |
| — | — | @@ -27,6 +27,8 @@ |
| 28 | 28 |
|
| 29 | 29 | void clockgate_enable(int gate, bool enable)
|
| 30 | 30 | {
|
| | 31 | + uint32_t mode = enter_critical_section();
|
| 31 | 32 | if (enable) PWRCON(gate >> 5) &= ~(1 << (gate & 0x1f));
|
| 32 | 33 | else PWRCON(gate >> 5) |= 1 << (gate & 0x1f);
|
| | 34 | + leave_critical_section(mode);
|
| 33 | 35 | }
|
| Index: embios/trunk/target/ipodnano2g/hwkeyaes.c |
| — | — | @@ -27,10 +27,14 @@ |
| 28 | 28 | #include "thread.h"
|
| 29 | 29 |
|
| 30 | 30 |
|
| | 31 | +struct mutex hwkeyaes_mutex;
|
| | 32 | +
|
| | 33 | +
|
| 31 | 34 | void hwkeyaes(enum hwkeyaes_direction direction, uint32_t keyidx, void* data, uint32_t size)
|
| 32 | 35 | {
|
| 33 | 36 | uint32_t ptr, i;
|
| 34 | 37 | uint32_t go = 1;
|
| | 38 | + mutex_lock(&hwkeyaes_mutex, TIMEOUT_BLOCK);
|
| 35 | 39 | PWRCON(1) &= ~0x400;
|
| 36 | 40 | AESTYPE = keyidx;
|
| 37 | 41 | AESUNKREG0 = 1;
|
| — | — | @@ -70,4 +74,5 @@ |
| 71 | 75 | }
|
| 72 | 76 | AESCONTROL = 0;
|
| 73 | 77 | PWRCON(1) |= 0x400;
|
| | 78 | + mutex_unlock(&hwkeyaes_mutex);
|
| 74 | 79 | }
|
| Index: embios/trunk/target/ipodnano2g/hmacsha1.c |
| — | — | @@ -27,10 +27,14 @@ |
| 28 | 28 | #include "thread.h"
|
| 29 | 29 |
|
| 30 | 30 |
|
| | 31 | +struct mutex hmacsha1_mutex;
|
| | 32 | +
|
| | 33 | +
|
| 31 | 34 | void hmacsha1(void* data, uint32_t size, void* result)
|
| 32 | 35 | {
|
| 33 | 36 | uint32_t ptr, i;
|
| 34 | 37 | uint32_t ctrl = 2;
|
| | 38 | + mutex_lock(&hmacsha1_mutex, TIMEOUT_BLOCK);
|
| 35 | 39 | PWRCON(1) &= ~4;
|
| 36 | 40 | for (ptr = 0; ptr < (size >> 2); ptr += 0x10)
|
| 37 | 41 | {
|
| — | — | @@ -41,4 +45,5 @@ |
| 42 | 46 | }
|
| 43 | 47 | for (i = 0; i < 5; i ++) ((uint32_t*)result)[i] = HASHRESULT[i];
|
| 44 | 48 | PWRCON(1) |= 4;
|
| | 49 | + mutex_unlock(&hmacsha1_mutex);
|
| 45 | 50 | }
|
| Index: embios/trunk/target/ipodnano2g/interrupt.c |
| — | — | @@ -132,8 +132,10 @@ |
| 133 | 133 |
|
| 134 | 134 | void interrupt_enable(int irq, bool state)
|
| 135 | 135 | {
|
| | 136 | + uint32_t mode = enter_critical_section();
|
| 136 | 137 | if (state) INTMSK |= 1 << irq;
|
| 137 | 138 | else INTMSK &= ~(1 << irq);
|
| | 139 | + leave_critical_section(mode);
|
| 138 | 140 | }
|
| 139 | 141 |
|
| 140 | 142 | void interrupt_set_handler(int irq, void* handler)
|
| Index: embios/trunk/target/ipodnano3g/clockgates.c |
| — | — | @@ -27,6 +27,8 @@ |
| 28 | 28 |
|
| 29 | 29 | void clockgate_enable(int gate, bool enable)
|
| 30 | 30 | {
|
| | 31 | + uint32_t mode = enter_critical_section();
|
| 31 | 32 | if (enable) PWRCON(gate >> 5) &= ~(1 << (gate & 0x1f));
|
| 32 | 33 | else PWRCON(gate >> 5) |= 1 << (gate & 0x1f);
|
| | 34 | + leave_critical_section(mode);
|
| 33 | 35 | }
|
| Index: embios/trunk/target/ipodnano3g/hwkeyaes.c |
| — | — | @@ -27,9 +27,13 @@ |
| 28 | 28 | #include "thread.h"
|
| 29 | 29 |
|
| 30 | 30 |
|
| | 31 | +struct mutex hwkeyaes_mutex;
|
| | 32 | +
|
| | 33 | +
|
| 31 | 34 | void hwkeyaes(enum hwkeyaes_direction direction, uint32_t keyidx, void* data, uint32_t size)
|
| 32 | 35 | {
|
| 33 | 36 | int i;
|
| | 37 | + mutex_lock(&hwkeyaes_mutex, TIMEOUT_BLOCK);
|
| 34 | 38 | clockgate_enable(10, true);
|
| 35 | 39 | for (i = 0; i < 4; i++) AESIV[i] = 0;
|
| 36 | 40 | AESUNKREG0 = 1;
|
| — | — | @@ -52,4 +56,5 @@ |
| 53 | 57 | invalidate_dcache();
|
| 54 | 58 | while (!(AESSTATUS & 0xf)) sleep(100);
|
| 55 | 59 | clockgate_enable(10, false);
|
| | 60 | + mutex_unlock(&hwkeyaes_mutex);
|
| 56 | 61 | }
|
