S5l8702 clocking

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Revision as of 22:22, 9 February 2011 by TheSeven (talk | contribs) (Created page with "<pre> 0x3c500000: CLKCON0 (00003000) Bits 0-3: CPU clock divider factor (n+1) Bit 4: CPU clock divider enable Bits 12-13: CPU clock source (0: OSC, 1-3: PLL0-2) 0x3c500004: CLK...")
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0x3c500000: CLKCON0 (00003000)
Bits 0-3: CPU clock divider factor (n+1)
Bit 4: CPU clock divider enable
Bits 12-13: CPU clock source (0: OSC, 1-3: PLL0-2)


0x3c500004: CLKCON1 (00404101)
Bits 8-15: AHB=>APB divider
Bits 16-23: CPU=>AHB divider


0x3c500008: CLKCON2 (80008000)
0x3c50000c: CLKCON3 (80008000)
0x3c500010: CLKCON4 (00008000)
0x3c500014: CLKCON5 (00008000)
Bits 0-3: Clock divider factor (n+1)
Bit 3: Clock divider enable
Bits 12-13: Clock source (0: OSC, 1-2: PLL0-2)
Bit 15: Disable clock


0x3c500018: Unknown (00000000)
0x3c50001c: Unknown (00000000)


0x3c500020: PLL0PMS (01002402: P=1, M=36, S=4) m: 294912Hz, d: 216000000Hz
0x3c500024: PLL1PMS (2700a900: P=39, M=169, S=1) m: 215973888Hz, d: 104000000Hz
0x3c500028: PLL2PMS (01002401: P=1, M=36, S=2) m: 589824Hz, d: 432000000Hz
0x3c50002c: PLL3PMS (00000000: invalid)
Bits 0-1: SDIV (2^n)
Bits 8-17: MDIV
Bits 24-29: PDIV


0x3c500030: PLL0LCNT (00000e10)
0x3c500034: PLL1LCNT (00000000)
0x3c500038: PLL2LCNT (00007e90)
0x3c50003c: PLL3LCNT (00000000)


0x3c500040: PLLLOCK (00000044)
Bits 0-3: PLL 0-3 locked


0x3c500044: PLLMODE (00040034)
Bits 0-3: PLL 0-3 enable
Bits 4-7: PLL 0-3 mode (0: multiply, 1: divide)



0x3c500048: PWRCON0 (fdffffe1)
0x3c50004c: PWRCON1 (0003efd5)


0x3c500050: Unknown (00000000)
0x3c500054: Unknown (00000001)


0x3c500058: PWRCON2 (00000000)


0x3c50005c: Unknown (00000000)
0x3c500060: Unknown (00000000)
0x3c500064: Unknown (00000000)


0x3c500068: PWRCON3 (00000000)
0x3c50006c: PWRCON4 (00000000)


0x3c500070: Unknown (00000000)
0x3c500074: Unknown (00000000)
0x3c500078: Unknown (00000000)
0x3c50007c: Unknown (00000000)