Nano 3G/Memory Map
| Address | Description | Notes |
|---|---|---|
| 0x100000000 - 0x4000_0000 | ||
| 0x4000_0000 - 0x3800_0000 | I/O Area | See table below |
| 0x3800_0000 - 0x2204_0000 | ||
| 0x2204_0000 - 0x2200_0000 | On-chip SRAM | Always accessible |
| 0x2200_0000 - 0x2000_C800 | ||
| 0x2000_C800 - 0x2000_0000 | Boot ROM | Executed by processor at start up |
| 0x2000_0000 - 0x0C00_0000 | ||
| 0x0C00_0000 - 0x0A00_0000 | SDRAM Mirror 2 | Same contents as mirror 1 |
| 0x0A00_0000 - 0x0800_0000 | SDRAM Mirror 1 | Needs initialization |
| 0x0800_0000 - 0x0000_0000 |
IO Map
| Address | Description | Notes |
|---|---|---|
| 0x3C80_0000 0x3C80_0004 |
WDTCON WDTCNT |
Watchdog timer[1] |
| 0x38E0_0000 - 0x38E0_1000 0x38E0_1000 - 0x38E0_2000 |
VIC0 Base VIC1 Base |
Vectored Interrupt Controller[2] |
- ↑ See S5L8700 datasheet
- ↑ Cite error: Invalid
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