Latest revision as of 03:10, 22 May 2011

Address	Description	Notes
`0x100000000 - 0x4000_0000`
`0x4000_0000 - 0x3800_0000`	I/O Area	See table below
`0x3800_0000 - 0x2204_0000`
`0x2204_0000 - 0x2200_0000`	On-chip SRAM	Always accessible
`0x2200_0000 - 0x2000_C800`
`0x2000_C800 - 0x2000_0000`	Boot ROM	Executed by processor at start up
`0x2000_0000 - 0x0C00_0000`
`0x0C00_0000 - 0x0A00_0000`	SDRAM Mirror 2	Same contents as mirror 1
`0x0A00_0000 - 0x0800_0000`	SDRAM Mirror 1	Needs initialization
`0x0800_0000 - 0x0000_0000`

IO Map

Address	Description	Notes
`0x3C80_0000 0x3C80_0004`	WDTCON WDTCNT	Watchdog timer^[1]
`0x38E0_1000 - 0x38E0_0000 0x38E0_2000 - 0x38E0_1000`	VIC0 Base VIC1 Base	Vectored Interrupt Controller^[2]

@@ Line 33: / Line 33: @@
 | <tt>0x3C80_0000<br />0x3C80_0004</tt> || WDTCON<br />WDTCNT || Watchdog timer<ref name="datasheet" />
 |-
-| <tt>0x38E0_0000 - 0x38E0_1000<br />0x38E0_1000 - 0x38E0_2000</tt> || VIC0 Base<br />VIC1 Base || Vectored Interrupt Controller<ref name="vic_ds" />
+| <tt>0x38E0_1000 - 0x38E0_0000<br />0x38E0_2000 - 0x38E0_1000</tt> || VIC0 Base<br />VIC1 Base || Vectored Interrupt Controller<ref name="vic_ds" />
 |-
 |}