Nano 3G/Memory Map: Difference between revisions

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! Address !! Description !! Notes
! Address !! Description !! Notes
|-
|-
| <tt>0xFFFF_FFFF - 0x4000_0000</tt> || ||
| <tt>0x100000000 - 0x4000_0000</tt> || ||
|-
|-
| <tt>0x3FFF_FFFF - 0x3800_0000</tt> || I/O Area || See table below
| <tt>0x4000_0000 - 0x3800_0000</tt> || I/O Area || See table below
|-
|-
| <tt>0x37FF_FFFF - 0x2204_0000</tt> || ||
| <tt>0x3800_0000 - 0x2204_0000</tt> || ||
|-
|-
| <tt>0x2203_FFFF - 0x2200_0000</tt> || On-chip SRAM || Always accessible
| <tt>0x2204_0000 - 0x2200_0000</tt> || On-chip SRAM || Always accessible
|-
|-
| <tt>0x21FF_FFFF - 0x2000_C800</tt> || ||
| <tt>0x2200_0000 - 0x2000_C800</tt> || ||
|-
|-
| <tt>0x2000_C7FF - 0x2000_0000</tt> || Boot ROM || Executed by processor at start up
| <tt>0x2000_C800 - 0x2000_0000</tt> || Boot ROM || Executed by processor at start up
|-
|-
| <tt>0x1FFF_FFFF - 0x0C00_0000</tt> || ||
| <tt>0x2000_0000 - 0x0C00_0000</tt> || ||
|-
|-
| <tt>0x0BFF_FFFF - 0x0A00_0000</tt> || SDRAM Mirror 2 || Same contents as mirror 1
| <tt>0x0C00_0000 - 0x0A00_0000</tt> || SDRAM Mirror 2 || Same contents as mirror 1
|-
|-
| <tt>0x09FF_FFFF - 0x0800_0000</tt> || SDRAM Mirror 1 || Needs initialization
| <tt>0x0A00_0000 - 0x0800_0000</tt> || SDRAM Mirror 1 || Needs initialization
|-
|-
| <tt>0x07FF_FFFF - 0x0000_0000</tt> || ||
| <tt>0x0800_0000 - 0x0000_0000</tt> || ||
|-
|-
|}
|}

Revision as of 01:09, 22 May 2011

Address Description Notes
0x100000000 - 0x4000_0000
0x4000_0000 - 0x3800_0000 I/O Area See table below
0x3800_0000 - 0x2204_0000
0x2204_0000 - 0x2200_0000 On-chip SRAM Always accessible
0x2200_0000 - 0x2000_C800
0x2000_C800 - 0x2000_0000 Boot ROM Executed by processor at start up
0x2000_0000 - 0x0C00_0000
0x0C00_0000 - 0x0A00_0000 SDRAM Mirror 2 Same contents as mirror 1
0x0A00_0000 - 0x0800_0000 SDRAM Mirror 1 Needs initialization
0x0800_0000 - 0x0000_0000

IO Map

Address Description Notes
0x3C80_0000
0x3C80_0004		 WDTCON
WDTCNT		 Watchdog timer[1]
0x38E0_0000 - 0x38E0_1000
0x38E0_1000 - 0x38E0_2000		 VIC0 Base
VIC1 Base		 Vectored Interrupt Controller[2]
  1. ↑ See S5L8700 datasheet
  2. ↑ Cite error: Invalid <ref> tag; no text was provided for refs named vic_ds
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