Difference between revisions of "Nano 3G/Memory Map"
(Added blank sections and reversed address ranges) |
(Some other stuff) |
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|- | |- | ||
| <tt>0x2203 FFFF - 0x2200 0000</tt> || On-chip SRAM || Always accessible | | <tt>0x2203 FFFF - 0x2200 0000</tt> || On-chip SRAM || Always accessible | ||
| + | |- | ||
| + | | <tt>0x21FF FFFF - 0x2000 C800</tt> || || | ||
| + | |- | ||
| + | | <tt>0x2000 C7FF - 0x2000 0000</tt> || Boot ROM || Executed by processor at start up | ||
| + | |- | ||
| + | | <tt>0x1FFF FFFF - 0x0C00 0000</tt> || || | ||
|- | |- | ||
| <tt>0x0BFF FFFF - 0x0A00 0000</tt> || SDRAM Mirror 2 || Same contents as mirror 1 | | <tt>0x0BFF FFFF - 0x0A00 0000</tt> || SDRAM Mirror 2 || Same contents as mirror 1 | ||
Revision as of 14:22, 29 November 2010
| Address | Description | Notes |
|---|---|---|
| 0xFFFF FFFF - 0x2204 0000 | ||
| 0x2203 FFFF - 0x2200 0000 | On-chip SRAM | Always accessible |
| 0x21FF FFFF - 0x2000 C800 | ||
| 0x2000 C7FF - 0x2000 0000 | Boot ROM | Executed by processor at start up |
| 0x1FFF FFFF - 0x0C00 0000 | ||
| 0x0BFF FFFF - 0x0A00 0000 | SDRAM Mirror 2 | Same contents as mirror 1 |
| 0x09FF FFFF - 0x0800 0000 | SDRAM Mirror 1 | Needs initialization |
| 0x07FF FFFF - 0x0000 0000 |
