Difference between revisions of "Nano 3G/Memory Map"

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(crappy memory map)
 
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! Address !! Description !! Notes
 
! Address !! Description !! Notes
 
|-
 
|-
−
| <tt>0x2200 0000 - 0x2203 FFFF</tt> || On-chip SRAM || Always accessible
+
| <tt>0x100000000 - 0x4000_0000</tt> || ||
 
|-
 
|-
−
| <tt>0x0A00 0000 - 0x0BFF FFFF</tt> || SDRAM Mirror 2 || Same contents as mirror 1
+
| <tt>0x4000_0000 - 0x3800_0000</tt> || I/O Area || See table below
 
|-
 
|-
−
| <tt>0x0800 0000 - 0x09FF FFFF</tt> || SDRAM Mirror 1 || Needs initialization
+
| <tt>0x3800_0000 - 0x2204_0000</tt> || ||
 +
|-
 +
| <tt>0x2204_0000 - 0x2200_0000</tt> || On-chip SRAM || Always accessible
 +
|-
 +
| <tt>0x2200_0000 - 0x2000_C800</tt> || ||
 +
|-
 +
| <tt>0x2000_C800 - 0x2000_0000</tt> || Boot ROM || Executed by processor at start up
 +
|-
 +
| <tt>0x2000_0000 - 0x0C00_0000</tt> || ||
 +
|-
 +
| <tt>0x0C00_0000 - 0x0A00_0000</tt> || SDRAM Mirror 2 || Same contents as mirror 1
 +
|-
 +
| <tt>0x0A00_0000 - 0x0800_0000</tt> || SDRAM Mirror 1 || Needs initialization
 +
|-
 +
| <tt>0x0800_0000 - 0x0000_0000</tt> || ||
 +
|-
 +
|}
 +
 
 +
= IO Map =
 +
 
 +
{| class="wikitable"
 +
|-
 +
! Address !! Description !! Notes
 +
|-
 +
| <tt>0x3C80_0000<br />0x3C80_0004</tt> || WDTCON<br />WDTCNT || Watchdog timer<ref name="datasheet" />
 +
|-
 +
| <tt>0x38E0_1000 - 0x38E0_0000<br />0x38E0_2000 - 0x38E0_1000</tt> || VIC0 Base<br />VIC1 Base || Vectored Interrupt Controller<ref name="vic_ds" />
 
|-
 
|-
 
|}
 
|}
 +
 +
<references>
 +
<ref name="datasheet">See [[S5L8700 datasheet]]</ref>
 +
<ref name="vic_ds">ARM PrimeCell Vectored Interrupt Controller (PL192) - [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0273a/DDI0273.pdf Datasheet]
 +
</references>

Latest revision as of 03:10, 22 May 2011

Address Description Notes
0x100000000 - 0x4000_0000
0x4000_0000 - 0x3800_0000 I/O Area See table below
0x3800_0000 - 0x2204_0000
0x2204_0000 - 0x2200_0000 On-chip SRAM Always accessible
0x2200_0000 - 0x2000_C800
0x2000_C800 - 0x2000_0000 Boot ROM Executed by processor at start up
0x2000_0000 - 0x0C00_0000
0x0C00_0000 - 0x0A00_0000 SDRAM Mirror 2 Same contents as mirror 1
0x0A00_0000 - 0x0800_0000 SDRAM Mirror 1 Needs initialization
0x0800_0000 - 0x0000_0000

IO Map

Address Description Notes
0x3C80_0000
0x3C80_0004		 WDTCON
WDTCNT		 Watchdog timer[1]
0x38E0_1000 - 0x38E0_0000
0x38E0_2000 - 0x38E0_1000		 VIC0 Base
VIC1 Base		 Vectored Interrupt Controller[2]
  1. ↑ See S5L8700 datasheet
  2. ↑ Cite error: Invalid <ref> tag; no text was provided for refs named vic_ds
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