Difference between revisions of "S5L8701 analysis"
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| + | [[File:S5L8701_bonding_wires_via_x-ray_bottom_view_2.jpg|200px|thumb|View of the bonding via X-ray]] | ||
| + | [[File:S5L8701_top_layer_bottom_view_2.jpg|200px|thumb|View of the top layer]] | ||
| + | [[File:S5L8701 bottom layer bot view 2.jpg|200px|thumb|View of the bottom layer]] | ||
== Introduction == | == Introduction == | ||
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The chip is a 226-pin TFBGA with a pitch of 0.5mm. | The chip is a 226-pin TFBGA with a pitch of 0.5mm. | ||
| − | This is the structure of a BGA package : [http://www.freepatentsonline.com/6569694-0-display.jpg BGA package] | + | This is the structure of a BGA package: [http://www.freepatentsonline.com/6569694-0-display.jpg BGA package] |
The chip is glued to a small double side PCB substrate. | The chip is glued to a small double side PCB substrate. | ||
| − | the electrical current passes through : | + | the electrical current passes through: |
| − | + | *a pad of the chip die | |
| − | + | *a bonding wire | |
| − | + | *the top layer of the substrate | |
| − | + | *a via | |
| − | + | *the bottom layer | |
| − | + | *finally, the BGA ball | |
The [[S5L8700 datasheet|known datasheet]] shows die pad numbers that need to be correlated to ball numbers (the specified package has a different ball layout). | The [[S5L8700 datasheet|known datasheet]] shows die pad numbers that need to be correlated to ball numbers (the specified package has a different ball layout). | ||
| Line 27: | Line 30: | ||
== Packaging analysis == | == Packaging analysis == | ||
| − | Following steps were made : | + | Following steps were made: |
| − | + | *desoldering of the IC | |
| − | + | *removing of the balls and filler glue | |
| − | + | *X-ray picture | |
| − | + | *microscope picture of the bottom layer | |
| − | + | *removing the bottom layer and most of the substrate (by careful manual grinding) | |
| − | + | *microscope picture of the top layer | |
| − | + | *superposition of these views, and path finding from the die to the ball | |
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
== Guessed pinout table == | == Guessed pinout table == | ||
| − | the pinout is currently under study. See [http://f4eru.free.fr/8701/ here] | + | the pinout is currently under study. See [http://f4eru.free.fr/8701/ here] for the actual status. |
| − | + | This is not an easy part of the work, each pad has to be tested for connections all over the board (most IC's removed). See [[Nano2G HW analysis]] for further PCB analysis. | |
| − | |||
Latest revision as of 02:15, 24 November 2010
Introduction
The samsung S5L8701 is the SOC of the IN2G. This chip is supposed to be close to the 8700 used on some concurrent MP3 players.
We currently know nearly nothing about the differences of both chips, and the further evolutions. There is probably a small unencrypted boot ROM inside, which would be very useful for integrating user SW. Probably containing crypto information. Knowing the location of some JTAG pins could be very helpful.
There is an OpenOffice Calc document describing possible pinouts here. There is also tof's mailing list post.
Structure of the packaging
The chip is a 226-pin TFBGA with a pitch of 0.5mm. This is the structure of a BGA package: BGA package
The chip is glued to a small double side PCB substrate. the electrical current passes through:
- a pad of the chip die
- a bonding wire
- the top layer of the substrate
- a via
- the bottom layer
- finally, the BGA ball
The known datasheet shows die pad numbers that need to be correlated to ball numbers (the specified package has a different ball layout). In order to do this, we make an analysis of the bonding and PCB.
Packaging analysis
Following steps were made:
- desoldering of the IC
- removing of the balls and filler glue
- X-ray picture
- microscope picture of the bottom layer
- removing the bottom layer and most of the substrate (by careful manual grinding)
- microscope picture of the top layer
- superposition of these views, and path finding from the die to the ball
Guessed pinout table
the pinout is currently under study. See here for the actual status. This is not an easy part of the work, each pad has to be tested for connections all over the board (most IC's removed). See Nano2G HW analysis for further PCB analysis.
