| Index: embios/branches/4g_compat/init.c |
| — | — | @@ -24,10 +24,25 @@ |
| 25 | 25 | #include "global.h"
|
| 26 | 26 | #include "lcdconsole.h"
|
| 27 | 27 | #include "console.h"
|
| 28 | | -#include "accel.h"
|
| | 28 | +#include "thread.h"
|
| 29 | 29 |
|
| | 30 | +
|
| 30 | 31 | static const char welcomestring[] INITCONST_ATTR = "emBIOS v" VERSION "\n";
|
| 31 | 32 |
|
| | 33 | +uint32_t stack_a[0x400];
|
| | 34 | +uint32_t stack_b[0x400];
|
| | 35 | +
|
| | 36 | +
|
| | 37 | +void thread_a()
|
| | 38 | +{
|
| | 39 | + while(1) cprintf(1, "Hello from Thread A!\n");
|
| | 40 | +}
|
| | 41 | +
|
| | 42 | +void thread_b()
|
| | 43 | +{
|
| | 44 | + while(1) cprintf(1, "Hello from Thread B!\n");
|
| | 45 | +}
|
| | 46 | +
|
| 32 | 47 | #include "s5l8720.h"
|
| 33 | 48 |
|
| 34 | 49 | void init() INITCODE_ATTR;
|
| — | — | @@ -35,10 +50,8 @@ |
| 36 | 51 | {
|
| 37 | 52 | scheduler_init();
|
| 38 | 53 | lcdconsole_init();
|
| 39 | | - cputs(1, welcomestring);
|
| 40 | | - while(1)
|
| 41 | | - {
|
| 42 | | - cprintf(1, "TBCNT: %d \n", TBCNT);
|
| 43 | | - }
|
| | 54 | + interrupt_init();
|
| | 55 | + thread_create("Thread A", thread_a, stack_a, sizeof(stack_a), USER_THREAD, 127, true);
|
| | 56 | + thread_create("Thread B", thread_b, stack_b, sizeof(stack_b), USER_THREAD, 127, true);
|
| 44 | 57 |
|
| 45 | 58 | }
|
| Index: embios/branches/4g_compat/target/ipodnano4g/crt0.S |
| — | — | @@ -36,6 +36,8 @@ |
| 37 | 37 | .section .initcode,"ax",%progbits
|
| 38 | 38 | .global _start
|
| 39 | 39 | _start:
|
| | 40 | + ldr r0, =0x00450878
|
| | 41 | + mcr p15, 0, r0,c1,c0,0
|
| 40 | 42 | ldr r0, =_sramsource
|
| 41 | 43 | ldr r1, =_sramstart
|
| 42 | 44 | ldr r2, =_sramend
|
| — | — | @@ -78,6 +80,22 @@ |
| 79 | 81 | str r0, [r1]
|
| 80 | 82 | mov r0, #0
|
| 81 | 83 | mcr p15, 0, r0,c7,c5,0
|
| | 84 | + add r1, r1, #0x00c00000
|
| | 85 | + add r2, r1, #0x00001000
|
| | 86 | + add r3, r1, #0x00002000
|
| | 87 | + sub r4, r0, #1
|
| | 88 | + str r4, [r1,#0x14]
|
| | 89 | + str r4, [r2,#0x14]
|
| | 90 | + str r4, [r1,#0xf00]
|
| | 91 | + str r4, [r2,#0xf00]
|
| | 92 | + str r4, [r3,#0x08]
|
| | 93 | + str r4, [r3,#0x0c]
|
| | 94 | + str r0, [r1,#0x14]
|
| | 95 | + str r0, [r2,#0x14]
|
| | 96 | + mov r0, #0
|
| | 97 | + ldr r1, =0x3c500000
|
| | 98 | + str r0, [r1,#0x48]
|
| | 99 | + str r0, [r1,#0x4c]
|
| 82 | 100 | msr cpsr_c, #0xd2
|
| 83 | 101 | ldr sp, =_irqstackend
|
| 84 | 102 | msr cpsr_c, #0xd7
|
| — | — | @@ -84,7 +102,7 @@ |
| 85 | 103 | ldr sp, =_abortstackend
|
| 86 | 104 | msr cpsr_c, #0xdb
|
| 87 | 105 | ldr sp, =_abortstackend
|
| 88 | | - msr cpsr_c, #0xdf
|
| | 106 | + msr cpsr_c, #0x1f
|
| 89 | 107 | ldr sp, =_initstackend
|
| 90 | 108 | bl init
|
| 91 | 109 | bl context_switch
|
| — | — | @@ -181,14 +199,14 @@ |
| 182 | 200 |
|
| 183 | 201 | .section .icode.usec_timer, "ax", %progbits
|
| 184 | 202 | .align 2
|
| 185 | | -.global read_5usec_timer
|
| 186 | | -.type read_5usec_timer, %function
|
| 187 | | -read_5usec_timer:
|
| | 203 | +.global read_42nsec_timer
|
| | 204 | +.type read_42nsec_timer, %function
|
| | 205 | +read_42nsec_timer:
|
| 188 | 206 | ldr r0, val_3c700000
|
| 189 | 207 | ldr r1, [r0,#0x80]
|
| 190 | 208 | ldr r0, [r0,#0x84]
|
| 191 | 209 | bx lr
|
| 192 | | -.size read_5usec_timer, .-read_5usec_timer
|
| | 210 | +.size read_42nsec_timer, .-read_42nsec_timer
|
| 193 | 211 |
|
| 194 | 212 | .global read_usec_timer
|
| 195 | 213 | .type read_usec_timer, %function
|
| — | — | @@ -196,7 +214,10 @@ |
| 197 | 215 | ldr r0, val_3c700000
|
| 198 | 216 | ldr r1, [r0,#0x80]
|
| 199 | 217 | ldr r0, [r0,#0x84]
|
| 200 | | - add r0, r0, r0,lsl#2
|
| | 218 | + mov r0, r0,lsr#5
|
| | 219 | + orr r0, r0, r1,lsl#27
|
| | 220 | + add r0, r0, r0,asr#2
|
| | 221 | + add r0, r0, r0,asr#6
|
| 201 | 222 | bx lr
|
| 202 | 223 | .size read_usec_timer, .-read_usec_timer
|
| 203 | 224 |
|
| Index: embios/branches/4g_compat/target/ipodnano4g/s5l8720.h |
| — | — | @@ -293,8 +293,8 @@ |
| 294 | 294 | #define THDATA1 (*((volatile uint32_t*)(0x3C70010C)))
|
| 295 | 295 | #define THPRE (*((volatile uint32_t*)(0x3C700110)))
|
| 296 | 296 | #define THCNT (*((volatile uint32_t*)(0x3C700114)))
|
| 297 | | -uint64_t read_5usec_timer();
|
| 298 | | -#define FIVE_USEC_TIMER (read_5usec_timer()) /* 64bit 5usec timer */
|
| | 297 | +uint64_t read_42nsec_timer();
|
| | 298 | +#define FOURTYTWO_NSEC_TIMER (read_42nsec_timer()) /* 64bit 24MHz timer */
|
| 299 | 299 |
|
| 300 | 300 |
|
| 301 | 301 | /////USB/////
|
| — | — | @@ -310,11 +310,178 @@ |
| 311 | 311 |
|
| 312 | 312 |
|
| 313 | 313 | /////INTERRUPTS/////
|
| 314 | | -#define INTMSK_TIMER (1<<5)
|
| 315 | | -#define INTMSK_DMA (1<<10)
|
| 316 | | -#define INTMSK_USB_OTG (1<<16)
|
| 317 | | -#define INTMSK_ECC (1<<19)
|
| 318 | | -#define INTMSK_IIC (1<<27)
|
| | 314 | +#define VICIRQSTATUS(v) (*((volatile uint32_t*)(0x38E00000 + 0x1000 * v)))
|
| | 315 | +#define VICFIQSTATUS(v) (*((volatile uint32_t*)(0x38E00004 + 0x1000 * v)))
|
| | 316 | +#define VICRAWINTR(v) (*((volatile uint32_t*)(0x38E00008 + 0x1000 * v)))
|
| | 317 | +#define VICINTSELECT(v) (*((volatile uint32_t*)(0x38E0000C + 0x1000 * v)))
|
| | 318 | +#define VICINTENABLE(v) (*((volatile uint32_t*)(0x38E00010 + 0x1000 * v)))
|
| | 319 | +#define VICINTENCLEAR(v) (*((volatile uint32_t*)(0x38E00014 + 0x1000 * v)))
|
| | 320 | +#define VICSOFTINT(v) (*((volatile uint32_t*)(0x38E00018 + 0x1000 * v)))
|
| | 321 | +#define VICSOFTINTCLEAR(v) (*((volatile uint32_t*)(0x38E0001C + 0x1000 * v)))
|
| | 322 | +#define VICPROTECTION(v) (*((volatile uint32_t*)(0x38E00020 + 0x1000 * v)))
|
| | 323 | +#define VICSWPRIORITYMASK(v) (*((volatile uint32_t*)(0x38E00024 + 0x1000 * v)))
|
| | 324 | +#define VICPRIORITYDAISY(v) (*((volatile uint32_t*)(0x38E00028 + 0x1000 * v)))
|
| | 325 | +#define VICVECTADDR(v, i) (*((volatile uint32_t*)(0x38E00100 + 0x1000 * v + 4 * i)))
|
| | 326 | +#define VICVECTPRIORITY(v, i) (*((volatile uint32_t*)(0x38E00200 + 0x1000 * v + 4 * i)))
|
| | 327 | +#define VICADDRESS(v) (*((volatile uint32_t*)(0x38E00F00 + 0x1000 * v)))
|
| | 328 | +#define VIC0IRQSTATUS (*((volatile uint32_t*)(0x38E00000)))
|
| | 329 | +#define VIC0FIQSTATUS (*((volatile uint32_t*)(0x38E00004)))
|
| | 330 | +#define VIC0RAWINTR (*((volatile uint32_t*)(0x38E00008)))
|
| | 331 | +#define VIC0INTSELECT (*((volatile uint32_t*)(0x38E0000C)))
|
| | 332 | +#define VIC0INTENABLE (*((volatile uint32_t*)(0x38E00010)))
|
| | 333 | +#define VIC0INTENCLEAR (*((volatile uint32_t*)(0x38E00014)))
|
| | 334 | +#define VIC0SOFTINT (*((volatile uint32_t*)(0x38E00018)))
|
| | 335 | +#define VIC0SOFTINTCLEAR (*((volatile uint32_t*)(0x38E0001C)))
|
| | 336 | +#define VIC0PROTECTION (*((volatile uint32_t*)(0x38E00020)))
|
| | 337 | +#define VIC0SWPRIORITYMASK (*((volatile uint32_t*)(0x38E00024)))
|
| | 338 | +#define VIC0PRIORITYDAISY (*((volatile uint32_t*)(0x38E00028)))
|
| | 339 | +#define VIC0VECTADDR(i) (*((volatile uint32_t*)(0x38E00100 + 4 * i)))
|
| | 340 | +#define VIC0VECTADDR0 (*((volatile uint32_t*)(0x38E00100)))
|
| | 341 | +#define VIC0VECTADDR1 (*((volatile uint32_t*)(0x38E00104)))
|
| | 342 | +#define VIC0VECTADDR2 (*((volatile uint32_t*)(0x38E00108)))
|
| | 343 | +#define VIC0VECTADDR3 (*((volatile uint32_t*)(0x38E0010C)))
|
| | 344 | +#define VIC0VECTADDR4 (*((volatile uint32_t*)(0x38E00110)))
|
| | 345 | +#define VIC0VECTADDR5 (*((volatile uint32_t*)(0x38E00114)))
|
| | 346 | +#define VIC0VECTADDR6 (*((volatile uint32_t*)(0x38E00118)))
|
| | 347 | +#define VIC0VECTADDR7 (*((volatile uint32_t*)(0x38E0011C)))
|
| | 348 | +#define VIC0VECTADDR8 (*((volatile uint32_t*)(0x38E00120)))
|
| | 349 | +#define VIC0VECTADDR9 (*((volatile uint32_t*)(0x38E00124)))
|
| | 350 | +#define VIC0VECTADDR10 (*((volatile uint32_t*)(0x38E00128)))
|
| | 351 | +#define VIC0VECTADDR11 (*((volatile uint32_t*)(0x38E0012C)))
|
| | 352 | +#define VIC0VECTADDR12 (*((volatile uint32_t*)(0x38E00130)))
|
| | 353 | +#define VIC0VECTADDR13 (*((volatile uint32_t*)(0x38E00134)))
|
| | 354 | +#define VIC0VECTADDR14 (*((volatile uint32_t*)(0x38E00138)))
|
| | 355 | +#define VIC0VECTADDR15 (*((volatile uint32_t*)(0x38E0013C)))
|
| | 356 | +#define VIC0VECTADDR16 (*((volatile uint32_t*)(0x38E00140)))
|
| | 357 | +#define VIC0VECTADDR17 (*((volatile uint32_t*)(0x38E00144)))
|
| | 358 | +#define VIC0VECTADDR18 (*((volatile uint32_t*)(0x38E00148)))
|
| | 359 | +#define VIC0VECTADDR19 (*((volatile uint32_t*)(0x38E0014C)))
|
| | 360 | +#define VIC0VECTADDR20 (*((volatile uint32_t*)(0x38E00150)))
|
| | 361 | +#define VIC0VECTADDR21 (*((volatile uint32_t*)(0x38E00154)))
|
| | 362 | +#define VIC0VECTADDR22 (*((volatile uint32_t*)(0x38E00158)))
|
| | 363 | +#define VIC0VECTADDR23 (*((volatile uint32_t*)(0x38E0015C)))
|
| | 364 | +#define VIC0VECTADDR24 (*((volatile uint32_t*)(0x38E00160)))
|
| | 365 | +#define VIC0VECTADDR25 (*((volatile uint32_t*)(0x38E00164)))
|
| | 366 | +#define VIC0VECTADDR26 (*((volatile uint32_t*)(0x38E00168)))
|
| | 367 | +#define VIC0VECTADDR27 (*((volatile uint32_t*)(0x38E0016C)))
|
| | 368 | +#define VIC0VECTADDR28 (*((volatile uint32_t*)(0x38E00170)))
|
| | 369 | +#define VIC0VECTADDR29 (*((volatile uint32_t*)(0x38E00174)))
|
| | 370 | +#define VIC0VECTADDR30 (*((volatile uint32_t*)(0x38E00178)))
|
| | 371 | +#define VIC0VECTADDR31 (*((volatile uint32_t*)(0x38E0017C)))
|
| | 372 | +#define VIC0VECTPRIORITY(i) (*((volatile uint32_t*)(0x38E00200 + 4 * i)))
|
| | 373 | +#define VIC0VECTPRIORITY0 (*((volatile uint32_t*)(0x38E00200)))
|
| | 374 | +#define VIC0VECTPRIORITY1 (*((volatile uint32_t*)(0x38E00204)))
|
| | 375 | +#define VIC0VECTPRIORITY2 (*((volatile uint32_t*)(0x38E00208)))
|
| | 376 | +#define VIC0VECTPRIORITY3 (*((volatile uint32_t*)(0x38E0020C)))
|
| | 377 | +#define VIC0VECTPRIORITY4 (*((volatile uint32_t*)(0x38E00210)))
|
| | 378 | +#define VIC0VECTPRIORITY5 (*((volatile uint32_t*)(0x38E00214)))
|
| | 379 | +#define VIC0VECTPRIORITY6 (*((volatile uint32_t*)(0x38E00218)))
|
| | 380 | +#define VIC0VECTPRIORITY7 (*((volatile uint32_t*)(0x38E0021C)))
|
| | 381 | +#define VIC0VECTPRIORITY8 (*((volatile uint32_t*)(0x38E00220)))
|
| | 382 | +#define VIC0VECTPRIORITY9 (*((volatile uint32_t*)(0x38E00224)))
|
| | 383 | +#define VIC0VECTPRIORITY10 (*((volatile uint32_t*)(0x38E00228)))
|
| | 384 | +#define VIC0VECTPRIORITY11 (*((volatile uint32_t*)(0x38E0022C)))
|
| | 385 | +#define VIC0VECTPRIORITY12 (*((volatile uint32_t*)(0x38E00230)))
|
| | 386 | +#define VIC0VECTPRIORITY13 (*((volatile uint32_t*)(0x38E00234)))
|
| | 387 | +#define VIC0VECTPRIORITY14 (*((volatile uint32_t*)(0x38E00238)))
|
| | 388 | +#define VIC0VECTPRIORITY15 (*((volatile uint32_t*)(0x38E0023C)))
|
| | 389 | +#define VIC0VECTPRIORITY16 (*((volatile uint32_t*)(0x38E00240)))
|
| | 390 | +#define VIC0VECTPRIORITY17 (*((volatile uint32_t*)(0x38E00244)))
|
| | 391 | +#define VIC0VECTPRIORITY18 (*((volatile uint32_t*)(0x38E00248)))
|
| | 392 | +#define VIC0VECTPRIORITY19 (*((volatile uint32_t*)(0x38E0024C)))
|
| | 393 | +#define VIC0VECTPRIORITY20 (*((volatile uint32_t*)(0x38E00250)))
|
| | 394 | +#define VIC0VECTPRIORITY21 (*((volatile uint32_t*)(0x38E00254)))
|
| | 395 | +#define VIC0VECTPRIORITY22 (*((volatile uint32_t*)(0x38E00258)))
|
| | 396 | +#define VIC0VECTPRIORITY23 (*((volatile uint32_t*)(0x38E0025C)))
|
| | 397 | +#define VIC0VECTPRIORITY24 (*((volatile uint32_t*)(0x38E00260)))
|
| | 398 | +#define VIC0VECTPRIORITY25 (*((volatile uint32_t*)(0x38E00264)))
|
| | 399 | +#define VIC0VECTPRIORITY26 (*((volatile uint32_t*)(0x38E00268)))
|
| | 400 | +#define VIC0VECTPRIORITY27 (*((volatile uint32_t*)(0x38E0026C)))
|
| | 401 | +#define VIC0VECTPRIORITY28 (*((volatile uint32_t*)(0x38E00270)))
|
| | 402 | +#define VIC0VECTPRIORITY29 (*((volatile uint32_t*)(0x38E00274)))
|
| | 403 | +#define VIC0VECTPRIORITY30 (*((volatile uint32_t*)(0x38E00278)))
|
| | 404 | +#define VIC0VECTPRIORITY31 (*((volatile uint32_t*)(0x38E0027C)))
|
| | 405 | +#define VIC0ADDRESS (*((volatile uint32_t*)(0x38E00F00)))
|
| | 406 | +#define VIC1IRQSTATUS (*((volatile uint32_t*)(0x38E01000)))
|
| | 407 | +#define VIC1FIQSTATUS (*((volatile uint32_t*)(0x38E01004)))
|
| | 408 | +#define VIC1RAWINTR (*((volatile uint32_t*)(0x38E01008)))
|
| | 409 | +#define VIC1INTSELECT (*((volatile uint32_t*)(0x38E0100C)))
|
| | 410 | +#define VIC1INTENABLE (*((volatile uint32_t*)(0x38E01010)))
|
| | 411 | +#define VIC1INTENCLEAR (*((volatile uint32_t*)(0x38E01014)))
|
| | 412 | +#define VIC1SOFTINT (*((volatile uint32_t*)(0x38E01018)))
|
| | 413 | +#define VIC1SOFTINTCLEAR (*((volatile uint32_t*)(0x38E0101C)))
|
| | 414 | +#define VIC1PROTECTION (*((volatile uint32_t*)(0x38E01020)))
|
| | 415 | +#define VIC1SWPRIORITYMASK (*((volatile uint32_t*)(0x38E01024)))
|
| | 416 | +#define VIC1PRIORITYDAISY (*((volatile uint32_t*)(0x38E01028)))
|
| | 417 | +#define VIC1VECTADDR(i) (*((volatile uint32_t*)(0x38E01100 + 4 * i)))
|
| | 418 | +#define VIC1VECTADDR0 (*((volatile uint32_t*)(0x38E01100)))
|
| | 419 | +#define VIC1VECTADDR1 (*((volatile uint32_t*)(0x38E01104)))
|
| | 420 | +#define VIC1VECTADDR2 (*((volatile uint32_t*)(0x38E01108)))
|
| | 421 | +#define VIC1VECTADDR3 (*((volatile uint32_t*)(0x38E0110C)))
|
| | 422 | +#define VIC1VECTADDR4 (*((volatile uint32_t*)(0x38E01110)))
|
| | 423 | +#define VIC1VECTADDR5 (*((volatile uint32_t*)(0x38E01114)))
|
| | 424 | +#define VIC1VECTADDR6 (*((volatile uint32_t*)(0x38E01118)))
|
| | 425 | +#define VIC1VECTADDR7 (*((volatile uint32_t*)(0x38E0111C)))
|
| | 426 | +#define VIC1VECTADDR8 (*((volatile uint32_t*)(0x38E01120)))
|
| | 427 | +#define VIC1VECTADDR9 (*((volatile uint32_t*)(0x38E01124)))
|
| | 428 | +#define VIC1VECTADDR10 (*((volatile uint32_t*)(0x38E01128)))
|
| | 429 | +#define VIC1VECTADDR11 (*((volatile uint32_t*)(0x38E0112C)))
|
| | 430 | +#define VIC1VECTADDR12 (*((volatile uint32_t*)(0x38E01130)))
|
| | 431 | +#define VIC1VECTADDR13 (*((volatile uint32_t*)(0x38E01134)))
|
| | 432 | +#define VIC1VECTADDR14 (*((volatile uint32_t*)(0x38E01138)))
|
| | 433 | +#define VIC1VECTADDR15 (*((volatile uint32_t*)(0x38E0113C)))
|
| | 434 | +#define VIC1VECTADDR16 (*((volatile uint32_t*)(0x38E01140)))
|
| | 435 | +#define VIC1VECTADDR17 (*((volatile uint32_t*)(0x38E01144)))
|
| | 436 | +#define VIC1VECTADDR18 (*((volatile uint32_t*)(0x38E01148)))
|
| | 437 | +#define VIC1VECTADDR19 (*((volatile uint32_t*)(0x38E0114C)))
|
| | 438 | +#define VIC1VECTADDR20 (*((volatile uint32_t*)(0x38E01150)))
|
| | 439 | +#define VIC1VECTADDR21 (*((volatile uint32_t*)(0x38E01154)))
|
| | 440 | +#define VIC1VECTADDR22 (*((volatile uint32_t*)(0x38E01158)))
|
| | 441 | +#define VIC1VECTADDR23 (*((volatile uint32_t*)(0x38E0115C)))
|
| | 442 | +#define VIC1VECTADDR24 (*((volatile uint32_t*)(0x38E01160)))
|
| | 443 | +#define VIC1VECTADDR25 (*((volatile uint32_t*)(0x38E01164)))
|
| | 444 | +#define VIC1VECTADDR26 (*((volatile uint32_t*)(0x38E01168)))
|
| | 445 | +#define VIC1VECTADDR27 (*((volatile uint32_t*)(0x38E0116C)))
|
| | 446 | +#define VIC1VECTADDR28 (*((volatile uint32_t*)(0x38E01170)))
|
| | 447 | +#define VIC1VECTADDR29 (*((volatile uint32_t*)(0x38E01174)))
|
| | 448 | +#define VIC1VECTADDR30 (*((volatile uint32_t*)(0x38E01178)))
|
| | 449 | +#define VIC1VECTADDR31 (*((volatile uint32_t*)(0x38E0117C)))
|
| | 450 | +#define VIC1VECTPRIORITY(i) (*((volatile uint32_t*)(0x38E01200 + 4 * i)))
|
| | 451 | +#define VIC1VECTPRIORITY0 (*((volatile uint32_t*)(0x38E01200)))
|
| | 452 | +#define VIC1VECTPRIORITY1 (*((volatile uint32_t*)(0x38E01204)))
|
| | 453 | +#define VIC1VECTPRIORITY2 (*((volatile uint32_t*)(0x38E01208)))
|
| | 454 | +#define VIC1VECTPRIORITY3 (*((volatile uint32_t*)(0x38E0120C)))
|
| | 455 | +#define VIC1VECTPRIORITY4 (*((volatile uint32_t*)(0x38E01210)))
|
| | 456 | +#define VIC1VECTPRIORITY5 (*((volatile uint32_t*)(0x38E01214)))
|
| | 457 | +#define VIC1VECTPRIORITY6 (*((volatile uint32_t*)(0x38E01218)))
|
| | 458 | +#define VIC1VECTPRIORITY7 (*((volatile uint32_t*)(0x38E0121C)))
|
| | 459 | +#define VIC1VECTPRIORITY8 (*((volatile uint32_t*)(0x38E01220)))
|
| | 460 | +#define VIC1VECTPRIORITY9 (*((volatile uint32_t*)(0x38E01224)))
|
| | 461 | +#define VIC1VECTPRIORITY10 (*((volatile uint32_t*)(0x38E01228)))
|
| | 462 | +#define VIC1VECTPRIORITY11 (*((volatile uint32_t*)(0x38E0122C)))
|
| | 463 | +#define VIC1VECTPRIORITY12 (*((volatile uint32_t*)(0x38E01230)))
|
| | 464 | +#define VIC1VECTPRIORITY13 (*((volatile uint32_t*)(0x38E01234)))
|
| | 465 | +#define VIC1VECTPRIORITY14 (*((volatile uint32_t*)(0x38E01238)))
|
| | 466 | +#define VIC1VECTPRIORITY15 (*((volatile uint32_t*)(0x38E0123C)))
|
| | 467 | +#define VIC1VECTPRIORITY16 (*((volatile uint32_t*)(0x38E01240)))
|
| | 468 | +#define VIC1VECTPRIORITY17 (*((volatile uint32_t*)(0x38E01244)))
|
| | 469 | +#define VIC1VECTPRIORITY18 (*((volatile uint32_t*)(0x38E01248)))
|
| | 470 | +#define VIC1VECTPRIORITY19 (*((volatile uint32_t*)(0x38E0124C)))
|
| | 471 | +#define VIC1VECTPRIORITY20 (*((volatile uint32_t*)(0x38E01250)))
|
| | 472 | +#define VIC1VECTPRIORITY21 (*((volatile uint32_t*)(0x38E01254)))
|
| | 473 | +#define VIC1VECTPRIORITY22 (*((volatile uint32_t*)(0x38E01258)))
|
| | 474 | +#define VIC1VECTPRIORITY23 (*((volatile uint32_t*)(0x38E0125C)))
|
| | 475 | +#define VIC1VECTPRIORITY24 (*((volatile uint32_t*)(0x38E01260)))
|
| | 476 | +#define VIC1VECTPRIORITY25 (*((volatile uint32_t*)(0x38E01264)))
|
| | 477 | +#define VIC1VECTPRIORITY26 (*((volatile uint32_t*)(0x38E01268)))
|
| | 478 | +#define VIC1VECTPRIORITY27 (*((volatile uint32_t*)(0x38E0126C)))
|
| | 479 | +#define VIC1VECTPRIORITY28 (*((volatile uint32_t*)(0x38E01270)))
|
| | 480 | +#define VIC1VECTPRIORITY29 (*((volatile uint32_t*)(0x38E01274)))
|
| | 481 | +#define VIC1VECTPRIORITY30 (*((volatile uint32_t*)(0x38E01278)))
|
| | 482 | +#define VIC1VECTPRIORITY31 (*((volatile uint32_t*)(0x38E0127C)))
|
| | 483 | +#define VIC1ADDRESS (*((volatile uint32_t*)(0x38E01F00)))
|
| | 484 | +#define INTMSK_TIMER (1<<8)
|
| | 485 | +#define INTMSK_USB_OTG (1<<23)
|
| 319 | 486 |
|
| 320 | 487 |
|
| 321 | 488 | #endif
|
| Index: embios/branches/4g_compat/target/ipodnano4g/interrupt.c |
| — | — | @@ -28,12 +28,14 @@ |
| 29 | 29 |
|
| 30 | 30 | #define default_interrupt(name) extern __attribute__((weak,alias("unhandled_irq"))) void name(void)
|
| 31 | 31 |
|
| 32 | | -default_interrupt(EXT0);
|
| 33 | | -default_interrupt(EXT1);
|
| 34 | | -default_interrupt(EXT2);
|
| 35 | | -default_interrupt(EINT_VBUS);
|
| 36 | | -default_interrupt(EINTG);
|
| 37 | | -default_interrupt(INT_WDT);
|
| | 32 | +default_interrupt(INT_IRQ0);
|
| | 33 | +default_interrupt(INT_IRQ1);
|
| | 34 | +default_interrupt(INT_IRQ2);
|
| | 35 | +default_interrupt(INT_IRQ3);
|
| | 36 | +default_interrupt(INT_IRQ4);
|
| | 37 | +default_interrupt(INT_IRQ5);
|
| | 38 | +default_interrupt(INT_IRQ6);
|
| | 39 | +default_interrupt(INT_IRQ7);
|
| 38 | 40 | default_interrupt(INT_TIMERA);
|
| 39 | 41 | default_interrupt(INT_TIMERB);
|
| 40 | 42 | default_interrupt(INT_TIMERC);
|
| — | — | @@ -42,44 +44,69 @@ |
| 43 | 45 | default_interrupt(INT_TIMERF);
|
| 44 | 46 | default_interrupt(INT_TIMERG);
|
| 45 | 47 | default_interrupt(INT_TIMERH);
|
| 46 | | -default_interrupt(INT_DMA0);
|
| 47 | | -default_interrupt(INT_DMA1);
|
| 48 | | -default_interrupt(INT_DMA2);
|
| 49 | | -default_interrupt(INT_DMA3);
|
| 50 | | -default_interrupt(INT_DMA4);
|
| 51 | | -default_interrupt(INT_DMA5);
|
| 52 | | -default_interrupt(INT_DMA6);
|
| 53 | | -default_interrupt(INT_DMA7);
|
| 54 | | -default_interrupt(INT_DMA8);
|
| 55 | | -default_interrupt(INT_ALARM_RTC);
|
| 56 | | -default_interrupt(INT_PRI_RTC);
|
| 57 | | -default_interrupt(RESERVED1);
|
| 58 | | -default_interrupt(INT_UART);
|
| 59 | | -default_interrupt(INT_USB_HOST);
|
| | 48 | +default_interrupt(INT_IRQ9);
|
| | 49 | +default_interrupt(INT_IRQ10);
|
| | 50 | +default_interrupt(INT_IRQ11);
|
| | 51 | +default_interrupt(INT_IRQ12);
|
| | 52 | +default_interrupt(INT_IRQ13);
|
| | 53 | +default_interrupt(INT_IRQ14);
|
| | 54 | +default_interrupt(INT_IRQ15);
|
| | 55 | +default_interrupt(INT_IRQ16);
|
| | 56 | +default_interrupt(INT_IRQ17);
|
| | 57 | +default_interrupt(INT_IRQ18);
|
| | 58 | +default_interrupt(INT_IRQ19);
|
| | 59 | +default_interrupt(INT_IRQ20);
|
| | 60 | +default_interrupt(INT_IRQ21);
|
| | 61 | +default_interrupt(INT_IRQ22);
|
| 60 | 62 | default_interrupt(INT_USB_FUNC);
|
| 61 | | -default_interrupt(INT_LCDC_0);
|
| 62 | | -default_interrupt(INT_LCDC_1);
|
| 63 | | -default_interrupt(INT_ECC);
|
| 64 | | -default_interrupt(INT_CALM);
|
| 65 | | -default_interrupt(INT_ATA);
|
| 66 | | -default_interrupt(INT_UART0);
|
| 67 | | -default_interrupt(INT_SPDIF_OUT);
|
| 68 | | -default_interrupt(INT_SDCI);
|
| 69 | | -default_interrupt(INT_LCD);
|
| 70 | | -default_interrupt(INT_SPI);
|
| 71 | | -default_interrupt(INT_IIC);
|
| 72 | | -default_interrupt(RESERVED2);
|
| 73 | | -default_interrupt(INT_MSTICK);
|
| 74 | | -default_interrupt(INT_ADC_WAKEUP);
|
| 75 | | -default_interrupt(INT_ADC);
|
| 76 | | -default_interrupt(INT_UNK1);
|
| 77 | | -default_interrupt(INT_UNK2);
|
| 78 | | -default_interrupt(INT_UNK3);
|
| | 63 | +default_interrupt(INT_IRQ24);
|
| | 64 | +default_interrupt(INT_IRQ25);
|
| | 65 | +default_interrupt(INT_IRQ26);
|
| | 66 | +default_interrupt(INT_IRQ27);
|
| | 67 | +default_interrupt(INT_IRQ28);
|
| | 68 | +default_interrupt(INT_IRQ29);
|
| | 69 | +default_interrupt(INT_IRQ30);
|
| | 70 | +default_interrupt(INT_IRQ31);
|
| | 71 | +default_interrupt(INT_IRQ32);
|
| | 72 | +default_interrupt(INT_IRQ33);
|
| | 73 | +default_interrupt(INT_IRQ34);
|
| | 74 | +default_interrupt(INT_IRQ35);
|
| | 75 | +default_interrupt(INT_IRQ36);
|
| | 76 | +default_interrupt(INT_IRQ37);
|
| | 77 | +default_interrupt(INT_IRQ38);
|
| | 78 | +default_interrupt(INT_IRQ39);
|
| | 79 | +default_interrupt(INT_IRQ40);
|
| | 80 | +default_interrupt(INT_IRQ41);
|
| | 81 | +default_interrupt(INT_IRQ42);
|
| | 82 | +default_interrupt(INT_IRQ43);
|
| | 83 | +default_interrupt(INT_IRQ44);
|
| | 84 | +default_interrupt(INT_IRQ45);
|
| | 85 | +default_interrupt(INT_IRQ46);
|
| | 86 | +default_interrupt(INT_IRQ47);
|
| | 87 | +default_interrupt(INT_IRQ48);
|
| | 88 | +default_interrupt(INT_IRQ49);
|
| | 89 | +default_interrupt(INT_IRQ50);
|
| | 90 | +default_interrupt(INT_IRQ51);
|
| | 91 | +default_interrupt(INT_IRQ52);
|
| | 92 | +default_interrupt(INT_IRQ53);
|
| | 93 | +default_interrupt(INT_IRQ54);
|
| | 94 | +default_interrupt(INT_IRQ55);
|
| | 95 | +default_interrupt(INT_IRQ56);
|
| | 96 | +default_interrupt(INT_IRQ57);
|
| | 97 | +default_interrupt(INT_IRQ58);
|
| | 98 | +default_interrupt(INT_IRQ59);
|
| | 99 | +default_interrupt(INT_IRQ60);
|
| | 100 | +default_interrupt(INT_IRQ61);
|
| | 101 | +default_interrupt(INT_IRQ62);
|
| | 102 | +default_interrupt(INT_IRQ63);
|
| 79 | 103 |
|
| 80 | 104 |
|
| | 105 | +static int current_irq;
|
| | 106 | +
|
| | 107 | +
|
| 81 | 108 | void unhandled_irq(void)
|
| 82 | 109 | {
|
| 83 | | - panicf(PANIC_FATAL, "Unhandled IRQ %d!", INTOFFSET);
|
| | 110 | + panicf(PANIC_FATAL, "Unhandled IRQ %d!", current_irq);
|
| 84 | 111 | }
|
| 85 | 112 |
|
| 86 | 113 | static void (* const timervector[])(void) IDATA_ATTR =
|
| — | — | @@ -100,44 +127,35 @@ |
| 101 | 128 | if (THCON & 0x00038000) timervector[7]();
|
| 102 | 129 | }
|
| 103 | 130 |
|
| 104 | | -static void (* const dmavector[])(void) IDATA_ATTR =
|
| 105 | | -{
|
| 106 | | - INT_DMA0,INT_DMA1,INT_DMA2,INT_DMA3,INT_DMA4,INT_DMA5,INT_DMA6,INT_DMA7,INT_DMA8
|
| 107 | | -};
|
| 108 | | -
|
| 109 | | -void INT_DMA(void) ICODE_ATTR;
|
| 110 | | -void INT_DMA()
|
| 111 | | -{
|
| 112 | | - uint32_t dmaallst = DMAALLST;
|
| 113 | | - uint32_t dmaallst2 = DMAALLST2;
|
| 114 | | - if (dmaallst & (DMACON0 >> 16) & 3) dmavector[0]();
|
| 115 | | - if (dmaallst & (DMACON1 >> 12) & 0x30) dmavector[1]();
|
| 116 | | - if (dmaallst & (DMACON2 >> 8) & 0x300) dmavector[2]();
|
| 117 | | - if (dmaallst & (DMACON3 >> 4) & 0x3000) dmavector[3]();
|
| 118 | | - if (dmaallst2 & (DMACON4 >> 16) & 3) dmavector[4]();
|
| 119 | | - if (dmaallst2 & (DMACON5 >> 12) & 0x30) dmavector[5]();
|
| 120 | | - if (dmaallst2 & (DMACON6 >> 8) & 0x300) dmavector[6]();
|
| 121 | | - if (dmaallst2 & (DMACON7 >> 4) & 0x3000) dmavector[7]();
|
| 122 | | - if (dmaallst2 & DMACON8 & 0x30000) dmavector[8]();
|
| 123 | | -}
|
| 124 | | -
|
| 125 | 131 | static void (* const irqvector[])(void) IDATA_ATTR =
|
| 126 | 132 | {
|
| 127 | | - EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMER,INT_WDT,INT_UNK1,
|
| 128 | | - INT_UNK2,INT_UNK3,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST,
|
| 129 | | - INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,INT_ECC,
|
| 130 | | - INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC
|
| | 133 | + INT_IRQ0,INT_IRQ1,INT_IRQ2,INT_IRQ3,INT_IRQ4,INT_IRQ5,INT_IRQ6,INT_IRQ7,
|
| | 134 | + INT_TIMER,INT_IRQ9,INT_IRQ10,INT_IRQ11,INT_IRQ12,INT_IRQ13,INT_IRQ14,INT_IRQ15,
|
| | 135 | + INT_IRQ16,INT_IRQ17,INT_IRQ18,INT_IRQ19,INT_IRQ20,INT_IRQ21,INT_IRQ22,INT_USB_FUNC,
|
| | 136 | + INT_IRQ24,INT_IRQ25,INT_IRQ26,INT_IRQ27,INT_IRQ28,INT_IRQ29,INT_IRQ30,INT_IRQ31,
|
| | 137 | + INT_IRQ32,INT_IRQ33,INT_IRQ34,INT_IRQ35,INT_IRQ36,INT_IRQ37,INT_IRQ38,INT_IRQ39,
|
| | 138 | + INT_IRQ40,INT_IRQ41,INT_IRQ42,INT_IRQ43,INT_IRQ55,INT_IRQ56,INT_IRQ57,INT_IRQ58,
|
| | 139 | + INT_IRQ48,INT_IRQ49,INT_IRQ50,INT_IRQ51,INT_IRQ52,INT_IRQ53,INT_IRQ54,INT_IRQ55,
|
| | 140 | + INT_IRQ56,INT_IRQ57,INT_IRQ58,INT_IRQ59,INT_IRQ60,INT_IRQ61,INT_IRQ62,INT_IRQ63
|
| 131 | 141 | };
|
| 132 | 142 |
|
| 133 | 143 | void irqhandler(void)
|
| 134 | 144 | {
|
| 135 | | - int irq_no = INTOFFSET;
|
| 136 | | - irqvector[irq_no]();
|
| 137 | | - SRCPND = (1 << irq_no);
|
| 138 | | - INTPND = INTPND;
|
| | 145 | + uint32_t dummy = VIC0ADDRESS;
|
| | 146 | + dummy = VIC1ADDRESS;
|
| | 147 | + uint32_t irqs0 = VIC0IRQSTATUS;
|
| | 148 | + uint32_t irqs1 = VIC1IRQSTATUS;
|
| | 149 | + for (current_irq = 0; irqs0; current_irq++, irqs0 >>= 1)
|
| | 150 | + if (irqs0 & 1)
|
| | 151 | + irqvector[current_irq]();
|
| | 152 | + for (current_irq = 32; irqs1; current_irq++, irqs1 >>= 1)
|
| | 153 | + if (irqs1 & 1)
|
| | 154 | + irqvector[current_irq]();
|
| | 155 | + VIC0ADDRESS = 0;
|
| | 156 | + VIC1ADDRESS = 0;
|
| 139 | 157 | }
|
| 140 | 158 |
|
| 141 | 159 | void interrupt_init(void)
|
| 142 | 160 | {
|
| 143 | | - INTMSK = INTMSK_TIMER | INTMSK_DMA;
|
| | 161 | + VIC0INTENABLE = INTMSK_TIMER;
|
| 144 | 162 | }
|
