| Index: apps/installer-ipodnano4g/bootstub/bootstub.S |
| — | — | @@ -24,7 +24,6 @@ |
| 25 | 25 |
|
| 26 | 26 | .global _start
|
| 27 | 27 | _start:
|
| 28 | | -
|
| 29 | 28 | msr cpsr_c, #0xd3
|
| 30 | 29 | mrc p15, 0, r0,c1,c0
|
| 31 | 30 | bic r0, r0, #1
|
| — | — | @@ -31,25 +30,27 @@ |
| 32 | 31 | mcr p15, 0, r0,c1,c0 @ disable mmu
|
| 33 | 32 |
|
| 34 | 33 | mov lr, #0
|
| 35 | | - adr sp, values1
|
| 36 | 34 | mcr p15, 0, lr,c7,c14,0 @ clean & invalidate data cache
|
| 37 | 35 | mcr p15, 0, lr,c7,c10,4 @ drain write buffer
|
| 38 | 36 | mcr p15, 0, lr,c7,c5 @ invalidate instruction cache
|
| | 37 | + mcr p15, 0, lr,c7,c5,4 @ flush prefetch buffer
|
| 39 | 38 | mcr p15, 0, lr,c8,c7 @ invalidate all unlocked entries in the TLB
|
| 40 | 39 | mcr p15, 0, lr,c13,c0,0 @ disable context id register
|
| 41 | 40 |
|
| 42 | | -.macro block0_constpool @ Block 0 (MMU, DMA) register map:
|
| | 41 | + adr sp, values1
|
| | 42 | +
|
| | 43 | +.macro block0_constpool @ Block 0 (MMU) register map:
|
| 43 | 44 | @ R0: Unused
|
| 44 | 45 | @ R1: Unused
|
| 45 | 46 | @ R2: Unused
|
| 46 | 47 | @ R3: Scratchpad
|
| 47 | | - @ R4: Unused
|
| 48 | | - @ R5: Unused
|
| 49 | | - @ R6: Unused
|
| 50 | | - @ R7: Unused
|
| 51 | | - @ R8: Unused
|
| 52 | | - @ R9: Unused
|
| 53 | | - .word 0x0005107D @ R10: CP15r1
|
| | 48 | + @ R4: Unused
|
| | 49 | + @ R5: Unused
|
| | 50 | + @ R6: Unused
|
| | 51 | + @ R7: Unused
|
| | 52 | + @ R8: Unused
|
| | 53 | + @ R9: Unused
|
| | 54 | + .word 0x0005187D @ R10: CP15r1
|
| 54 | 55 | .word 0x2202C000 @ R11: First level page table
|
| 55 | 56 | .word 0x00000C1E @ R12: Default segment flags
|
| 56 | 57 | @ R13: Constant pool pointer
|
| — | — | @@ -59,6 +60,9 @@ |
| 60 | 61 | mcr p15, 0, r11,c2,c0 @ set first level translation table
|
| 61 | 62 | mov r3, #-1
|
| 62 | 63 | mcr p15, 0, r3,c3,c0 @ disable domain access control @ R3: Unused
|
| | 64 | + orr r0, r12, #0x22000000
|
| | 65 | + str r0, [r11], #4
|
| | 66 | + add r12, r12, #0x00100000
|
| 63 | 67 | mmuloop:
|
| 64 | 68 | str r12, [r11], #4
|
| 65 | 69 | add r12, r12, #0x00100000
|
| — | — | @@ -66,11 +70,12 @@ |
| 67 | 71 | biccs r12, r12, #0xc
|
| 68 | 72 | tst r12, #0x40000000
|
| 69 | 73 | beq mmuloop
|
| 70 | | - @ R11: Unused
|
| 71 | | - @ R12: Unused
|
| | 74 | + @ R11: Unused
|
| | 75 | + @ R12: Unused
|
| 72 | 76 | mcr p15, 0, r10,c1,c0 @ R10: Unused
|
| 73 | 77 |
|
| 74 | | -.macro block1_constpool @ Block 1 (SYSCON) register map:
|
| | 78 | +
|
| | 79 | +.macro block1_constpool @ Block 1 (SYSCON) register map:
|
| 75 | 80 | .word 0x000327E5 @ R0: PWRCON(0)
|
| 76 | 81 | .word 0xFE2BED6D @ R1: PWRCON(1)
|
| 77 | 82 | .word 0x00DCF779 @ R2: PWRCON(4)
|
| — | — | @@ -88,7 +93,7 @@ |
| 89 | 94 | .endm @ R14: 0
|
| 90 | 95 |
|
| 91 | 96 | ldmia sp!, {r0-r12}
|
| 92 | | - str r0, [r12,#0x48] @ PWRCON0 ... @ R0: Scratchpad
|
| | 97 | + str r0, [r12,#0x48] @ PWRCON0 ... @ R0: Scratchpad
|
| 93 | 98 | str r1, [r12,#0x4c]
|
| 94 | 99 | mov r0, #0x73
|
| 95 | 100 | str r0, [r12,#0x58]
|
| — | — | @@ -111,7 +116,7 @@ |
| 112 | 117 | str r0, [r12,#0x44]
|
| 113 | 118 | str lr, [r12,#0x44]
|
| 114 | 119 | str lr, [r12,#0x3c]
|
| 115 | | - str r4, [r12,#0x20] @ R4: Scratchpad
|
| | 120 | + str r4, [r12,#0x20] @ R4: Scratchpad
|
| 116 | 121 | str r5, [r12,#0x30]
|
| 117 | 122 | mov r5, #1 @ R5: 1
|
| 118 | 123 | str r5, [r12,#0x44]
|
| — | — | @@ -122,14 +127,14 @@ |
| 123 | 128 | tst r4, #0x1
|
| 124 | 129 | beq sysconwait3 @ while (!([SYSCON+0x40] & 1))
|
| 125 | 130 |
|
| 126 | | - str r6, [r12,#0x04] @ R6: Unused
|
| | 131 | + str r6, [r12,#0x04] @ R6: Unused
|
| 127 | 132 | add r3, r3, #0x3e @ R3: 0x003E3E3E
|
| 128 | 133 | sysconwait4:
|
| 129 | 134 | ldr r4, [r12,#0x04]
|
| 130 | | - tst r4, r3 @ R3: Unused
|
| | 135 | + tst r4, r3 @ R3: Unused
|
| 131 | 136 | bne sysconwait4
|
| 132 | 137 |
|
| 133 | | - str r7, [r12] @ R7: Unused
|
| | 138 | + str r7, [r12] @ R7: Unused
|
| 134 | 139 | sysconwait5:
|
| 135 | 140 | ldr r2, [r12]
|
| 136 | 141 | tst r4, #0xf
|
| — | — | @@ -136,7 +141,7 @@ |
| 137 | 142 | bne sysconwait5
|
| 138 | 143 |
|
| 139 | 144 | str r8, [r12,#0x08]
|
| 140 | | - orr r4, r8, r8,lsr#1 @ R8: Unused
|
| | 145 | + orr r4, r8, r8,lsr#1 @ R8: Unused
|
| 141 | 146 | str r4, [r12,#0x0c]
|
| 142 | 147 | mov r4, #0xc000
|
| 143 | 148 | str r4, [r12,#0x10]
|
| — | — | @@ -147,26 +152,26 @@ |
| 148 | 153 | str r4, [r9] @ R9: Unused
|
| 149 | 154 | mov r0, #0x10 @ R5: 0x10
|
| 150 | 155 |
|
| 151 | | - @ Block 2 (TIMER) register map:
|
| 152 | | - @ R0: 1
|
| 153 | | - @ R1: PWRCON(1)
|
| 154 | | - @ R2: PWRCON(4)
|
| 155 | | - @ R3: Scratchpad
|
| 156 | | - @ R4: Scratchpad
|
| 157 | | - @ R5: 0x10
|
| 158 | | - @ R6: Unused
|
| 159 | | - @ R7: Unused
|
| 160 | | - @ R8: Unused
|
| 161 | | - @ R9: Unused
|
| 162 | | - @ R10: PWRCON(1) during timer setup
|
| 163 | | - @ R11: PWRCON(4) during timer setup
|
| 164 | | - @ R12: SYSCON base address
|
| | 156 | + @ Block 2 (TIMER) register map:
|
| | 157 | + @ R0: 1
|
| | 158 | + @ R1: PWRCON(1)
|
| | 159 | + @ R2: PWRCON(4)
|
| | 160 | + @ R3: Scratchpad
|
| | 161 | + @ R4: Scratchpad
|
| | 162 | + @ R5: 0x10
|
| | 163 | + @ R6: Unused
|
| | 164 | + @ R7: Unused
|
| | 165 | + @ R8: Unused
|
| | 166 | + @ R9: Unused
|
| | 167 | + @ R10: PWRCON(1) during timer setup
|
| | 168 | + @ R11: PWRCON(4) during timer setup
|
| | 169 | + @ R12: SYSCON base address
|
| 165 | 170 | @ R13: Constant pool pointer
|
| 166 | 171 | @ R14: 0
|
| 167 | 172 |
|
| 168 | 173 | str r10, [r12,#0x4c] @ PWRCON(1) for timer setup @ R10: Unused
|
| 169 | 174 | mov r4, #0x13
|
| 170 | | - str r4, [r12,#0x58] @ PWRCON(2) for timer setup
|
| | 175 | + str r4, [r12,#0x58] @ PWRCON(2) for timer setup
|
| 171 | 176 | str r11, [r12,#0x6c] @ PWRCON(4) for timer setup @ R11: Unused
|
| 172 | 177 | orr r11, r12, #0x00200000 @ R11: TIMER base address
|
| 173 | 178 | str r0, [r11,#0x4] @ TACMD = 0x10
|
| — | — | @@ -188,23 +193,23 @@ |
| 189 | 194 | str r1, [r12,#0x4c] @ PWRCON(1) @ R1: Unused
|
| 190 | 195 | mov r3, #0x73
|
| 191 | 196 | str r3, [r12,#0x58] @ PWRCON(2)
|
| 192 | | - str r2, [r12,#0x6c] @ PWRCON(4) @ R2: Unused
|
| | 197 | + str r2, [r12,#0x6c] @ PWRCON(4) @ R2: Unused
|
| 193 | 198 | orr r10, r11, #0x00800000 @ R10: GPIO base address
|
| 194 | 199 |
|
| 195 | | - @ Block 3 (GPIO) register map:
|
| 196 | | - @ R0: Unused
|
| 197 | | - @ R1: Unused
|
| 198 | | - @ R2: Unused
|
| 199 | | - @ R3: Scratchpad
|
| 200 | | - @ R4: -1
|
| 201 | | - @ R5: 1
|
| 202 | | - @ R6: Unused
|
| 203 | | - @ R7: Unused
|
| 204 | | - @ R8: Unused
|
| 205 | | - @ R9: Unused
|
| 206 | | - @ R10: GPIO base address
|
| 207 | | - @ R11: TIMER base address
|
| 208 | | - @ R12: SYSCON base address
|
| | 200 | + @ Block 3 (GPIO) register map:
|
| | 201 | + @ R0: Unused
|
| | 202 | + @ R1: Unused
|
| | 203 | + @ R2: Unused
|
| | 204 | + @ R3: Scratchpad
|
| | 205 | + @ R4: -1
|
| | 206 | + @ R5: 1
|
| | 207 | + @ R6: Unused
|
| | 208 | + @ R7: Unused
|
| | 209 | + @ R8: Unused
|
| | 210 | + @ R9: Unused
|
| | 211 | + @ R10: GPIO base address
|
| | 212 | + @ R11: TIMER base address
|
| | 213 | + @ R12: SYSCON base address
|
| 209 | 214 | @ R13: Constant pool pointer
|
| 210 | 215 | @ R14: 0
|
| 211 | 216 |
|
| — | — | @@ -227,7 +232,7 @@ |
| 228 | 233 | .endm
|
| 229 | 234 |
|
| 230 | 235 | ldr r3, [sp], #0x4
|
| 231 | | - str r3, [r10], #0xc @ R10: PCONx iterator
|
| | 236 | + str r3, [r10], #0xc @ R10: PCONx iterator
|
| 232 | 237 | mov r3, #0x20
|
| 233 | 238 | str r3, [r10], #0x4 @ PCON0 + 0xc = 0x20
|
| 234 | 239 | mov r3, #0x40
|
| — | — | @@ -240,7 +245,7 @@ |
| 241 | 246 | str lr, [r10], #0x10 @ PCON + 0x10 = 0
|
| 242 | 247 | cmp r10, r9
|
| 243 | 248 | bls gpioloop1
|
| 244 | | - @ R10: 0x3CF001E0
|
| | 249 | + @ R10: 0x3CF001E0
|
| 245 | 250 | ldr r3, [r10,#0x1a8]
|
| 246 | 251 | bic r3, r3, #2
|
| 247 | 252 | orr r3, r3, #1
|
| — | — | @@ -255,12 +260,12 @@ |
| 256 | 261 | add r8, r8, #4
|
| 257 | 262 | subs r9, r9, #1
|
| 258 | 263 | bne gpioloop2
|
| 259 | | - @ R9: 0
|
| 260 | | - ldr r8, [r10,#-0x180] @ R8: PCON3 backup
|
| | 264 | + @ R9: 0
|
| | 265 | + ldr r8, [r10,#-0x180] @ R8: PCON3 backup
|
| 261 | 266 | and r3, r8, #0xff
|
| 262 | 267 | str r3, [r10,#-0x180] @ *PCON3 &= 0xff
|
| 263 | | - mov r0, #0x3e8 @ R0: Scratchpad
|
| 264 | | - bl udelay @ R14: Return address
|
| | 268 | + mov r0, #0x3e8 @ R0: Scratchpad
|
| | 269 | + bl udelay @ R14: Return address
|
| 265 | 270 | ldr r3, [r10,#-0x17c]
|
| 266 | 271 | and r3, r3, #0xfc
|
| 267 | 272 | mov r6, r3, lsr #0x2 @ R6: Data for first PMU access
|
| — | — | @@ -267,20 +272,20 @@ |
| 268 | 273 | str r8, [r10,#-0x180]
|
| 269 | 274 | bic r10, r11, #0x00100000 @ R10: I2C base address
|
| 270 | 275 |
|
| 271 | | - @ Block 4 (I2C) register map:
|
| 272 | | - @ R0: Scratchpad
|
| 273 | | - @ R1: Scratchpad
|
| 274 | | - @ R2: Unused
|
| 275 | | - @ R3: Unused
|
| 276 | | - @ R4: -1
|
| 277 | | - @ R5: 1
|
| 278 | | - @ R6: Data for first PMU access
|
| 279 | | - @ R7: Unused
|
| 280 | | - @ R8: Unused
|
| 281 | | - @ R9: 0
|
| 282 | | - @ R10: I2C base address
|
| 283 | | - @ R11: TIMER base address
|
| 284 | | - @ R12: SYSCON base address
|
| | 276 | + @ Block 4 (I2C) register map:
|
| | 277 | + @ R0: Scratchpad
|
| | 278 | + @ R1: Scratchpad
|
| | 279 | + @ R2: Unused
|
| | 280 | + @ R3: Unused
|
| | 281 | + @ R4: -1
|
| | 282 | + @ R5: 1
|
| | 283 | + @ R6: Data for first PMU access
|
| | 284 | + @ R7: Unused
|
| | 285 | + @ R8: Unused
|
| | 286 | + @ R9: 0
|
| | 287 | + @ R10: I2C base address
|
| | 288 | + @ R11: TIMER base address
|
| | 289 | + @ R12: SYSCON base address
|
| 285 | 290 | @ R13: Constant pool pointer
|
| 286 | 291 | @ R14: Return address / Scratchpad
|
| 287 | 292 |
|
| — | — | @@ -308,20 +313,20 @@ |
| 309 | 314 | str r0, [r10,#0x04]
|
| 310 | 315 | bl i2cwaitrdy
|
| 311 | 316 |
|
| 312 | | - @ Block 5 (PMU) register map:
|
| 313 | | - @ R0: Address / Scratchpad (trashed by pmubatch)
|
| 314 | | - @ R1: Data / Scratchpad (trashed by pmubatch)
|
| 315 | | - @ R2: Scratchpad (set to 0xb7 by pmu accesses)
|
| 316 | | - @ R3: Scratchpad (set to 0x10 by pmu accesses)
|
| 317 | | - @ R4: Scratchpad (trashed by pmu accesses)
|
| 318 | | - @ R5: 1
|
| 319 | | - @ R6: Data for first PMU access
|
| 320 | | - @ R7: Scratchpad (trashed by pmubatch)
|
| 321 | | - @ R8: Used to store warmboot flag
|
| 322 | | - @ R9: 0 / pmubatch transfer count (reset to 0 by pmubatch)
|
| 323 | | - @ R10: I2C base address
|
| 324 | | - @ R11: TIMER base address
|
| 325 | | - @ R12: SYSCON base address
|
| | 317 | + @ Block 5 (PMU) register map:
|
| | 318 | + @ R0: Address / Scratchpad (trashed by pmubatch)
|
| | 319 | + @ R1: Data / Scratchpad (trashed by pmubatch)
|
| | 320 | + @ R2: Scratchpad (set to 0xb7 by pmu accesses)
|
| | 321 | + @ R3: Scratchpad (set to 0x10 by pmu accesses)
|
| | 322 | + @ R4: Scratchpad (trashed by pmu accesses)
|
| | 323 | + @ R5: 1
|
| | 324 | + @ R6: Data for first PMU access
|
| | 325 | + @ R7: Scratchpad (trashed by pmubatch)
|
| | 326 | + @ R8: Used to store warmboot flag
|
| | 327 | + @ R9: 0 / pmubatch transfer count (reset to 0 by pmubatch)
|
| | 328 | + @ R10: I2C base address
|
| | 329 | + @ R11: TIMER base address
|
| | 330 | + @ R12: SYSCON base address
|
| 326 | 331 | @ R13: Constant pool / pmubatch data pointer
|
| 327 | 332 | @ R14: Return address / Scratchpad
|
| 328 | 333 |
|
| — | — | @@ -344,7 +349,7 @@ |
| 345 | 350 | .endm
|
| 346 | 351 | mov r9, #(pmu_batch_1_end - pmu_batch_1_begin) / 2
|
| 347 | 352 | bl pmubatch
|
| 348 | | - tst r6, #1 @ R6: Unused
|
| | 353 | + tst r6, #1 @ R6: Unused
|
| 349 | 354 | beq pmu_skip
|
| 350 | 355 | mov r0, #0x0d
|
| 351 | 356 | bl pmuread
|
| — | — | @@ -367,7 +372,7 @@ |
| 368 | 373 | bl pmuread
|
| 369 | 374 | bic r1, r1, #0x80
|
| 370 | 375 | orr r1, r1, #0x60
|
| 371 | | -nop@ bl pmuwrite
|
| | 376 | + bl pmuwrite
|
| 372 | 377 | .macro pmu_batch_3
|
| 373 | 378 | pmu_batch_3_begin:
|
| 374 | 379 | .byte 0x44, 0x72
|
| — | — | @@ -421,9 +426,9 @@ |
| 422 | 427 | mov r9, #(pmu_batch_5_end - pmu_batch_5_begin) / 2
|
| 423 | 428 | bl pmubatch
|
| 424 | 429 |
|
| 425 | | - orr lr, r11, #0x00800000 @ R14: GPIO base address
|
| | 430 | + orr lr, r11, #0x00800000 @ R14: GPIO base address
|
| 426 | 431 | str r9, [lr,#0x384]
|
| 427 | | - orr lr, r11, #0x01000000 @ R14: MIU base address
|
| | 432 | + orr lr, r11, #0x01000000 @ R14: MIU base address
|
| 428 | 433 | str r5, [lr]
|
| 429 | 434 | ldrh r0, [sp], #2
|
| 430 | 435 | str r0, [lr,#0x100]
|
| — | — | @@ -431,7 +436,7 @@ |
| 432 | 437 | str r0, [lr,#0x11c]
|
| 433 | 438 | str r0, [lr,#0x120]
|
| 434 | 439 |
|
| 435 | | -.macro block6_constpool @ Block 6 (SDRAM) register map:
|
| | 440 | +.macro block6_constpool @ Block 6 (SDRAM) register map:
|
| 436 | 441 | .hword 0x1030
|
| 437 | 442 | .word 0x008AAC25 @ R0
|
| 438 | 443 | .word 0x050D67E5 @ R1
|
| — | — | @@ -441,18 +446,18 @@ |
| 442 | 447 | .word 0x00008040 @ R5
|
| 443 | 448 | .word 0x8000100F @ R6: For LCD init at end of block
|
| 444 | 449 | .word 0x41100DB8 @ R7: For LCD init at end of block
|
| 445 | | - @ R8: Warmboot flag
|
| 446 | | - @ R9: 0
|
| 447 | | - @ R10: I2C base address
|
| 448 | | - @ R11: TIMER base address
|
| 449 | | - @ R12: SYSCON base address
|
| | 450 | + @ R8: Warmboot flag
|
| | 451 | + @ R9: 0
|
| | 452 | + @ R10: I2C base address
|
| | 453 | + @ R11: TIMER base address
|
| | 454 | + @ R12: SYSCON base address
|
| 450 | 455 | @ R13: Constant pool pointer
|
| 451 | 456 | .endm @ R14: MIU base address
|
| 452 | 457 |
|
| 453 | 458 | ldmia sp!, {r0-r7}
|
| 454 | | - str r0, [lr,#0x114] @ R0: Unused
|
| 455 | | - str r1, [lr,#0x124] @ R1: Unused
|
| 456 | | - mov r0, #0x18 @ R0: Scratchpad
|
| | 459 | + str r0, [lr,#0x114] @ R0: Unused
|
| | 460 | + str r1, [lr,#0x124] @ R1: Unused
|
| | 461 | + mov r0, #8 @ R0: Scratchpad
|
| 457 | 462 | str r0, [lr,#0x118]
|
| 458 | 463 | str r2, [lr,#0x108]
|
| 459 | 464 | mov r0, #4
|
| — | — | @@ -463,7 +468,7 @@ |
| 464 | 469 | ldr r0, [lr,#0x140]
|
| 465 | 470 | tst r0, #2
|
| 466 | 471 | beq miu_wait1
|
| 467 | | - add r0, r3, #1 @ R3: Unused
|
| | 472 | + add r0, r3, #1 @ R3: Unused
|
| 468 | 473 | str r0, [lr,#0x140]
|
| 469 | 474 | miu_wait2:
|
| 470 | 475 | ldr r0, [lr,#0x144]
|
| — | — | @@ -470,20 +475,20 @@ |
| 471 | 476 | mvn r0, r0
|
| 472 | 477 | tst r0, #3
|
| 473 | 478 | bne miu_wait2
|
| 474 | | - ldr r1, [lr,#0x144] @ R1: Scratchpad
|
| | 479 | + ldr r1, [lr,#0x144] @ R1: Scratchpad
|
| 475 | 480 | mov r0, #0x0ff00000
|
| 476 | | - and r0, r0, r1, lsl #0x2
|
| 477 | | - add r0, r0, r4 @ R4: Unused
|
| | 481 | + and r0, r0, r1, lsl#2
|
| | 482 | + add r0, r0, r4 @ R4: Unused
|
| 478 | 483 | str r0, [lr,#0x140]
|
| 479 | 484 | mov r0, #0x10
|
| 480 | 485 | str r0, [lr,#0x150]
|
| 481 | | - cmp r8, #0 @ R8: Unused
|
| | 486 | + cmp r8, #0 @ R8: Unused
|
| 482 | 487 | sub r8, r10, #0x04300000 @ R8: LCD base address
|
| 483 | 488 | str r6, [r12,#0x08] @ R6: Unused
|
| 484 | 489 | str r7, [r8] @ R7: Unused
|
| 485 | 490 | mov r0, #0x11
|
| 486 | 491 | str r0, [r8,#0x20]
|
| 487 | | - mov r3, #0x33 @ R3: 0x33
|
| | 492 | + mov r3, #0x33 @ R3: 0x33
|
| 488 | 493 | beq miu_coldboot
|
| 489 | 494 | str r0, [lr,#0x104]
|
| 490 | 495 | b miu_common
|
| — | — | @@ -516,8 +521,8 @@ |
| 517 | 522 | str r3, [lr,#0x104]
|
| 518 | 523 | str r3, [lr,#0x104]
|
| 519 | 524 | str r3, [lr,#0x110]
|
| 520 | | - orr r1, r3, #0x100
|
| 521 | | - str r1, [lr,#0x104]
|
| | 525 | + orr r0, r3, #0x100
|
| | 526 | + str r0, [lr,#0x104]
|
| 522 | 527 | miu_wait6:
|
| 523 | 528 | ldr r0, [lr,#0x104]
|
| 524 | 529 | tst r0, #0x110000
|
| — | — | @@ -525,7 +530,7 @@ |
| 526 | 531 | str r3, [lr,#0x104]
|
| 527 | 532 | str r3, [lr,#0x104]
|
| 528 | 533 | str r3, [lr,#0x104]
|
| 529 | | - str r5, [lr,#0x110] @ R5: Unused
|
| | 534 | + str r5, [lr,#0x110] @ R5: Unused
|
| 530 | 535 | str r1, [lr,#0x104]
|
| 531 | 536 | miu_wait7:
|
| 532 | 537 | ldr r0, [lr,#0x104]
|
| — | — | @@ -534,7 +539,7 @@ |
| 535 | 540 | str r3, [lr,#0x104]
|
| 536 | 541 | str r3, [lr,#0x104]
|
| 537 | 542 | miu_common:
|
| 538 | | - str r3, [lr,#0x104] @ R3: Unused
|
| | 543 | + str r3, [lr,#0x104] @ R3: Unused
|
| 539 | 544 | mov r0, #0x40
|
| 540 | 545 | str r0, [lr,#0x10c]
|
| 541 | 546 | ldr r0, [lr,#0x100]
|
| — | — | @@ -544,7 +549,7 @@ |
| 545 | 550 | str r0, [lr,#0x11c]
|
| 546 | 551 | mov r0, #1
|
| 547 | 552 | str r0, [lr,#0x120]
|
| 548 | | - orr r1, r2, #0x1000 @ R2: Unused
|
| | 553 | + orr r1, r2, #0x1000 @ R2: Unused
|
| 549 | 554 | str r1, [lr,#0x108]
|
| 550 | 555 | str r0, [lr,#0x08]
|
| 551 | 556 | mov r1, #0x3e000000
|
| — | — | @@ -552,7 +557,7 @@ |
| 553 | 558 | str r0, [r1,#0x08]
|
| 554 | 559 |
|
| 555 | 560 | @ Block 7 (LCD) register map:
|
| 556 | | - @ R0: Cmd/Data to be written / Scratchpad
|
| | 561 | + @ R0: Cmd/Data to be written / Scratchpad
|
| 557 | 562 | @ R1: Scratchpad
|
| 558 | 563 | @ R2: Scratchpad
|
| 559 | 564 | @ R3: Scratchpad
|
| — | — | @@ -560,11 +565,11 @@ |
| 561 | 566 | @ R5: Scratchpad
|
| 562 | 567 | @ R6: Unused
|
| 563 | 568 | @ R7: Unused
|
| 564 | | - @ R8: LCD base address
|
| 565 | | - @ R9: 0
|
| 566 | | - @ R10: I2C base address
|
| 567 | | - @ R11: TIMER base address
|
| 568 | | - @ R12: SYSCON base address
|
| | 569 | + @ R8: LCD base address
|
| | 570 | + @ R9: 0
|
| | 571 | + @ R10: I2C base address
|
| | 572 | + @ R11: TIMER base address
|
| | 573 | + @ R12: SYSCON base address
|
| 569 | 574 | @ R13: LCD init script pointer / Scratchpad
|
| 570 | 575 | @ R14: Return address / Scratchpad
|
| 571 | 576 |
|
| — | — | @@ -575,6 +580,7 @@ |
| 576 | 581 | .word lcd_sequence_e6 - lcd_sequences_begin
|
| 577 | 582 | .word lcd_sequence_b3 - lcd_sequences_begin
|
| 578 | 583 | lcd_sequence_b3:
|
| | 584 | +.byte 0x01, 0x11, 0xf8, 0x01, 0x13, 0x01, 0x29, 0x80
|
| 579 | 585 | .byte 0x01, 0x11
|
| 580 | 586 | .byte 0xf8
|
| 581 | 587 | .byte 0x02, 0xfe, 0x00
|
| — | — | @@ -597,12 +603,13 @@ |
| 598 | 604 | .byte 0x0c, 0xe2, 0x7e, 0x04, 0x43, 0x40, 0x00, 0x02, 0x13, 0x00, 0x00, 0x01, 0x0b
|
| 599 | 605 | .byte 0x0c, 0xe3, 0x40, 0x40, 0x03, 0x74, 0x0e, 0x00, 0x00, 0x31, 0x02, 0x0b, 0x01
|
| 600 | 606 | .byte 0x0c, 0xe4, 0x5a, 0x43, 0x67, 0x56, 0x00, 0x02, 0x67, 0x72, 0x00, 0x05, 0x12
|
| 601 | | - .byte 0x0c, 0xe5, 0x50, 0x66, 0x47, 0x53, 0x0a, 0x00, 0x27, 0x76, 0x02, 0x12, 0x02
|
| | 607 | + .byte 0x0c, 0xe5, 0x50, 0x66, 0x47, 0x53, 0x0a, 0x00, 0x27, 0x76, 0x02, 0x12, 0x05
|
| 602 | 608 | .byte 0x02, 0x3a, 0x06
|
| 603 | 609 | .byte 0x01, 0x13
|
| 604 | 610 | .byte 0x01, 0x29
|
| 605 | 611 | .byte 0x80
|
| 606 | 612 | lcd_sequence_c4:
|
| | 613 | +.byte 0x01, 0x01, 0x85, 0x01, 0x11, 0x01, 0x29, 0x80
|
| 607 | 614 | .byte 0x01, 0x01
|
| 608 | 615 | .byte 0x85
|
| 609 | 616 | .byte 0x02, 0xc0, 0x00
|
| — | — | @@ -612,7 +619,7 @@ |
| 613 | 620 | .byte 0x03, 0xc4, 0x73, 0x03
|
| 614 | 621 | .byte 0x03, 0xc5, 0x3c, 0x3c
|
| 615 | 622 | .byte 0x02, 0xfe, 0x00
|
| 616 | | -@ .byte 0x03, 0xb1, 0x6a, 0x15
|
| | 623 | + .byte 0x03, 0xb1, 0x6a, 0x15
|
| 617 | 624 | .byte 0x03, 0xb2, 0x6a, 0x15
|
| 618 | 625 | .byte 0x03, 0xb3, 0x6a, 0x15
|
| 619 | 626 | .byte 0x02, 0xb4, 0x02
|
| — | — | @@ -625,12 +632,13 @@ |
| 626 | 633 | .byte 0x0c, 0xe3, 0x3f, 0x10, 0x16, 0x44, 0x0e, 0x04, 0x6c, 0x44, 0x04, 0x03, 0x0b
|
| 627 | 634 | .byte 0x0c, 0xe4, 0x00, 0x61, 0x77, 0x04, 0x02, 0x04, 0x72, 0x32, 0x09, 0x19, 0x06
|
| 628 | 635 | .byte 0x0c, 0xe5, 0x4f, 0x42, 0x27, 0x67, 0x0f, 0x02, 0x26, 0x33, 0x01, 0x03, 0x09
|
| 629 | | -@ .byte 0x02, 0x3a, 0x66
|
| | 636 | + .byte 0x02, 0x3a, 0x66
|
| 630 | 637 | .byte 0x02, 0x36, 0x00
|
| 631 | 638 | .byte 0x01, 0x11
|
| 632 | 639 | .byte 0x01, 0x29
|
| 633 | 640 | .byte 0x80
|
| 634 | 641 | lcd_sequence_d5:
|
| | 642 | +.byte 0x01, 0x01, 0x85, 0x01, 0x11, 0x01, 0x29, 0x80
|
| 635 | 643 | .byte 0x02, 0xfe, 0x00
|
| 636 | 644 | .byte 0x02, 0xc0, 0x01
|
| 637 | 645 | .byte 0x02, 0xc1, 0x01
|
| — | — | @@ -658,6 +666,7 @@ |
| 659 | 667 | .byte 0x01, 0x29
|
| 660 | 668 | .byte 0x80
|
| 661 | 669 | lcd_sequence_e6:
|
| | 670 | +.byte 0x01, 0x11, 0xf8, 0x01, 0x13, 0x01, 0x29, 0x80
|
| 662 | 671 | .byte 0x01, 0x11
|
| 663 | 672 | .byte 0xf8
|
| 664 | 673 | .byte 0x02, 0xfe, 0x00
|
| — | — | @@ -715,10 +724,23 @@ |
| 716 | 725 | bl sendlcdd
|
| 717 | 726 | b lcdbyte
|
| 718 | 727 |
|
| 719 | | - @ udelay register map:
|
| 720 | | - @ R0: Microseconds
|
| 721 | | - @ R1: Trashed
|
| 722 | | - @ R11: TIMER base address
|
| | 728 | +values1:
|
| | 729 | + block0_constpool
|
| | 730 | + block1_constpool
|
| | 731 | + gpio_initdata
|
| | 732 | + pmu_batch_1
|
| | 733 | + pmu_batch_2
|
| | 734 | + pmu_batch_3
|
| | 735 | + pmu_batch_4
|
| | 736 | + pmu_batch_5
|
| | 737 | + block6_constpool
|
| | 738 | + lcd_sequences
|
| | 739 | + .align 2
|
| | 740 | +
|
| | 741 | + @ udelay register map:
|
| | 742 | + @ R0: Microseconds
|
| | 743 | + @ R1: Trashed
|
| | 744 | + @ R11: TIMER base address
|
| 723 | 745 | @ R14: Return address
|
| 724 | 746 |
|
| 725 | 747 | udelay:
|
| — | — | @@ -730,9 +752,9 @@ |
| 731 | 753 | bmi udelayloop
|
| 732 | 754 | mov pc, lr
|
| 733 | 755 |
|
| 734 | | - @ i2cwaitrdy register map:
|
| 735 | | - @ R9: Set to 0
|
| 736 | | - @ R10: I2C base address
|
| | 756 | + @ i2cwaitrdy register map:
|
| | 757 | + @ R9: Set to 0
|
| | 758 | + @ R10: I2C base address
|
| 737 | 759 | @ R14: Return address
|
| 738 | 760 |
|
| 739 | 761 | i2cwaitrdy:
|
| — | — | @@ -741,9 +763,9 @@ |
| 742 | 764 | bne i2cwaitrdy
|
| 743 | 765 | mov pc, lr
|
| 744 | 766 |
|
| 745 | | - @ i2cwait register map:
|
| 746 | | - @ R3: Set to 0x10
|
| 747 | | - @ R10: I2C base address
|
| | 767 | + @ i2cwait register map:
|
| | 768 | + @ R3: Set to 0x10
|
| | 769 | + @ R10: I2C base address
|
| 748 | 770 | @ R14: Return address
|
| 749 | 771 |
|
| 750 | 772 | i2cwait:
|
| — | — | @@ -752,13 +774,13 @@ |
| 753 | 775 | beq i2cwait
|
| 754 | 776 | mov pc, lr
|
| 755 | 777 |
|
| 756 | | - @ pmuwrite register map:
|
| 757 | | - @ R0: Address
|
| 758 | | - @ R1: Data
|
| 759 | | - @ R2: Set to 0xb7
|
| 760 | | - @ R3: Set to 0x10
|
| 761 | | - @ R4: Return address backup
|
| 762 | | - @ R10: I2C base address
|
| | 778 | + @ pmuwrite register map:
|
| | 779 | + @ R0: Address
|
| | 780 | + @ R1: Data
|
| | 781 | + @ R2: Set to 0xb7
|
| | 782 | + @ R3: Set to 0x10
|
| | 783 | + @ R4: Return address backup
|
| | 784 | + @ R10: I2C base address
|
| 763 | 785 | @ R14: Return address / Scratchpad
|
| 764 | 786 |
|
| 765 | 787 | pmuwrite:
|
| — | — | @@ -785,13 +807,13 @@ |
| 786 | 808 | bne pmuwrite_wait
|
| 787 | 809 | mov pc, r4
|
| 788 | 810 |
|
| 789 | | - @ pmuread register map:
|
| 790 | | - @ R0: Address
|
| 791 | | - @ R1: Data
|
| 792 | | - @ R2: Set to 0xb7
|
| 793 | | - @ R3: Set to 0x10
|
| 794 | | - @ R4: Return address backup
|
| 795 | | - @ R10: I2C base address
|
| | 811 | + @ pmuread register map:
|
| | 812 | + @ R0: Address
|
| | 813 | + @ R1: Data
|
| | 814 | + @ R2: Set to 0xb7
|
| | 815 | + @ R3: Set to 0x10
|
| | 816 | + @ R4: Return address backup
|
| | 817 | + @ R10: I2C base address
|
| 796 | 818 | @ R14: Return address / Scratchpad
|
| 797 | 819 |
|
| 798 | 820 | pmuread:
|
| — | — | @@ -820,20 +842,20 @@ |
| 821 | 843 | str lr, [r10,#0x04]
|
| 822 | 844 | str r2, [r10]
|
| 823 | 845 | pmuread_wait:
|
| 824 | | - ldr r1, [r10,#0x04]
|
| 825 | | - tst r1, #0x20
|
| | 846 | + ldr lr, [r10,#0x04]
|
| | 847 | + tst lr, #0x20
|
| 826 | 848 | bne pmuread_wait
|
| 827 | 849 | mov pc, r4
|
| 828 | 850 |
|
| 829 | | - @ pmubatch register map:
|
| 830 | | - @ R0: Scratchpad
|
| 831 | | - @ R1: Scratchpad
|
| 832 | | - @ R2: Set to 0xb7
|
| 833 | | - @ R3: Set to 0x10
|
| 834 | | - @ R4: Inner return address backup
|
| 835 | | - @ R7: Outer return address backup
|
| 836 | | - @ R9: Number of address-data pairs to be sent (must be >0), will be reset to 0
|
| 837 | | - @ R10: I2C base address
|
| | 851 | + @ pmubatch register map:
|
| | 852 | + @ R0: Scratchpad
|
| | 853 | + @ R1: Scratchpad
|
| | 854 | + @ R2: Set to 0xb7
|
| | 855 | + @ R3: Set to 0x10
|
| | 856 | + @ R4: Inner return address backup
|
| | 857 | + @ R7: Outer return address backup
|
| | 858 | + @ R9: Number of address-data pairs to be sent (must be >0), will be reset to 0
|
| | 859 | + @ R10: I2C base address
|
| 838 | 860 | @ R13: Address-data pair list pointer (will be incremented)
|
| 839 | 861 | @ R14: Return address / Scratchpad
|
| 840 | 862 |
|
| — | — | @@ -847,10 +869,10 @@ |
| 848 | 870 | bne pmubatch_loop
|
| 849 | 871 | mov pc, r7
|
| 850 | 872 |
|
| 851 | | - @ sendlcdc register map:
|
| 852 | | - @ R0: Command to be sent
|
| 853 | | - @ R8: LCD base address
|
| 854 | | - @ R9: Will be set to 0
|
| | 873 | + @ sendlcdc register map:
|
| | 874 | + @ R0: Command to be sent
|
| | 875 | + @ R8: LCD base address
|
| | 876 | + @ R9: Will be set to 0
|
| 855 | 877 | @ R14: Return address
|
| 856 | 878 |
|
| 857 | 879 | sendlcdc:
|
| — | — | @@ -860,10 +882,10 @@ |
| 861 | 883 | str r0, [r8,#0x04]
|
| 862 | 884 | mov pc, lr
|
| 863 | 885 |
|
| 864 | | - @ sendlcdd register map:
|
| 865 | | - @ R0: Data to be sent
|
| 866 | | - @ R8: LCD base address
|
| 867 | | - @ R9: Will be set to 0
|
| | 886 | + @ sendlcdd register map:
|
| | 887 | + @ R0: Data to be sent
|
| | 888 | + @ R8: LCD base address
|
| | 889 | + @ R9: Will be set to 0
|
| 868 | 890 | @ R14: Return address
|
| 869 | 891 |
|
| 870 | 892 | sendlcdd:
|
| — | — | @@ -873,9 +895,9 @@ |
| 874 | 896 | str r0, [r8,#0x40]
|
| 875 | 897 | mov pc, lr
|
| 876 | 898 |
|
| 877 | | - @ readlcd register map:
|
| 878 | | - @ R0: Result data
|
| 879 | | - @ R8: LCD base address
|
| | 899 | + @ readlcd register map:
|
| | 900 | + @ R0: Result data
|
| | 901 | + @ R8: LCD base address
|
| 880 | 902 | @ R14: Return address
|
| 881 | 903 |
|
| 882 | 904 | readlcd:
|
| — | — | @@ -892,6 +914,9 @@ |
| 893 | 915 | mov pc, lr
|
| 894 | 916 |
|
| 895 | 917 | lcddone:
|
| | 918 | + bic r1, r10, #0x04400000
|
| | 919 | + mov r0, #1
|
| | 920 | + str r0, [r1,#0x30]
|
| 896 | 921 | ldr r0, _stubend
|
| 897 | 922 | adr r1, _stubend + 4
|
| 898 | 923 | mov r2, #0x08000000
|
| — | — | @@ -901,22 +926,10 @@ |
| 902 | 927 | ldrhi r3, [r1], #4
|
| 903 | 928 | strhi r3, [r2], #4
|
| 904 | 929 | bhi movepayloadloop
|
| 905 | | - mcr p15, 0, r9,c7,c14,0 @ clean & invalidate data cache
|
| | 930 | + mcr p15, 0, r9,c7,c14,0 @ clean data cache
|
| 906 | 931 | mcr p15, 0, r9,c7,c10,4 @ drain write buffer
|
| 907 | | - mcr p15, 0, r9,c7,c5 @ invalidate instruction cache
|
| | 932 | + mcr p15, 0, r9,c7,c5,0 @ invalidate instruction cache
|
| | 933 | + mcr p15, 0, r9,c7,c5,4 @ flush prefetch buffer
|
| 908 | 934 | mov pc, #0x08000000
|
| 909 | 935 |
|
| 910 | | -values1:
|
| 911 | | - block0_constpool
|
| 912 | | - block1_constpool
|
| 913 | | - gpio_initdata
|
| 914 | | - pmu_batch_1
|
| 915 | | - pmu_batch_2
|
| 916 | | - pmu_batch_3
|
| 917 | | - pmu_batch_4
|
| 918 | | - pmu_batch_5
|
| 919 | | - block6_constpool
|
| 920 | | - lcd_sequences
|
| 921 | | - .align 2
|
| 922 | | -
|
| 923 | 936 | _stubend:
|
