freemyipod r642 - Code Review

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Repository:freemyipod
Revision:< r641‎ | r642 | r643 >
Date:01:33, 22 February 2011
Author:theseven
Status:new
Tags:
Comment:
emCORE: Some sector buffer alignment fixes
Modified paths:
  • /emcore/trunk/dir.h (modified) (history)
  • /emcore/trunk/fat.h (modified) (history)
  • /emcore/trunk/target/ipodnano3g/s5l8702.h (modified) (history)

Diff [purge]

Index: emcore/trunk/target/ipodnano3g/s5l8702.h
——@@ -573,189 +573,189 @@
574574
575575
576576 /////SDCI/////
577 -#define SDCI_CTRL (*((uint32_t volatile*)(0x38b00000)))
578 -#define SDCI_DCTRL (*((uint32_t volatile*)(0x38b00004)))
579 -#define SDCI_CMD (*((uint32_t volatile*)(0x38b00008)))
580 -#define SDCI_ARGU (*((uint32_t volatile*)(0x38b0000c)))
581 -#define SDCI_STATE (*((uint32_t volatile*)(0x38b00010)))
582 -#define SDCI_STAC (*((uint32_t volatile*)(0x38b00014)))
583 -#define SDCI_DSTA (*((uint32_t volatile*)(0x38b00018)))
584 -#define SDCI_FSTA (*((uint32_t volatile*)(0x38b0001c)))
585 -#define SDCI_RESP0 (*((uint32_t volatile*)(0x38b00020)))
586 -#define SDCI_RESP1 (*((uint32_t volatile*)(0x38b00024)))
587 -#define SDCI_RESP2 (*((uint32_t volatile*)(0x38b00028)))
588 -#define SDCI_RESP3 (*((uint32_t volatile*)(0x38b0002c)))
589 -#define SDCI_CDIV (*((uint32_t volatile*)(0x38b00030)))
590 -#define SDCI_SDIO_CSR (*((uint32_t volatile*)(0x38b00034)))
591 -#define SDCI_IRQ (*((uint32_t volatile*)(0x38b00038)))
592 -#define SDCI_IRQ_MASK (*((uint32_t volatile*)(0x38b0003c)))
593 -#define SDCI_DATA (*((uint32_t volatile*)(0x38b00040)))
594 -#define SDCI_DMAADDR (*((void* volatile*)(0x38b00044)))
595 -#define SDCI_DMASIZE (*((uint32_t volatile*)(0x38b00048)))
596 -#define SDCI_DMACOUNT (*((uint32_t volatile*)(0x38b0004c)))
597 -#define SDCI_RESET (*((uint32_t volatile*)(0x38b0006c)))
 577+#define SDCI_CTRL (*((uint32_t volatile*)(0x38b00000)))
 578+#define SDCI_DCTRL (*((uint32_t volatile*)(0x38b00004)))
 579+#define SDCI_CMD (*((uint32_t volatile*)(0x38b00008)))
 580+#define SDCI_ARGU (*((uint32_t volatile*)(0x38b0000c)))
 581+#define SDCI_STATE (*((uint32_t volatile*)(0x38b00010)))
 582+#define SDCI_STAC (*((uint32_t volatile*)(0x38b00014)))
 583+#define SDCI_DSTA (*((uint32_t volatile*)(0x38b00018)))
 584+#define SDCI_FSTA (*((uint32_t volatile*)(0x38b0001c)))
 585+#define SDCI_RESP0 (*((uint32_t volatile*)(0x38b00020)))
 586+#define SDCI_RESP1 (*((uint32_t volatile*)(0x38b00024)))
 587+#define SDCI_RESP2 (*((uint32_t volatile*)(0x38b00028)))
 588+#define SDCI_RESP3 (*((uint32_t volatile*)(0x38b0002c)))
 589+#define SDCI_CDIV (*((uint32_t volatile*)(0x38b00030)))
 590+#define SDCI_SDIO_CSR (*((uint32_t volatile*)(0x38b00034)))
 591+#define SDCI_IRQ (*((uint32_t volatile*)(0x38b00038)))
 592+#define SDCI_IRQ_MASK (*((uint32_t volatile*)(0x38b0003c)))
 593+#define SDCI_DATA (*((uint32_t volatile*)(0x38b00040)))
 594+#define SDCI_DMAADDR (*((void* volatile*)(0x38b00044)))
 595+#define SDCI_DMASIZE (*((uint32_t volatile*)(0x38b00048)))
 596+#define SDCI_DMACOUNT (*((uint32_t volatile*)(0x38b0004c)))
 597+#define SDCI_RESET (*((uint32_t volatile*)(0x38b0006c)))
598598
599 -#define SDCI_CTRL_SDCIEN BIT(0)
600 -#define SDCI_CTRL_CARD_TYPE_MASK BIT(1)
601 -#define SDCI_CTRL_CARD_TYPE_SD 0
602 -#define SDCI_CTRL_CARD_TYPE_MMC BIT(1)
603 -#define SDCI_CTRL_BUS_WIDTH_MASK BITRANGE(2, 3)
604 -#define SDCI_CTRL_BUS_WIDTH_1BIT 0
605 -#define SDCI_CTRL_BUS_WIDTH_4BIT BIT(2)
606 -#define SDCI_CTRL_BUS_WIDTH_8BIT BIT(3)
607 -#define SDCI_CTRL_DMA_EN BIT(4)
608 -#define SDCI_CTRL_L_ENDIAN BIT(5)
609 -#define SDCI_CTRL_DMA_REQ_CON_MASK BIT(6)
610 -#define SDCI_CTRL_DMA_REQ_CON_NEMPTY 0
611 -#define SDCI_CTRL_DMA_REQ_CON_FULL BIT(6)
612 -#define SDCI_CTRL_CLK_SEL_MASK BIT(7)
613 -#define SDCI_CTRL_CLK_SEL_PCLK 0
614 -#define SDCI_CTRL_CLK_SEL_SDCLK BIT(7)
615 -#define SDCI_CTRL_BIT_8 BIT(8)
616 -#define SDCI_CTRL_BIT_14 BIT(14)
617 -
618 -#define SDCI_DCTRL_TXFIFORST BIT(0)
619 -#define SDCI_DCTRL_RXFIFORST BIT(1)
620 -#define SDCI_DCTRL_TRCONT_MASK BITRANGE(4, 5)
621 -#define SDCI_DCTRL_TRCONT_TX BIT(4)
622 -#define SDCI_DCTRL_BUS_TEST_MASK BITRANGE(6, 7)
623 -#define SDCI_DCTRL_BUS_TEST_TX BIT(6)
624 -#define SDCI_DCTRL_BUS_TEST_RX BIT(7)
625 -
626 -#define SDCI_CDIV_CLKDIV_MASK BITRANGE(0, 7)
627 -#define SDCI_CDIV_CLKDIV(x) ((x) >> 1)
628 -#define SDCI_CDIV_CLKDIV_2 BIT(0)
629 -#define SDCI_CDIV_CLKDIV_4 BIT(1)
630 -#define SDCI_CDIV_CLKDIV_8 BIT(2)
631 -#define SDCI_CDIV_CLKDIV_16 BIT(3)
632 -#define SDCI_CDIV_CLKDIV_32 BIT(4)
633 -#define SDCI_CDIV_CLKDIV_64 BIT(5)
634 -#define SDCI_CDIV_CLKDIV_128 BIT(6)
635 -#define SDCI_CDIV_CLKDIV_256 BIT(7)
636 -
637 -#define SDCI_CMD_CMD_NUM_MASK BITRANGE(0, 5)
638 -#define SDCI_CMD_CMD_NUM_SHIFT 0
639 -#define SDCI_CMD_CMD_NUM(x) (x)
640 -#define SDCI_CMD_CMD_TYPE_MASK BITRANGE(6, 7)
641 -#define SDCI_CMD_CMD_TYPE_BC 0
642 -#define SDCI_CMD_CMD_TYPE_BCR BIT(6)
643 -#define SDCI_CMD_CMD_TYPE_AC BIT(7)
644 -#define SDCI_CMD_CMD_TYPE_ADTC (BIT(6) | BIT(7))
645 -#define SDCI_CMD_CMD_RD_WR BIT(8)
646 -#define SDCI_CMD_RES_TYPE_MASK BITRANGE(16, 18)
647 -#define SDCI_CMD_RES_TYPE_NONE 0
648 -#define SDCI_CMD_RES_TYPE_R1 BIT(16)
649 -#define SDCI_CMD_RES_TYPE_R2 BIT(17)
650 -#define SDCI_CMD_RES_TYPE_R3 (BIT(16) | BIT(17))
651 -#define SDCI_CMD_RES_TYPE_R4 BIT(18)
652 -#define SDCI_CMD_RES_TYPE_R5 (BIT(16) | BIT(18))
653 -#define SDCI_CMD_RES_TYPE_R6 (BIT(17) | BIT(18))
654 -#define SDCI_CMD_RES_BUSY BIT(19)
655 -#define SDCI_CMD_RES_SIZE_MASK BIT(20)
656 -#define SDCI_CMD_RES_SIZE_48 0
657 -#define SDCI_CMD_RES_SIZE_136 BIT(20)
658 -#define SDCI_CMD_NCR_NID_MASK BIT(21)
659 -#define SDCI_CMD_NCR_NID_NCR 0
660 -#define SDCI_CMD_NCR_NID_NID BIT(21)
661 -#define SDCI_CMD_CMDSTR BIT(31)
662 -
663 -#define SDCI_STATE_DAT_STATE_MASK BITRANGE(0, 3)
664 -#define SDCI_STATE_DAT_STATE_IDLE 0
665 -#define SDCI_STATE_DAT_STATE_DAT_RCV BIT(0)
666 -#define SDCI_STATE_DAT_STATE_CRC_RCV BIT(1)
667 -#define SDCI_STATE_DAT_STATE_DAT_END (BIT(0) | BIT(1))
668 -#define SDCI_STATE_DAT_STATE_DAT_SET BIT(2)
669 -#define SDCI_STATE_DAT_STATE_DAT_OUT (BIT(0) | BIT(2))
670 -#define SDCI_STATE_DAT_STATE_CRC_TIME (BIT(1) | BIT(2))
671 -#define SDCI_STATE_DAT_STATE_CRC_OUT (BIT(0) | BIT(1) | BIT(2))
672 -#define SDCI_STATE_DAT_STATE_ENDB_OUT BIT(3)
673 -#define SDCI_STATE_DAT_STATE_ENDB_STOD (BIT(0) | BIT(3))
674 -#define SDCI_STATE_DAT_STATE_DAT_CRCR (BIT(1) | BIT(3))
675 -#define SDCI_STATE_DAT_STATE_CARD_PRG (BIT(0) | BIT(1) | BIT(3))
676 -#define SDCI_STATE_DAT_STATE_DAT_BUSY (BIT(2) | BIT(3))
677 -#define SDCI_STATE_CMD_STATE_MASK (BIT(4) | BIT(5) | BIT(6))
678 -#define SDCI_STATE_CMD_STATE_CMD_IDLE 0
679 -#define SDCI_STATE_CMD_STATE_CMD_CMDO BIT(4)
680 -#define SDCI_STATE_CMD_STATE_CMD_CRCO BIT(5)
681 -#define SDCI_STATE_CMD_STATE_CMD_TOUT (BIT(4) | BIT(5))
682 -#define SDCI_STATE_CMD_STATE_CMD_RESR BIT(6)
683 -#define SDCI_STATE_CMD_STATE_CMD_INTV (BIT(4) | BIT(6))
684 -
685 -#define SDCI_STAC_CLR_CMDEND BIT(2)
686 -#define SDCI_STAC_CLR_BIT_3 BIT(3)
687 -#define SDCI_STAC_CLR_RESEND BIT(4)
688 -#define SDCI_STAC_CLR_DATEND BIT(6)
689 -#define SDCI_STAC_CLR_DAT_CRCEND BIT(7)
690 -#define SDCI_STAC_CLR_CRC_STAEND BIT(8)
691 -#define SDCI_STAC_CLR_RESTOUTE BIT(15)
692 -#define SDCI_STAC_CLR_RESENDE BIT(16)
693 -#define SDCI_STAC_CLR_RESINDE BIT(17)
694 -#define SDCI_STAC_CLR_RESCRCE BIT(18)
695 -#define SDCI_STAC_CLR_WR_DATCRCE BIT(22)
696 -#define SDCI_STAC_CLR_RD_DATCRCE BIT(23)
697 -#define SDCI_STAC_CLR_RD_DATENDE0 BIT(24)
698 -#define SDCI_STAC_CLR_RD_DATENDE1 BIT(25)
699 -#define SDCI_STAC_CLR_RD_DATENDE2 BIT(26)
700 -#define SDCI_STAC_CLR_RD_DATENDE3 BIT(27)
701 -#define SDCI_STAC_CLR_RD_DATENDE4 BIT(28)
702 -#define SDCI_STAC_CLR_RD_DATENDE5 BIT(29)
703 -#define SDCI_STAC_CLR_RD_DATENDE6 BIT(30)
704 -#define SDCI_STAC_CLR_RD_DATENDE7 BIT(31)
705 -
706 -#define SDCI_DSTA_CMDRDY BIT(0)
707 -#define SDCI_DSTA_CMDPRO BIT(1)
708 -#define SDCI_DSTA_CMDEND BIT(2)
709 -#define SDCI_DSTA_RESPRO BIT(3)
710 -#define SDCI_DSTA_RESEND BIT(4)
711 -#define SDCI_DSTA_DATPRO BIT(5)
712 -#define SDCI_DSTA_DATEND BIT(6)
713 -#define SDCI_DSTA_DAT_CRCEND BIT(7)
714 -#define SDCI_DSTA_CRC_STAEND BIT(8)
715 -#define SDCI_DSTA_DAT_BUSY BIT(9)
716 -#define SDCI_DSTA_SDCLK_HOLD BIT(12)
717 -#define SDCI_DSTA_DAT0_STATUS BIT(13)
718 -#define SDCI_DSTA_WP_DECT_INPUT BIT(14)
719 -#define SDCI_DSTA_RESTOUTE BIT(15)
720 -#define SDCI_DSTA_RESENDE BIT(16)
721 -#define SDCI_DSTA_RESINDE BIT(17)
722 -#define SDCI_DSTA_RESCRCE BIT(18)
723 -#define SDCI_DSTA_WR_CRC_STATUS_MASK BITRANGE(19, 21)
724 -#define SDCI_DSTA_WR_CRC_STATUS_OK BIT(20)
725 -#define SDCI_DSTA_WR_CRC_STATUS_TXERR (BIT(19) | BIT(21))
726 -#define SDCI_DSTA_WR_CRC_STATUS_CARDERR (BIT(19) | BIT(20) | BIT(21))
727 -#define SDCI_DSTA_WR_DATCRCE BIT(22)
728 -#define SDCI_DSTA_RD_DATCRCE BIT(23)
729 -#define SDCI_DSTA_RD_DATENDE0 BIT(24)
730 -#define SDCI_DSTA_RD_DATENDE1 BIT(25)
731 -#define SDCI_DSTA_RD_DATENDE2 BIT(26)
732 -#define SDCI_DSTA_RD_DATENDE3 BIT(27)
733 -#define SDCI_DSTA_RD_DATENDE4 BIT(28)
734 -#define SDCI_DSTA_RD_DATENDE5 BIT(29)
735 -#define SDCI_DSTA_RD_DATENDE6 BIT(30)
736 -#define SDCI_DSTA_RD_DATENDE7 BIT(31)
737 -
738 -#define SDCI_FSTA_RX_FIFO_EMPTY BIT(0)
739 -#define SDCI_FSTA_RX_FIFO_FULL BIT(1)
740 -#define SDCI_FSTA_TX_FIFO_EMPTY BIT(2)
741 -#define SDCI_FSTA_TX_FIFO_FULL BIT(3)
742 -
743 -#define SDCI_SDIO_CSR_SDIO_RW_EN BIT(0)
744 -#define SDCI_SDIO_CSR_SDIO_INT_EN BIT(1)
745 -#define SDCI_SDIO_CSR_SDIO_RW_REQ BIT(2)
746 -#define SDCI_SDIO_CSR_SDIO_RW_STOP BIT(3)
747 -#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MASK BIT(4)
748 -#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MORE 0
749 -#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_XACT BIT(4)
750 -
751 -#define SDCI_IRQ_DAT_DONE_INT BIT(0)
752 -#define SDCI_IRQ_IOCARD_IRQ_INT BIT(1)
753 -#define SDCI_IRQ_READ_WAIT_INT BIT(2)
754 -
755 -#define SDCI_IRQ_MASK_MASK_DAT_DONE_INT BIT(0)
756 -#define SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT BIT(1)
757 -#define SDCI_IRQ_MASK_MASK_READ_WAIT_INT BIT(2)
758 -
 599+#define SDCI_CTRL_SDCIEN BIT(0)
 600+#define SDCI_CTRL_CARD_TYPE_MASK BIT(1)
 601+#define SDCI_CTRL_CARD_TYPE_SD 0
 602+#define SDCI_CTRL_CARD_TYPE_MMC BIT(1)
 603+#define SDCI_CTRL_BUS_WIDTH_MASK BITRANGE(2, 3)
 604+#define SDCI_CTRL_BUS_WIDTH_1BIT 0
 605+#define SDCI_CTRL_BUS_WIDTH_4BIT BIT(2)
 606+#define SDCI_CTRL_BUS_WIDTH_8BIT BIT(3)
 607+#define SDCI_CTRL_DMA_EN BIT(4)
 608+#define SDCI_CTRL_L_ENDIAN BIT(5)
 609+#define SDCI_CTRL_DMA_REQ_CON_MASK BIT(6)
 610+#define SDCI_CTRL_DMA_REQ_CON_NEMPTY 0
 611+#define SDCI_CTRL_DMA_REQ_CON_FULL BIT(6)
 612+#define SDCI_CTRL_CLK_SEL_MASK BIT(7)
 613+#define SDCI_CTRL_CLK_SEL_PCLK 0
 614+#define SDCI_CTRL_CLK_SEL_SDCLK BIT(7)
 615+#define SDCI_CTRL_BIT_8 BIT(8)
 616+#define SDCI_CTRL_BIT_14 BIT(14)
759617
 618+#define SDCI_DCTRL_TXFIFORST BIT(0)
 619+#define SDCI_DCTRL_RXFIFORST BIT(1)
 620+#define SDCI_DCTRL_TRCONT_MASK BITRANGE(4, 5)
 621+#define SDCI_DCTRL_TRCONT_TX BIT(4)
 622+#define SDCI_DCTRL_BUS_TEST_MASK BITRANGE(6, 7)
 623+#define SDCI_DCTRL_BUS_TEST_TX BIT(6)
 624+#define SDCI_DCTRL_BUS_TEST_RX BIT(7)
 625+
 626+#define SDCI_CDIV_CLKDIV_MASK BITRANGE(0, 7)
 627+#define SDCI_CDIV_CLKDIV(x) ((x) >> 1)
 628+#define SDCI_CDIV_CLKDIV_2 BIT(0)
 629+#define SDCI_CDIV_CLKDIV_4 BIT(1)
 630+#define SDCI_CDIV_CLKDIV_8 BIT(2)
 631+#define SDCI_CDIV_CLKDIV_16 BIT(3)
 632+#define SDCI_CDIV_CLKDIV_32 BIT(4)
 633+#define SDCI_CDIV_CLKDIV_64 BIT(5)
 634+#define SDCI_CDIV_CLKDIV_128 BIT(6)
 635+#define SDCI_CDIV_CLKDIV_256 BIT(7)
 636+
 637+#define SDCI_CMD_CMD_NUM_MASK BITRANGE(0, 5)
 638+#define SDCI_CMD_CMD_NUM_SHIFT 0
 639+#define SDCI_CMD_CMD_NUM(x) (x)
 640+#define SDCI_CMD_CMD_TYPE_MASK BITRANGE(6, 7)
 641+#define SDCI_CMD_CMD_TYPE_BC 0
 642+#define SDCI_CMD_CMD_TYPE_BCR BIT(6)
 643+#define SDCI_CMD_CMD_TYPE_AC BIT(7)
 644+#define SDCI_CMD_CMD_TYPE_ADTC (BIT(6) | BIT(7))
 645+#define SDCI_CMD_CMD_RD_WR BIT(8)
 646+#define SDCI_CMD_RES_TYPE_MASK BITRANGE(16, 18)
 647+#define SDCI_CMD_RES_TYPE_NONE 0
 648+#define SDCI_CMD_RES_TYPE_R1 BIT(16)
 649+#define SDCI_CMD_RES_TYPE_R2 BIT(17)
 650+#define SDCI_CMD_RES_TYPE_R3 (BIT(16) | BIT(17))
 651+#define SDCI_CMD_RES_TYPE_R4 BIT(18)
 652+#define SDCI_CMD_RES_TYPE_R5 (BIT(16) | BIT(18))
 653+#define SDCI_CMD_RES_TYPE_R6 (BIT(17) | BIT(18))
 654+#define SDCI_CMD_RES_BUSY BIT(19)
 655+#define SDCI_CMD_RES_SIZE_MASK BIT(20)
 656+#define SDCI_CMD_RES_SIZE_48 0
 657+#define SDCI_CMD_RES_SIZE_136 BIT(20)
 658+#define SDCI_CMD_NCR_NID_MASK BIT(21)
 659+#define SDCI_CMD_NCR_NID_NCR 0
 660+#define SDCI_CMD_NCR_NID_NID BIT(21)
 661+#define SDCI_CMD_CMDSTR BIT(31)
 662+
 663+#define SDCI_STATE_DAT_STATE_MASK BITRANGE(0, 3)
 664+#define SDCI_STATE_DAT_STATE_IDLE 0
 665+#define SDCI_STATE_DAT_STATE_DAT_RCV BIT(0)
 666+#define SDCI_STATE_DAT_STATE_CRC_RCV BIT(1)
 667+#define SDCI_STATE_DAT_STATE_DAT_END (BIT(0) | BIT(1))
 668+#define SDCI_STATE_DAT_STATE_DAT_SET BIT(2)
 669+#define SDCI_STATE_DAT_STATE_DAT_OUT (BIT(0) | BIT(2))
 670+#define SDCI_STATE_DAT_STATE_CRC_TIME (BIT(1) | BIT(2))
 671+#define SDCI_STATE_DAT_STATE_CRC_OUT (BIT(0) | BIT(1) | BIT(2))
 672+#define SDCI_STATE_DAT_STATE_ENDB_OUT BIT(3)
 673+#define SDCI_STATE_DAT_STATE_ENDB_STOD (BIT(0) | BIT(3))
 674+#define SDCI_STATE_DAT_STATE_DAT_CRCR (BIT(1) | BIT(3))
 675+#define SDCI_STATE_DAT_STATE_CARD_PRG (BIT(0) | BIT(1) | BIT(3))
 676+#define SDCI_STATE_DAT_STATE_DAT_BUSY (BIT(2) | BIT(3))
 677+#define SDCI_STATE_CMD_STATE_MASK (BIT(4) | BIT(5) | BIT(6))
 678+#define SDCI_STATE_CMD_STATE_CMD_IDLE 0
 679+#define SDCI_STATE_CMD_STATE_CMD_CMDO BIT(4)
 680+#define SDCI_STATE_CMD_STATE_CMD_CRCO BIT(5)
 681+#define SDCI_STATE_CMD_STATE_CMD_TOUT (BIT(4) | BIT(5))
 682+#define SDCI_STATE_CMD_STATE_CMD_RESR BIT(6)
 683+#define SDCI_STATE_CMD_STATE_CMD_INTV (BIT(4) | BIT(6))
 684+
 685+#define SDCI_STAC_CLR_CMDEND BIT(2)
 686+#define SDCI_STAC_CLR_BIT_3 BIT(3)
 687+#define SDCI_STAC_CLR_RESEND BIT(4)
 688+#define SDCI_STAC_CLR_DATEND BIT(6)
 689+#define SDCI_STAC_CLR_DAT_CRCEND BIT(7)
 690+#define SDCI_STAC_CLR_CRC_STAEND BIT(8)
 691+#define SDCI_STAC_CLR_RESTOUTE BIT(15)
 692+#define SDCI_STAC_CLR_RESENDE BIT(16)
 693+#define SDCI_STAC_CLR_RESINDE BIT(17)
 694+#define SDCI_STAC_CLR_RESCRCE BIT(18)
 695+#define SDCI_STAC_CLR_WR_DATCRCE BIT(22)
 696+#define SDCI_STAC_CLR_RD_DATCRCE BIT(23)
 697+#define SDCI_STAC_CLR_RD_DATENDE0 BIT(24)
 698+#define SDCI_STAC_CLR_RD_DATENDE1 BIT(25)
 699+#define SDCI_STAC_CLR_RD_DATENDE2 BIT(26)
 700+#define SDCI_STAC_CLR_RD_DATENDE3 BIT(27)
 701+#define SDCI_STAC_CLR_RD_DATENDE4 BIT(28)
 702+#define SDCI_STAC_CLR_RD_DATENDE5 BIT(29)
 703+#define SDCI_STAC_CLR_RD_DATENDE6 BIT(30)
 704+#define SDCI_STAC_CLR_RD_DATENDE7 BIT(31)
 705+
 706+#define SDCI_DSTA_CMDRDY BIT(0)
 707+#define SDCI_DSTA_CMDPRO BIT(1)
 708+#define SDCI_DSTA_CMDEND BIT(2)
 709+#define SDCI_DSTA_RESPRO BIT(3)
 710+#define SDCI_DSTA_RESEND BIT(4)
 711+#define SDCI_DSTA_DATPRO BIT(5)
 712+#define SDCI_DSTA_DATEND BIT(6)
 713+#define SDCI_DSTA_DAT_CRCEND BIT(7)
 714+#define SDCI_DSTA_CRC_STAEND BIT(8)
 715+#define SDCI_DSTA_DAT_BUSY BIT(9)
 716+#define SDCI_DSTA_SDCLK_HOLD BIT(12)
 717+#define SDCI_DSTA_DAT0_STATUS BIT(13)
 718+#define SDCI_DSTA_WP_DECT_INPUT BIT(14)
 719+#define SDCI_DSTA_RESTOUTE BIT(15)
 720+#define SDCI_DSTA_RESENDE BIT(16)
 721+#define SDCI_DSTA_RESINDE BIT(17)
 722+#define SDCI_DSTA_RESCRCE BIT(18)
 723+#define SDCI_DSTA_WR_CRC_STATUS_MASK BITRANGE(19, 21)
 724+#define SDCI_DSTA_WR_CRC_STATUS_OK BIT(20)
 725+#define SDCI_DSTA_WR_CRC_STATUS_TXERR (BIT(19) | BIT(21))
 726+#define SDCI_DSTA_WR_CRC_STATUS_CARDERR (BIT(19) | BIT(20) | BIT(21))
 727+#define SDCI_DSTA_WR_DATCRCE BIT(22)
 728+#define SDCI_DSTA_RD_DATCRCE BIT(23)
 729+#define SDCI_DSTA_RD_DATENDE0 BIT(24)
 730+#define SDCI_DSTA_RD_DATENDE1 BIT(25)
 731+#define SDCI_DSTA_RD_DATENDE2 BIT(26)
 732+#define SDCI_DSTA_RD_DATENDE3 BIT(27)
 733+#define SDCI_DSTA_RD_DATENDE4 BIT(28)
 734+#define SDCI_DSTA_RD_DATENDE5 BIT(29)
 735+#define SDCI_DSTA_RD_DATENDE6 BIT(30)
 736+#define SDCI_DSTA_RD_DATENDE7 BIT(31)
 737+
 738+#define SDCI_FSTA_RX_FIFO_EMPTY BIT(0)
 739+#define SDCI_FSTA_RX_FIFO_FULL BIT(1)
 740+#define SDCI_FSTA_TX_FIFO_EMPTY BIT(2)
 741+#define SDCI_FSTA_TX_FIFO_FULL BIT(3)
 742+
 743+#define SDCI_SDIO_CSR_SDIO_RW_EN BIT(0)
 744+#define SDCI_SDIO_CSR_SDIO_INT_EN BIT(1)
 745+#define SDCI_SDIO_CSR_SDIO_RW_REQ BIT(2)
 746+#define SDCI_SDIO_CSR_SDIO_RW_STOP BIT(3)
 747+#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MASK BIT(4)
 748+#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MORE 0
 749+#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_XACT BIT(4)
 750+
 751+#define SDCI_IRQ_DAT_DONE_INT BIT(0)
 752+#define SDCI_IRQ_IOCARD_IRQ_INT BIT(1)
 753+#define SDCI_IRQ_READ_WAIT_INT BIT(2)
 754+
 755+#define SDCI_IRQ_MASK_MASK_DAT_DONE_INT BIT(0)
 756+#define SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT BIT(1)
 757+#define SDCI_IRQ_MASK_MASK_READ_WAIT_INT BIT(2)
 758+
 759+
760760 /////CLICKWHEEL/////
761761 #define WHEEL00 (*((uint32_t volatile*)(0x3C200000)))
762762 #define WHEEL04 (*((uint32_t volatile*)(0x3C200004)))
Index: emcore/trunk/fat.h
——@@ -90,11 +90,11 @@
9191
9292 struct fat_dir
9393 {
 94+ unsigned char sectorcache[SECTOR_SIZE] CACHEALIGN_ATTR;
9495 unsigned int entry;
9596 unsigned int entrycount;
9697 long sector;
9798 struct fat_file file;
98 - unsigned char sectorcache[SECTOR_SIZE] CACHEALIGN_ATTR;
9999 /* There are 2-bytes per characters. We don't want to bother too much, as LFN entries are
100100 * at much 255 characters longs, that's at most 20 LFN entries. Each entry hold at most
101101 * 13 characters, that a total of 260 characters. So we keep a buffer of that size.
Index: emcore/trunk/dir.h
——@@ -48,9 +48,9 @@
4949 #include "fat.h"
5050
5151 typedef struct dirdesc {
 52+ struct fat_dir fatdir CACHEALIGN_ATTR;
5253 struct dirdesc* next;
5354 long startcluster;
54 - struct fat_dir fatdir;
5555 struct dirent theent;
5656 struct scheduler_thread* process;
5757 #ifdef HAVE_MULTIVOLUME
Retrieved from "https://freemyipod.org/wiki/Special:Code/freemyipod/642"