Index: emcore/trunk/target/ipodnano3g/s5l8702.h |
— | — | @@ -572,6 +572,190 @@ |
573 | 573 | #define ATA_DMA_ADDR (*((void* volatile*)(0x38700088))) |
574 | 574 | |
575 | 575 | |
| 576 | +/////SDCI///// |
| 577 | +#define SDCI_CTRL (*((uint32_t volatile*)(0x38b00000)))
|
| 578 | +#define SDCI_DCTRL (*((uint32_t volatile*)(0x38b00004)))
|
| 579 | +#define SDCI_CMD (*((uint32_t volatile*)(0x38b00008)))
|
| 580 | +#define SDCI_ARGU (*((uint32_t volatile*)(0x38b0000c)))
|
| 581 | +#define SDCI_STATE (*((uint32_t volatile*)(0x38b00010)))
|
| 582 | +#define SDCI_STAC (*((uint32_t volatile*)(0x38b00014)))
|
| 583 | +#define SDCI_DSTA (*((uint32_t volatile*)(0x38b00018)))
|
| 584 | +#define SDCI_FSTA (*((uint32_t volatile*)(0x38b0001c)))
|
| 585 | +#define SDCI_RESP0 (*((uint32_t volatile*)(0x38b00020)))
|
| 586 | +#define SDCI_RESP1 (*((uint32_t volatile*)(0x38b00024)))
|
| 587 | +#define SDCI_RESP2 (*((uint32_t volatile*)(0x38b00028)))
|
| 588 | +#define SDCI_RESP3 (*((uint32_t volatile*)(0x38b0002c)))
|
| 589 | +#define SDCI_CDIV (*((uint32_t volatile*)(0x38b00030)))
|
| 590 | +#define SDCI_SDIO_CSR (*((uint32_t volatile*)(0x38b00034)))
|
| 591 | +#define SDCI_IRQ (*((uint32_t volatile*)(0x38b00038)))
|
| 592 | +#define SDCI_IRQ_MASK (*((uint32_t volatile*)(0x38b0003c)))
|
| 593 | +#define SDCI_DATA (*((uint32_t volatile*)(0x38b00040)))
|
| 594 | +#define SDCI_DMAADDR (*((void* volatile*)(0x38b00044)))
|
| 595 | +#define SDCI_DMASIZE (*((uint32_t volatile*)(0x38b00048)))
|
| 596 | +#define SDCI_DMACOUNT (*((uint32_t volatile*)(0x38b0004c)))
|
| 597 | +#define SDCI_RESET (*((uint32_t volatile*)(0x38b0006c)))
|
| 598 | + |
| 599 | +#define SDCI_CTRL_SDCIEN BIT(0)
|
| 600 | +#define SDCI_CTRL_CARD_TYPE_MASK BIT(1)
|
| 601 | +#define SDCI_CTRL_CARD_TYPE_SD 0
|
| 602 | +#define SDCI_CTRL_CARD_TYPE_MMC BIT(1)
|
| 603 | +#define SDCI_CTRL_BUS_WIDTH_MASK BITRANGE(2, 3)
|
| 604 | +#define SDCI_CTRL_BUS_WIDTH_1BIT 0
|
| 605 | +#define SDCI_CTRL_BUS_WIDTH_4BIT BIT(2)
|
| 606 | +#define SDCI_CTRL_BUS_WIDTH_8BIT BIT(3)
|
| 607 | +#define SDCI_CTRL_DMA_EN BIT(4)
|
| 608 | +#define SDCI_CTRL_L_ENDIAN BIT(5)
|
| 609 | +#define SDCI_CTRL_DMA_REQ_CON_MASK BIT(6)
|
| 610 | +#define SDCI_CTRL_DMA_REQ_CON_NEMPTY 0
|
| 611 | +#define SDCI_CTRL_DMA_REQ_CON_FULL BIT(6)
|
| 612 | +#define SDCI_CTRL_CLK_SEL_MASK BIT(7)
|
| 613 | +#define SDCI_CTRL_CLK_SEL_PCLK 0
|
| 614 | +#define SDCI_CTRL_CLK_SEL_SDCLK BIT(7)
|
| 615 | +#define SDCI_CTRL_BIT_8 BIT(8)
|
| 616 | +#define SDCI_CTRL_BIT_14 BIT(14)
|
| 617 | +
|
| 618 | +#define SDCI_DCTRL_TXFIFORST BIT(0)
|
| 619 | +#define SDCI_DCTRL_RXFIFORST BIT(1)
|
| 620 | +#define SDCI_DCTRL_TRCONT_MASK BITRANGE(4, 5)
|
| 621 | +#define SDCI_DCTRL_TRCONT_TX BIT(4)
|
| 622 | +#define SDCI_DCTRL_BUS_TEST_MASK BITRANGE(6, 7)
|
| 623 | +#define SDCI_DCTRL_BUS_TEST_TX BIT(6)
|
| 624 | +#define SDCI_DCTRL_BUS_TEST_RX BIT(7)
|
| 625 | +
|
| 626 | +#define SDCI_CDIV_CLKDIV_MASK BITRANGE(0, 7)
|
| 627 | +#define SDCI_CDIV_CLKDIV(x) ((x) >> 1)
|
| 628 | +#define SDCI_CDIV_CLKDIV_2 BIT(0)
|
| 629 | +#define SDCI_CDIV_CLKDIV_4 BIT(1)
|
| 630 | +#define SDCI_CDIV_CLKDIV_8 BIT(2)
|
| 631 | +#define SDCI_CDIV_CLKDIV_16 BIT(3)
|
| 632 | +#define SDCI_CDIV_CLKDIV_32 BIT(4)
|
| 633 | +#define SDCI_CDIV_CLKDIV_64 BIT(5)
|
| 634 | +#define SDCI_CDIV_CLKDIV_128 BIT(6)
|
| 635 | +#define SDCI_CDIV_CLKDIV_256 BIT(7)
|
| 636 | +
|
| 637 | +#define SDCI_CMD_CMD_NUM_MASK BITRANGE(0, 5)
|
| 638 | +#define SDCI_CMD_CMD_NUM_SHIFT 0
|
| 639 | +#define SDCI_CMD_CMD_NUM(x) (x)
|
| 640 | +#define SDCI_CMD_CMD_TYPE_MASK BITRANGE(6, 7)
|
| 641 | +#define SDCI_CMD_CMD_TYPE_BC 0
|
| 642 | +#define SDCI_CMD_CMD_TYPE_BCR BIT(6)
|
| 643 | +#define SDCI_CMD_CMD_TYPE_AC BIT(7)
|
| 644 | +#define SDCI_CMD_CMD_TYPE_ADTC (BIT(6) | BIT(7))
|
| 645 | +#define SDCI_CMD_CMD_RD_WR BIT(8)
|
| 646 | +#define SDCI_CMD_RES_TYPE_MASK BITRANGE(16, 18)
|
| 647 | +#define SDCI_CMD_RES_TYPE_NONE 0
|
| 648 | +#define SDCI_CMD_RES_TYPE_R1 BIT(16)
|
| 649 | +#define SDCI_CMD_RES_TYPE_R2 BIT(17)
|
| 650 | +#define SDCI_CMD_RES_TYPE_R3 (BIT(16) | BIT(17))
|
| 651 | +#define SDCI_CMD_RES_TYPE_R4 BIT(18)
|
| 652 | +#define SDCI_CMD_RES_TYPE_R5 (BIT(16) | BIT(18))
|
| 653 | +#define SDCI_CMD_RES_TYPE_R6 (BIT(17) | BIT(18))
|
| 654 | +#define SDCI_CMD_RES_BUSY BIT(19)
|
| 655 | +#define SDCI_CMD_RES_SIZE_MASK BIT(20)
|
| 656 | +#define SDCI_CMD_RES_SIZE_48 0
|
| 657 | +#define SDCI_CMD_RES_SIZE_136 BIT(20)
|
| 658 | +#define SDCI_CMD_NCR_NID_MASK BIT(21)
|
| 659 | +#define SDCI_CMD_NCR_NID_NCR 0
|
| 660 | +#define SDCI_CMD_NCR_NID_NID BIT(21)
|
| 661 | +#define SDCI_CMD_CMDSTR BIT(31)
|
| 662 | +
|
| 663 | +#define SDCI_STATE_DAT_STATE_MASK BITRANGE(0, 3)
|
| 664 | +#define SDCI_STATE_DAT_STATE_IDLE 0
|
| 665 | +#define SDCI_STATE_DAT_STATE_DAT_RCV BIT(0)
|
| 666 | +#define SDCI_STATE_DAT_STATE_CRC_RCV BIT(1)
|
| 667 | +#define SDCI_STATE_DAT_STATE_DAT_END (BIT(0) | BIT(1))
|
| 668 | +#define SDCI_STATE_DAT_STATE_DAT_SET BIT(2)
|
| 669 | +#define SDCI_STATE_DAT_STATE_DAT_OUT (BIT(0) | BIT(2))
|
| 670 | +#define SDCI_STATE_DAT_STATE_CRC_TIME (BIT(1) | BIT(2))
|
| 671 | +#define SDCI_STATE_DAT_STATE_CRC_OUT (BIT(0) | BIT(1) | BIT(2))
|
| 672 | +#define SDCI_STATE_DAT_STATE_ENDB_OUT BIT(3)
|
| 673 | +#define SDCI_STATE_DAT_STATE_ENDB_STOD (BIT(0) | BIT(3))
|
| 674 | +#define SDCI_STATE_DAT_STATE_DAT_CRCR (BIT(1) | BIT(3))
|
| 675 | +#define SDCI_STATE_DAT_STATE_CARD_PRG (BIT(0) | BIT(1) | BIT(3))
|
| 676 | +#define SDCI_STATE_DAT_STATE_DAT_BUSY (BIT(2) | BIT(3))
|
| 677 | +#define SDCI_STATE_CMD_STATE_MASK (BIT(4) | BIT(5) | BIT(6))
|
| 678 | +#define SDCI_STATE_CMD_STATE_CMD_IDLE 0
|
| 679 | +#define SDCI_STATE_CMD_STATE_CMD_CMDO BIT(4)
|
| 680 | +#define SDCI_STATE_CMD_STATE_CMD_CRCO BIT(5)
|
| 681 | +#define SDCI_STATE_CMD_STATE_CMD_TOUT (BIT(4) | BIT(5))
|
| 682 | +#define SDCI_STATE_CMD_STATE_CMD_RESR BIT(6)
|
| 683 | +#define SDCI_STATE_CMD_STATE_CMD_INTV (BIT(4) | BIT(6))
|
| 684 | +
|
| 685 | +#define SDCI_STAC_CLR_CMDEND BIT(2)
|
| 686 | +#define SDCI_STAC_CLR_BIT_3 BIT(3)
|
| 687 | +#define SDCI_STAC_CLR_RESEND BIT(4)
|
| 688 | +#define SDCI_STAC_CLR_DATEND BIT(6)
|
| 689 | +#define SDCI_STAC_CLR_DAT_CRCEND BIT(7)
|
| 690 | +#define SDCI_STAC_CLR_CRC_STAEND BIT(8)
|
| 691 | +#define SDCI_STAC_CLR_RESTOUTE BIT(15)
|
| 692 | +#define SDCI_STAC_CLR_RESENDE BIT(16)
|
| 693 | +#define SDCI_STAC_CLR_RESINDE BIT(17)
|
| 694 | +#define SDCI_STAC_CLR_RESCRCE BIT(18)
|
| 695 | +#define SDCI_STAC_CLR_WR_DATCRCE BIT(22)
|
| 696 | +#define SDCI_STAC_CLR_RD_DATCRCE BIT(23)
|
| 697 | +#define SDCI_STAC_CLR_RD_DATENDE0 BIT(24)
|
| 698 | +#define SDCI_STAC_CLR_RD_DATENDE1 BIT(25)
|
| 699 | +#define SDCI_STAC_CLR_RD_DATENDE2 BIT(26)
|
| 700 | +#define SDCI_STAC_CLR_RD_DATENDE3 BIT(27)
|
| 701 | +#define SDCI_STAC_CLR_RD_DATENDE4 BIT(28)
|
| 702 | +#define SDCI_STAC_CLR_RD_DATENDE5 BIT(29)
|
| 703 | +#define SDCI_STAC_CLR_RD_DATENDE6 BIT(30)
|
| 704 | +#define SDCI_STAC_CLR_RD_DATENDE7 BIT(31)
|
| 705 | +
|
| 706 | +#define SDCI_DSTA_CMDRDY BIT(0)
|
| 707 | +#define SDCI_DSTA_CMDPRO BIT(1)
|
| 708 | +#define SDCI_DSTA_CMDEND BIT(2)
|
| 709 | +#define SDCI_DSTA_RESPRO BIT(3)
|
| 710 | +#define SDCI_DSTA_RESEND BIT(4)
|
| 711 | +#define SDCI_DSTA_DATPRO BIT(5)
|
| 712 | +#define SDCI_DSTA_DATEND BIT(6)
|
| 713 | +#define SDCI_DSTA_DAT_CRCEND BIT(7)
|
| 714 | +#define SDCI_DSTA_CRC_STAEND BIT(8)
|
| 715 | +#define SDCI_DSTA_DAT_BUSY BIT(9)
|
| 716 | +#define SDCI_DSTA_SDCLK_HOLD BIT(12)
|
| 717 | +#define SDCI_DSTA_DAT0_STATUS BIT(13)
|
| 718 | +#define SDCI_DSTA_WP_DECT_INPUT BIT(14)
|
| 719 | +#define SDCI_DSTA_RESTOUTE BIT(15)
|
| 720 | +#define SDCI_DSTA_RESENDE BIT(16)
|
| 721 | +#define SDCI_DSTA_RESINDE BIT(17)
|
| 722 | +#define SDCI_DSTA_RESCRCE BIT(18)
|
| 723 | +#define SDCI_DSTA_WR_CRC_STATUS_MASK BITRANGE(19, 21)
|
| 724 | +#define SDCI_DSTA_WR_CRC_STATUS_OK BIT(20)
|
| 725 | +#define SDCI_DSTA_WR_CRC_STATUS_TXERR (BIT(19) | BIT(21))
|
| 726 | +#define SDCI_DSTA_WR_CRC_STATUS_CARDERR (BIT(19) | BIT(20) | BIT(21))
|
| 727 | +#define SDCI_DSTA_WR_DATCRCE BIT(22)
|
| 728 | +#define SDCI_DSTA_RD_DATCRCE BIT(23)
|
| 729 | +#define SDCI_DSTA_RD_DATENDE0 BIT(24)
|
| 730 | +#define SDCI_DSTA_RD_DATENDE1 BIT(25)
|
| 731 | +#define SDCI_DSTA_RD_DATENDE2 BIT(26)
|
| 732 | +#define SDCI_DSTA_RD_DATENDE3 BIT(27)
|
| 733 | +#define SDCI_DSTA_RD_DATENDE4 BIT(28)
|
| 734 | +#define SDCI_DSTA_RD_DATENDE5 BIT(29)
|
| 735 | +#define SDCI_DSTA_RD_DATENDE6 BIT(30)
|
| 736 | +#define SDCI_DSTA_RD_DATENDE7 BIT(31)
|
| 737 | +
|
| 738 | +#define SDCI_FSTA_RX_FIFO_EMPTY BIT(0)
|
| 739 | +#define SDCI_FSTA_RX_FIFO_FULL BIT(1)
|
| 740 | +#define SDCI_FSTA_TX_FIFO_EMPTY BIT(2)
|
| 741 | +#define SDCI_FSTA_TX_FIFO_FULL BIT(3)
|
| 742 | +
|
| 743 | +#define SDCI_SDIO_CSR_SDIO_RW_EN BIT(0)
|
| 744 | +#define SDCI_SDIO_CSR_SDIO_INT_EN BIT(1)
|
| 745 | +#define SDCI_SDIO_CSR_SDIO_RW_REQ BIT(2)
|
| 746 | +#define SDCI_SDIO_CSR_SDIO_RW_STOP BIT(3)
|
| 747 | +#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MASK BIT(4)
|
| 748 | +#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MORE 0
|
| 749 | +#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_XACT BIT(4)
|
| 750 | +
|
| 751 | +#define SDCI_IRQ_DAT_DONE_INT BIT(0)
|
| 752 | +#define SDCI_IRQ_IOCARD_IRQ_INT BIT(1)
|
| 753 | +#define SDCI_IRQ_READ_WAIT_INT BIT(2)
|
| 754 | +
|
| 755 | +#define SDCI_IRQ_MASK_MASK_DAT_DONE_INT BIT(0)
|
| 756 | +#define SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT BIT(1)
|
| 757 | +#define SDCI_IRQ_MASK_MASK_READ_WAIT_INT BIT(2)
|
| 758 | +
|
| 759 | + |
576 | 760 | /////CLICKWHEEL///// |
577 | 761 | #define WHEEL00 (*((uint32_t volatile*)(0x3C200000))) |
578 | 762 | #define WHEEL04 (*((uint32_t volatile*)(0x3C200004))) |
— | — | @@ -605,6 +789,7 @@ |
606 | 790 | #define IRQ_DMAC1 17 |
607 | 791 | #define IRQ_WHEEL 23 |
608 | 792 | #define IRQ_ATA 29 |
| 793 | +#define IRQ_MMC 44 |
609 | 794 | |
610 | 795 | |
611 | 796 | #endif |
Index: emcore/trunk/target/ipodnano3g/interrupt.c |
— | — | @@ -94,7 +94,7 @@ |
95 | 95 | default_interrupt(INT_IRQ41);
|
96 | 96 | default_interrupt(INT_IRQ42);
|
97 | 97 | default_interrupt(INT_IRQ43);
|
98 | | -default_interrupt(INT_IRQ44);
|
| 98 | +default_interrupt(INT_MMC);
|
99 | 99 | default_interrupt(INT_IRQ45);
|
100 | 100 | default_interrupt(INT_IRQ46);
|
101 | 101 | default_interrupt(INT_IRQ47);
|
— | — | @@ -186,7 +186,7 @@ |
187 | 187 | INT_DMAC0,INT_DMAC1,INT_IRQ18,INT_USB_FUNC,INT_IRQ20,INT_IRQ21,INT_IRQ22,INT_WHEEL,
|
188 | 188 | INT_IRQ24,INT_IRQ25,INT_IRQ26,INT_IRQ27,INT_IRQ28,INT_ATA,INT_IRQ30,INT_IRQ31,
|
189 | 189 | INT_IRQ32,INT_IRQ33,INT_IRQ34,INT_IRQ35,INT_IRQ36,INT_IRQ37,INT_IRQ38,INT_IRQ39,
|
190 | | - INT_IRQ40,INT_IRQ41,INT_IRQ42,INT_IRQ43,INT_IRQ55,INT_IRQ56,INT_IRQ57,INT_IRQ58,
|
| 190 | + INT_IRQ40,INT_IRQ41,INT_IRQ42,INT_IRQ43,INT_MMC,INT_IRQ45,INT_IRQ46,INT_IRQ47,
|
191 | 191 | INT_IRQ48,INT_IRQ49,INT_IRQ50,INT_IRQ51,INT_IRQ52,INT_IRQ53,INT_IRQ54,INT_IRQ55,
|
192 | 192 | INT_IRQ56,INT_IRQ57,INT_IRQ58,INT_IRQ59,INT_IRQ60,INT_IRQ61,INT_IRQ62,INT_IRQ63
|
193 | 193 | };
|
— | — | @@ -238,6 +238,7 @@ |
239 | 239 | VIC0INTENABLE = 1 << IRQ_DMAC1;
|
240 | 240 | #ifdef TARGET_ipodclassic
|
241 | 241 | VIC0INTENABLE = 1 << IRQ_ATA;
|
| 242 | + VIC1INTENABLE = 1 << (IRQ_MMC - 32);
|
242 | 243 | #endif
|
243 | 244 | }
|
244 | 245 |
|
Index: emcore/trunk/target/ipodclassic/storage_ata.c |
— | — | @@ -24,6 +24,7 @@ |
25 | 25 | #include "storage.h"
|
26 | 26 | #include "storage_ata-target.h"
|
27 | 27 | #include "timer.h"
|
| 28 | +#include "constants/mmc.h"
|
28 | 29 | #include "../ipodnano3g/s5l8702.h"
|
29 | 30 |
|
30 | 31 |
|
— | — | @@ -32,8 +33,16 @@ |
33 | 34 | #endif
|
34 | 35 |
|
35 | 36 |
|
| 37 | +#define CEATA_POWERUP_TIMEOUT 30000000
|
| 38 | +#define CEATA_COMMAND_TIMEOUT 1000000
|
| 39 | +#define CEATA_DAT_NONBUSY_TIMEOUT 5000000
|
| 40 | +#define CEATA_MMC_RCA 1
|
| 41 | +
|
| 42 | +
|
36 | 43 | /** static, private data **/
|
| 44 | +static uint8_t ceata_taskfile[16] __attribute__((aligned(16)));
|
37 | 45 | uint16_t ata_identify_data[0x100];
|
| 46 | +bool ceata;
|
38 | 47 | bool ata_lba48;
|
39 | 48 | bool ata_dma;
|
40 | 49 | uint64_t ata_total_sectors;
|
— | — | @@ -47,7 +56,10 @@ |
48 | 57 | static bool ata_powered;
|
49 | 58 | static int ata_retries = ATA_RETRIES;
|
50 | 59 | static bool ata_error_srst = true;
|
| 60 | +static struct wakeup mmc_wakeup;
|
| 61 | +static struct wakeup mmc_comp_wakeup;
|
51 | 62 |
|
| 63 | +
|
52 | 64 | #ifdef ATA_HAVE_BBT
|
53 | 65 | #include "panic.h"
|
54 | 66 | uint16_t (*ata_bbt)[0x20];
|
— | — | @@ -150,18 +162,382 @@ |
151 | 163 | RET_ERR(2);
|
152 | 164 | }
|
153 | 165 |
|
| 166 | +int mmc_dsta_check_command_success(bool disable_crc)
|
| 167 | +{
|
| 168 | + int rc = 0;
|
| 169 | + uint32_t dsta = SDCI_DSTA;
|
| 170 | + if (dsta & SDCI_DSTA_RESTOUTE) rc |= 1;
|
| 171 | + if (dsta & SDCI_DSTA_RESENDE) rc |= 2;
|
| 172 | + if (dsta & SDCI_DSTA_RESINDE) rc |= 4;
|
| 173 | + if (!disable_crc)
|
| 174 | + if (dsta & SDCI_DSTA_RESCRCE)
|
| 175 | + rc |= 8;
|
| 176 | + if (rc) RET_ERR(rc);
|
| 177 | + return 0;
|
| 178 | +}
|
| 179 | +
|
| 180 | +bool mmc_send_command(uint32_t cmd, uint32_t arg, uint32_t* result, int timeout)
|
| 181 | +{
|
| 182 | + long starttime = USEC_TIMER;
|
| 183 | + while ((SDCI_STATE & SDCI_STATE_CMD_STATE_MASK) != SDCI_STATE_CMD_STATE_CMD_IDLE)
|
| 184 | + {
|
| 185 | + if (TIMEOUT_EXPIRED(starttime, timeout)) RET_ERR(0);
|
| 186 | + yield();
|
| 187 | + }
|
| 188 | + SDCI_STAC = SDCI_STAC_CLR_CMDEND | SDCI_STAC_CLR_BIT_3
|
| 189 | + | SDCI_STAC_CLR_RESEND | SDCI_STAC_CLR_DATEND
|
| 190 | + | SDCI_STAC_CLR_DAT_CRCEND | SDCI_STAC_CLR_CRC_STAEND
|
| 191 | + | SDCI_STAC_CLR_RESTOUTE | SDCI_STAC_CLR_RESENDE
|
| 192 | + | SDCI_STAC_CLR_RESINDE | SDCI_STAC_CLR_RESCRCE
|
| 193 | + | SDCI_STAC_CLR_WR_DATCRCE | SDCI_STAC_CLR_RD_DATCRCE
|
| 194 | + | SDCI_STAC_CLR_RD_DATENDE0 | SDCI_STAC_CLR_RD_DATENDE1
|
| 195 | + | SDCI_STAC_CLR_RD_DATENDE2 | SDCI_STAC_CLR_RD_DATENDE3
|
| 196 | + | SDCI_STAC_CLR_RD_DATENDE4 | SDCI_STAC_CLR_RD_DATENDE5
|
| 197 | + | SDCI_STAC_CLR_RD_DATENDE6 | SDCI_STAC_CLR_RD_DATENDE7;
|
| 198 | + SDCI_ARGU = arg;
|
| 199 | + SDCI_CMD = cmd;
|
| 200 | + if (!(SDCI_DSTA & SDCI_DSTA_CMDRDY)) RET_ERR(1);
|
| 201 | + SDCI_CMD = cmd | SDCI_CMD_CMDSTR;
|
| 202 | + sleep(1000);
|
| 203 | + while (!(SDCI_DSTA & SDCI_DSTA_CMDEND))
|
| 204 | + {
|
| 205 | + if (TIMEOUT_EXPIRED(starttime, timeout)) RET_ERR(2);
|
| 206 | + yield();
|
| 207 | + }
|
| 208 | + if ((cmd & SDCI_CMD_RES_TYPE_MASK) != SDCI_CMD_RES_TYPE_NONE)
|
| 209 | + {
|
| 210 | + while (!(SDCI_DSTA & SDCI_DSTA_RESEND))
|
| 211 | + {
|
| 212 | + if (TIMEOUT_EXPIRED(starttime, timeout)) RET_ERR(3);
|
| 213 | + yield();
|
| 214 | + }
|
| 215 | + if (cmd & SDCI_CMD_RES_BUSY)
|
| 216 | + while (SDCI_DSTA & SDCI_DSTA_DAT_BUSY)
|
| 217 | + {
|
| 218 | + if (TIMEOUT_EXPIRED(starttime, CEATA_DAT_NONBUSY_TIMEOUT)) RET_ERR(4);
|
| 219 | + yield();
|
| 220 | + }
|
| 221 | + }
|
| 222 | + bool nocrc = (cmd & SDCI_CMD_RES_SIZE_MASK) == SDCI_CMD_RES_SIZE_136;
|
| 223 | + PASS_RC(mmc_dsta_check_command_success(nocrc), 3, 5);
|
| 224 | + if (result) *result = SDCI_RESP0;
|
| 225 | + return 0;
|
| 226 | +}
|
| 227 | +
|
| 228 | +int mmc_get_card_status(uint32_t* result)
|
| 229 | +{
|
| 230 | + return mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SEND_STATUS)
|
| 231 | + | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
|
| 232 | + | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
| 233 | + MMC_CMD_SEND_STATUS_RCA(CEATA_MMC_RCA), result, CEATA_COMMAND_TIMEOUT);
|
| 234 | +}
|
| 235 | +
|
| 236 | +int mmc_init()
|
| 237 | +{
|
| 238 | + sleep(100000);
|
| 239 | + PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_GO_IDLE_STATE)
|
| 240 | + | SDCI_CMD_CMD_TYPE_BC | SDCI_CMD_RES_TYPE_NONE
|
| 241 | + | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NID,
|
| 242 | + 0, NULL, CEATA_COMMAND_TIMEOUT), 3, 0);
|
| 243 | + long startusec = USEC_TIMER;
|
| 244 | + uint32_t result;
|
| 245 | + do
|
| 246 | + {
|
| 247 | + if (TIMEOUT_EXPIRED(startusec, CEATA_POWERUP_TIMEOUT)) RET_ERR(1);
|
| 248 | + sleep(1000);
|
| 249 | + PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SEND_OP_COND)
|
| 250 | + | SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R3
|
| 251 | + | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NID,
|
| 252 | + MMC_CMD_SEND_OP_COND_OCR(MMC_OCR_270_360),
|
| 253 | + NULL, CEATA_COMMAND_TIMEOUT), 3, 2);
|
| 254 | + result = SDCI_RESP0;
|
| 255 | + }
|
| 256 | + while (!(result & MMC_OCR_POWER_UP_DONE));
|
| 257 | + PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_ALL_SEND_CID)
|
| 258 | + | SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R2
|
| 259 | + | SDCI_CMD_RES_SIZE_136 | SDCI_CMD_NCR_NID_NID,
|
| 260 | + 0, NULL, CEATA_COMMAND_TIMEOUT), 3, 3);
|
| 261 | + PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SET_RELATIVE_ADDR)
|
| 262 | + | SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R1
|
| 263 | + | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
| 264 | + MMC_CMD_SET_RELATIVE_ADDR_RCA(CEATA_MMC_RCA),
|
| 265 | + NULL, CEATA_COMMAND_TIMEOUT), 3, 4);
|
| 266 | + PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SELECT_CARD)
|
| 267 | + | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
|
| 268 | + | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
| 269 | + MMC_CMD_SELECT_CARD_RCA(CEATA_MMC_RCA),
|
| 270 | + NULL, CEATA_COMMAND_TIMEOUT), 3, 5);
|
| 271 | + PASS_RC(mmc_get_card_status(&result), 3, 6);
|
| 272 | + if ((result & MMC_STATUS_CURRENT_STATE_MASK) != MMC_STATUS_CURRENT_STATE_TRAN) RET_ERR(7);
|
| 273 | + return 0;
|
| 274 | +}
|
| 275 | +
|
| 276 | +int mmc_fastio_write(uint32_t addr, uint32_t data)
|
| 277 | +{
|
| 278 | + return mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_FAST_IO)
|
| 279 | + | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R4
|
| 280 | + | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
| 281 | + MMC_CMD_FAST_IO_RCA(CEATA_MMC_RCA) | MMC_CMD_FAST_IO_DIRECTION_WRITE
|
| 282 | + | MMC_CMD_FAST_IO_ADDRESS(addr) | MMC_CMD_FAST_IO_DATA(data),
|
| 283 | + NULL, CEATA_COMMAND_TIMEOUT);
|
| 284 | +}
|
| 285 | +
|
| 286 | +int mmc_fastio_read(uint32_t addr, uint32_t* data)
|
| 287 | +{
|
| 288 | + return mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_FAST_IO)
|
| 289 | + | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R4
|
| 290 | + | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
| 291 | + MMC_CMD_FAST_IO_RCA(CEATA_MMC_RCA) | MMC_CMD_FAST_IO_DIRECTION_READ
|
| 292 | + | MMC_CMD_FAST_IO_ADDRESS(addr), data, CEATA_COMMAND_TIMEOUT);
|
| 293 | +}
|
| 294 | +
|
| 295 | +int ceata_soft_reset()
|
| 296 | +{
|
| 297 | + PASS_RC(mmc_fastio_write(6, 4), 2, 0);
|
| 298 | + sleep(1000);
|
| 299 | + PASS_RC(mmc_fastio_write(6, 0), 2, 1);
|
| 300 | + sleep(10000);
|
| 301 | + long startusec = USEC_TIMER;
|
| 302 | + uint32_t status;
|
| 303 | + do
|
| 304 | + {
|
| 305 | + PASS_RC(mmc_fastio_read(0xf, &status), 2, 2);
|
| 306 | + if (TIMEOUT_EXPIRED(startusec, CEATA_POWERUP_TIMEOUT)) RET_ERR(3);
|
| 307 | + sleep(1000);
|
| 308 | + }
|
| 309 | + while (status & 0x80);
|
| 310 | + return 0;
|
| 311 | +}
|
| 312 | +
|
| 313 | +int mmc_dsta_check_data_success()
|
| 314 | +{
|
| 315 | + int rc = 0;
|
| 316 | + uint32_t dsta = SDCI_DSTA;
|
| 317 | + if (dsta & (SDCI_DSTA_WR_DATCRCE | SDCI_DSTA_RD_DATCRCE))
|
| 318 | + {
|
| 319 | + if (dsta & SDCI_DSTA_WR_DATCRCE) rc |= 1;
|
| 320 | + if (dsta & SDCI_DSTA_RD_DATCRCE) rc |= 2;
|
| 321 | + if ((dsta & SDCI_DSTA_WR_CRC_STATUS_MASK) == SDCI_DSTA_WR_CRC_STATUS_TXERR) rc |= 4;
|
| 322 | + else if ((dsta & SDCI_DSTA_WR_CRC_STATUS_MASK) == SDCI_DSTA_WR_CRC_STATUS_CARDERR) rc |= 8;
|
| 323 | + }
|
| 324 | + if (dsta & (SDCI_DSTA_RD_DATENDE0 | SDCI_DSTA_RD_DATENDE1 | SDCI_DSTA_RD_DATENDE2
|
| 325 | + | SDCI_DSTA_RD_DATENDE3 | SDCI_DSTA_RD_DATENDE4 | SDCI_DSTA_RD_DATENDE5
|
| 326 | + | SDCI_DSTA_RD_DATENDE6 | SDCI_DSTA_RD_DATENDE7))
|
| 327 | + rc |= 16;
|
| 328 | + if (rc) RET_ERR(rc);
|
| 329 | + return 0;
|
| 330 | +}
|
| 331 | +
|
| 332 | +void mmc_discard_irq()
|
| 333 | +{
|
| 334 | + SDCI_IRQ = SDCI_IRQ_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT
|
| 335 | + | SDCI_IRQ_MASK_MASK_READ_WAIT_INT;
|
| 336 | + wakeup_wait(&mmc_wakeup, TIMEOUT_NONE);
|
| 337 | +}
|
| 338 | +
|
| 339 | +int ceata_read_multiple_register(uint32_t addr, void* dest, uint32_t size)
|
| 340 | +{
|
| 341 | + if (size > 0x10) RET_ERR(0);
|
| 342 | + mmc_discard_irq();
|
| 343 | + SDCI_DMASIZE = size;
|
| 344 | + SDCI_DMACOUNT = 1;
|
| 345 | + SDCI_DMAADDR = dest;
|
| 346 | + SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
|
| 347 | + PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_REG)
|
| 348 | + | SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_RES_TYPE_R1
|
| 349 | + | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
| 350 | + MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_READ
|
| 351 | + | MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(addr & 0xfc)
|
| 352 | + | MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(size & 0xfc),
|
| 353 | + NULL, CEATA_COMMAND_TIMEOUT), 2, 1);
|
| 354 | + long startusec = USEC_TIMER;
|
| 355 | + if (wakeup_wait(&mmc_wakeup, CEATA_COMMAND_TIMEOUT) == THREAD_TIMEOUT) RET_ERR(2);
|
| 356 | + invalidate_dcache();
|
| 357 | + PASS_RC(mmc_dsta_check_data_success(), 2, 3);
|
| 358 | + return 0;
|
| 359 | +}
|
| 360 | +
|
| 361 | +int ceata_write_multiple_register(uint32_t addr, void* dest, uint32_t size)
|
| 362 | +{
|
| 363 | + int i;
|
| 364 | + if (size > 0x10) RET_ERR(0);
|
| 365 | + mmc_discard_irq();
|
| 366 | + SDCI_DMASIZE = size;
|
| 367 | + SDCI_DMACOUNT = 0;
|
| 368 | + SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
|
| 369 | + PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_REG)
|
| 370 | + | SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_CMD_RD_WR
|
| 371 | + | SDCI_CMD_RES_BUSY | SDCI_CMD_RES_TYPE_R1
|
| 372 | + | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
| 373 | + MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_WRITE
|
| 374 | + | MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(addr & 0xfc)
|
| 375 | + | MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(size & 0xfc),
|
| 376 | + NULL, CEATA_COMMAND_TIMEOUT), 3, 1);
|
| 377 | + SDCI_DCTRL = SDCI_DCTRL_TRCONT_TX;
|
| 378 | + for (i = 0; i < size / 4; i++) SDCI_DATA = ((uint32_t*)dest)[i];
|
| 379 | + long startusec = USEC_TIMER;
|
| 380 | + if (wakeup_wait(&mmc_wakeup, CEATA_COMMAND_TIMEOUT) == THREAD_TIMEOUT) RET_ERR(2);
|
| 381 | + while ((SDCI_STATE & SDCI_STATE_DAT_STATE_MASK) != SDCI_STATE_DAT_STATE_IDLE)
|
| 382 | + {
|
| 383 | + if (TIMEOUT_EXPIRED(startusec, CEATA_COMMAND_TIMEOUT)) RET_ERR(3);
|
| 384 | + yield();
|
| 385 | + }
|
| 386 | + PASS_RC(mmc_dsta_check_data_success(), 3, 4);
|
| 387 | + return 0;
|
| 388 | +}
|
| 389 | +
|
| 390 | +int ceata_init(int buswidth)
|
| 391 | +{
|
| 392 | + uint32_t result;
|
| 393 | + PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SWITCH) | SDCI_CMD_RES_BUSY
|
| 394 | + | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
|
| 395 | + | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
| 396 | + MMC_CMD_SWITCH_ACCESS_WRITE_BYTE
|
| 397 | + | MMC_CMD_SWITCH_INDEX(MMC_CMD_SWITCH_FIELD_HS_TIMING)
|
| 398 | + | MMC_CMD_SWITCH_VALUE(MMC_CMD_SWITCH_FIELD_HS_TIMING_HIGH_SPEED),
|
| 399 | + &result, CEATA_COMMAND_TIMEOUT), 3, 0);
|
| 400 | + if (result & MMC_STATUS_SWITCH_ERROR) RET_ERR(1);
|
| 401 | + if (buswidth > 1)
|
| 402 | + {
|
| 403 | + int setting;
|
| 404 | + if (buswidth == 4) setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_4BIT;
|
| 405 | + else if (buswidth == 8) setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_8BIT;
|
| 406 | + else setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_1BIT;
|
| 407 | + PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SWITCH) | SDCI_CMD_RES_BUSY
|
| 408 | + | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
|
| 409 | + | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
| 410 | + MMC_CMD_SWITCH_ACCESS_WRITE_BYTE
|
| 411 | + | MMC_CMD_SWITCH_INDEX(MMC_CMD_SWITCH_FIELD_BUS_WIDTH)
|
| 412 | + | MMC_CMD_SWITCH_VALUE(setting),
|
| 413 | + &result, CEATA_COMMAND_TIMEOUT), 3, 2);
|
| 414 | + if (result & MMC_STATUS_SWITCH_ERROR) RET_ERR(3);
|
| 415 | + if (buswidth == 4)
|
| 416 | + SDCI_CTRL = (SDCI_CTRL & ~SDCI_CTRL_BUS_WIDTH_MASK) | SDCI_CTRL_BUS_WIDTH_4BIT;
|
| 417 | + else if (buswidth == 8)
|
| 418 | + SDCI_CTRL = (SDCI_CTRL & ~SDCI_CTRL_BUS_WIDTH_MASK) | SDCI_CTRL_BUS_WIDTH_8BIT;
|
| 419 | + }
|
| 420 | + PASS_RC(ceata_soft_reset(), 3, 4);
|
| 421 | + PASS_RC(ceata_read_multiple_register(0, ceata_taskfile, 0x10), 3, 5);
|
| 422 | + if (ceata_taskfile[0xc] != 0xce || ceata_taskfile[0xd] != 0xaa) RET_ERR(6);
|
| 423 | + PASS_RC(mmc_fastio_write(6, 0), 3, 7);
|
| 424 | + return 0;
|
| 425 | +}
|
| 426 | +
|
| 427 | +int ceata_check_error()
|
| 428 | +{
|
| 429 | + uint32_t status, error;
|
| 430 | + PASS_RC(mmc_fastio_read(0xf, &status), 2, 0);
|
| 431 | + if (status & 1)
|
| 432 | + {
|
| 433 | + PASS_RC(mmc_fastio_read(0x9, &error), 2, 1);
|
| 434 | + RET_ERR((error << 2) | 2);
|
| 435 | + }
|
| 436 | + return 0;
|
| 437 | +}
|
| 438 | +
|
| 439 | +int ceata_wait_idle()
|
| 440 | +{
|
| 441 | + long startusec = USEC_TIMER;
|
| 442 | + while (true)
|
| 443 | + {
|
| 444 | + uint32_t status;
|
| 445 | + PASS_RC(mmc_fastio_read(0xf, &status), 1, 0);
|
| 446 | + if (!(status & 0x88)) return 0;
|
| 447 | + if (TIMEOUT_EXPIRED(startusec, CEATA_DAT_NONBUSY_TIMEOUT)) RET_ERR(1);
|
| 448 | + sleep(50000);
|
| 449 | + }
|
| 450 | +}
|
| 451 | +
|
| 452 | +int ceata_cancel_command()
|
| 453 | +{
|
| 454 | + *((uint32_t volatile*)0x3cf00200) = 0x9000e;
|
| 455 | + sleep(1);
|
| 456 | + *((uint32_t volatile*)0x3cf00200) = 0x9000f;
|
| 457 | + sleep(1);
|
| 458 | + *((uint32_t volatile*)0x3cf00200) = 0x90003;
|
| 459 | + sleep(1);
|
| 460 | + PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_STOP_TRANSMISSION)
|
| 461 | + | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1 | SDCI_CMD_RES_BUSY
|
| 462 | + | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
| 463 | + 0, NULL, CEATA_COMMAND_TIMEOUT), 1, 0);
|
| 464 | + PASS_RC(ceata_wait_idle(), 1, 1);
|
| 465 | + return 0;
|
| 466 | +}
|
| 467 | +
|
| 468 | +int ceata_rw_multiple_block(bool write, void* buf, uint32_t count, long timeout)
|
| 469 | +{
|
| 470 | + mmc_discard_irq();
|
| 471 | + uint32_t responsetype;
|
| 472 | + uint32_t cmdtype;
|
| 473 | + uint32_t direction;
|
| 474 | + if (write)
|
| 475 | + {
|
| 476 | + clean_dcache();
|
| 477 | + cmdtype = SDCI_CMD_CMD_TYPE_ADTC | SDCI_CMD_CMD_RD_WR;
|
| 478 | + responsetype = SDCI_CMD_RES_TYPE_R1 | SDCI_CMD_RES_BUSY;
|
| 479 | + direction = MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_WRITE;
|
| 480 | + }
|
| 481 | + else
|
| 482 | + {
|
| 483 | + cmdtype = SDCI_CMD_CMD_TYPE_ADTC;
|
| 484 | + responsetype = SDCI_CMD_RES_TYPE_R1;
|
| 485 | + direction = MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_READ;
|
| 486 | + }
|
| 487 | + SDCI_DMASIZE = 0x200;
|
| 488 | + SDCI_DMAADDR = buf;
|
| 489 | + SDCI_DMACOUNT = count;
|
| 490 | + SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
|
| 491 | + PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_BLOCK)
|
| 492 | + | SDCI_CMD_CMD_TYPE_ADTC | cmdtype | responsetype
|
| 493 | + | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
|
| 494 | + direction | MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT(count),
|
| 495 | + NULL, CEATA_COMMAND_TIMEOUT), 4, 0);
|
| 496 | + if (write) SDCI_DCTRL = SDCI_DCTRL_TRCONT_TX;
|
| 497 | + if (wakeup_wait(&mmc_wakeup, timeout) == THREAD_TIMEOUT)
|
| 498 | + {
|
| 499 | + PASS_RC(ceata_cancel_command(), 4, 1);
|
| 500 | + RET_ERR(2);
|
| 501 | + }
|
| 502 | + if (!write) invalidate_dcache();
|
| 503 | + PASS_RC(mmc_dsta_check_data_success(), 4, 3);
|
| 504 | + if (wakeup_wait(&mmc_comp_wakeup, timeout) == THREAD_TIMEOUT)
|
| 505 | + {
|
| 506 | + PASS_RC(ceata_cancel_command(), 4, 4);
|
| 507 | + RET_ERR(4);
|
| 508 | + }
|
| 509 | + PASS_RC(ceata_check_error(), 4, 5);
|
| 510 | + return 0;
|
| 511 | +}
|
| 512 | +
|
154 | 513 | int ata_identify(uint16_t* buf)
|
155 | 514 | {
|
156 | 515 | int i;
|
157 | | - PASS_RC(ata_wait_for_not_bsy(10000000), 1, 0);
|
158 | | - ata_write_cbr(&ATA_PIO_DVR, 0);
|
159 | | - ata_write_cbr(&ATA_PIO_CSD, 0xec);
|
160 | | - PASS_RC(ata_wait_for_start_of_transfer(10000000), 1, 1);
|
161 | | - for (i = 0; i < 0x100; i++)
|
| 516 | + if (ceata)
|
162 | 517 | {
|
163 | | - uint16_t word = ata_read_cbr(&ATA_PIO_DTR);
|
164 | | - buf[i] = (word >> 8) | (word << 8);
|
| 518 | + memset(ceata_taskfile, 0, 16);
|
| 519 | + ceata_taskfile[0xf] = 0xec;
|
| 520 | + PASS_RC(ceata_wait_idle(), 2, 0);
|
| 521 | + PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
|
| 522 | + PASS_RC(ceata_rw_multiple_block(false, buf, 1, CEATA_COMMAND_TIMEOUT), 2, 2);
|
| 523 | + for (i = 0; i < 0x100; i++)
|
| 524 | + {
|
| 525 | + uint16_t word = buf[i];
|
| 526 | + buf[i] = (word >> 8) | (word << 8);
|
| 527 | + }
|
165 | 528 | }
|
| 529 | + else
|
| 530 | + {
|
| 531 | + PASS_RC(ata_wait_for_not_bsy(10000000), 1, 0);
|
| 532 | + ata_write_cbr(&ATA_PIO_DVR, 0);
|
| 533 | + ata_write_cbr(&ATA_PIO_CSD, 0xec);
|
| 534 | + PASS_RC(ata_wait_for_start_of_transfer(10000000), 1, 1);
|
| 535 | + for (i = 0; i < 0x100; i++)
|
| 536 | + {
|
| 537 | + uint16_t word = ata_read_cbr(&ATA_PIO_DTR);
|
| 538 | + buf[i] = (word >> 8) | (word << 8);
|
| 539 | + }
|
| 540 | + }
|
| 541 | + return 0;
|
166 | 542 | }
|
167 | 543 |
|
168 | 544 | void ata_set_active(void)
|
— | — | @@ -195,89 +571,110 @@ |
196 | 572 | ata_set_active();
|
197 | 573 | if (ata_powered) return 0;
|
198 | 574 | i2c_sendbyte(0, 0xe6, 0x1b, 1);
|
199 | | - clockgate_enable(5, true);
|
200 | | - ATA_CFG = BIT(0);
|
201 | | - sleep(1000);
|
202 | | - ATA_CFG = 0;
|
203 | | - sleep(6000);
|
204 | | - ATA_SWRST = BIT(0);
|
205 | | - sleep(500);
|
206 | | - ATA_SWRST = 0;
|
207 | | - sleep(90000);
|
208 | | - ATA_CONTROL = BIT(0);
|
209 | | - sleep(200000);
|
210 | | - ATA_PIO_TIME = 0x191f7;
|
211 | | - ATA_PIO_LHR = 0;
|
212 | | - while (!(ATA_PIO_READY & BIT(1))) sleep(100);
|
213 | | - PASS_RC(ata_identify(ata_identify_data), 2, 0);
|
214 | | - uint32_t piotime = 0x11f3;
|
215 | | - uint32_t mdmatime = 0x1c175;
|
216 | | - uint32_t udmatime = 0x5071152;
|
217 | | - uint32_t param = 0;
|
218 | | - ata_dma_flags = 0;
|
219 | | - ata_lba48 = ata_identify_data[83] & BIT(10) ? true : false;
|
220 | | - if (ata_lba48)
|
221 | | - ata_total_sectors = ata_identify_data[100]
|
222 | | - | (((uint64_t)ata_identify_data[101]) << 16)
|
223 | | - | (((uint64_t)ata_identify_data[102]) << 32)
|
224 | | - | (((uint64_t)ata_identify_data[103]) << 48);
|
225 | | - else ata_total_sectors = ata_identify_data[60] | (((uint32_t)ata_identify_data[61]) << 16);
|
226 | | - ata_total_sectors >>= 3;
|
227 | | - if (ata_identify_data[53] & BIT(1))
|
| 575 | + if (ceata)
|
228 | 576 | {
|
229 | | - if (ata_identify_data[64] & BIT(1)) piotime = 0x2072;
|
230 | | - else if (ata_identify_data[64] & BIT(0)) piotime = 0x7083;
|
| 577 | + clockgate_enable(9, true);
|
| 578 | + SDCI_RESET = 0xa5;
|
| 579 | + sleep(1000);
|
| 580 | + *((uint32_t volatile*)0x3cf00380) = 0;
|
| 581 | + *((uint32_t volatile*)0x3cf0010c) = 0xff;
|
| 582 | + SDCI_CTRL = SDCI_CTRL_SDCIEN | SDCI_CTRL_CLK_SEL_SDCLK
|
| 583 | + | SDCI_CTRL_BIT_8 | SDCI_CTRL_BIT_14;
|
| 584 | + SDCI_CDIV = SDCI_CDIV_CLKDIV(260);
|
| 585 | + *((uint32_t volatile*)0x3cf00200) = 0xb000f;
|
| 586 | + SDCI_IRQ_MASK = SDCI_IRQ_MASK_MASK_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT;
|
| 587 | + PASS_RC(mmc_init(), 2, 0);
|
| 588 | + SDCI_CDIV = SDCI_CDIV_CLKDIV(4);
|
| 589 | + sleep(10000);
|
| 590 | + PASS_RC(ceata_init(8), 2, 1);
|
| 591 | + PASS_RC(ata_identify(ata_identify_data), 2, 2);
|
231 | 592 | }
|
232 | | - if (ata_identify_data[63] & BIT(2))
|
| 593 | + else
|
233 | 594 | {
|
234 | | - mdmatime = 0x5072;
|
235 | | - param = 0x22;
|
236 | | - }
|
237 | | - else if (ata_identify_data[63] & BIT(1))
|
238 | | - {
|
239 | | - mdmatime = 0x7083;
|
240 | | - param = 0x21;
|
241 | | - }
|
242 | | - if (ata_identify_data[63] & BITRANGE(0, 2))
|
243 | | - {
|
244 | | - ata_dma_flags = BIT(3) | BIT(10);
|
245 | | - param |= 0x20;
|
246 | | - }
|
247 | | - if (ata_identify_data[53] & BIT(2))
|
248 | | - {
|
249 | | - if (ata_identify_data[88] & BIT(4))
|
| 595 | + clockgate_enable(5, true);
|
| 596 | + ATA_CFG = BIT(0);
|
| 597 | + sleep(1000);
|
| 598 | + ATA_CFG = 0;
|
| 599 | + sleep(6000);
|
| 600 | + ATA_SWRST = BIT(0);
|
| 601 | + sleep(500);
|
| 602 | + ATA_SWRST = 0;
|
| 603 | + sleep(90000);
|
| 604 | + ATA_CONTROL = BIT(0);
|
| 605 | + sleep(200000);
|
| 606 | + ATA_PIO_TIME = 0x191f7;
|
| 607 | + ATA_PIO_LHR = 0;
|
| 608 | + while (!(ATA_PIO_READY & BIT(1))) sleep(100);
|
| 609 | + PASS_RC(ata_identify(ata_identify_data), 2, 0);
|
| 610 | + uint32_t piotime = 0x11f3;
|
| 611 | + uint32_t mdmatime = 0x1c175;
|
| 612 | + uint32_t udmatime = 0x5071152;
|
| 613 | + uint32_t param = 0;
|
| 614 | + ata_dma_flags = 0;
|
| 615 | + ata_lba48 = ata_identify_data[83] & BIT(10) ? true : false;
|
| 616 | + if (ata_identify_data[53] & BIT(1))
|
250 | 617 | {
|
251 | | - udmatime = 0x2010a52;
|
252 | | - param = 0x44;
|
| 618 | + if (ata_identify_data[64] & BIT(1)) piotime = 0x2072;
|
| 619 | + else if (ata_identify_data[64] & BIT(0)) piotime = 0x7083;
|
253 | 620 | }
|
254 | | - else if (ata_identify_data[88] & BIT(3))
|
| 621 | + if (ata_identify_data[63] & BIT(2))
|
255 | 622 | {
|
256 | | - udmatime = 0x2020a52;
|
257 | | - param = 0x43;
|
| 623 | + mdmatime = 0x5072;
|
| 624 | + param = 0x22;
|
258 | 625 | }
|
259 | | - else if (ata_identify_data[88] & BIT(2))
|
| 626 | + else if (ata_identify_data[63] & BIT(1))
|
260 | 627 | {
|
261 | | - udmatime = 0x3030a52;
|
262 | | - param = 0x42;
|
| 628 | + mdmatime = 0x7083;
|
| 629 | + param = 0x21;
|
263 | 630 | }
|
264 | | - else if (ata_identify_data[88] & BIT(1))
|
| 631 | + if (ata_identify_data[63] & BITRANGE(0, 2))
|
265 | 632 | {
|
266 | | - udmatime = 0x3050a52;
|
267 | | - param = 0x41;
|
| 633 | + ata_dma_flags = BIT(3) | BIT(10);
|
| 634 | + param |= 0x20;
|
268 | 635 | }
|
269 | | - if (ata_identify_data[88] & BITRANGE(0, 4))
|
| 636 | + if (ata_identify_data[53] & BIT(2))
|
270 | 637 | {
|
271 | | - ata_dma_flags = BIT(2) | BIT(3) | BIT(9) | BIT(10);
|
272 | | - param |= 0x40;
|
| 638 | + if (ata_identify_data[88] & BIT(4))
|
| 639 | + {
|
| 640 | + udmatime = 0x2010a52;
|
| 641 | + param = 0x44;
|
| 642 | + }
|
| 643 | + else if (ata_identify_data[88] & BIT(3))
|
| 644 | + {
|
| 645 | + udmatime = 0x2020a52;
|
| 646 | + param = 0x43;
|
| 647 | + }
|
| 648 | + else if (ata_identify_data[88] & BIT(2))
|
| 649 | + {
|
| 650 | + udmatime = 0x3030a52;
|
| 651 | + param = 0x42;
|
| 652 | + }
|
| 653 | + else if (ata_identify_data[88] & BIT(1))
|
| 654 | + {
|
| 655 | + udmatime = 0x3050a52;
|
| 656 | + param = 0x41;
|
| 657 | + }
|
| 658 | + if (ata_identify_data[88] & BITRANGE(0, 4))
|
| 659 | + {
|
| 660 | + ata_dma_flags = BIT(2) | BIT(3) | BIT(9) | BIT(10);
|
| 661 | + param |= 0x40;
|
| 662 | + }
|
273 | 663 | }
|
| 664 | + ata_dma = param ? true : false;
|
| 665 | + PASS_RC(ata_set_feature(0xef, param), 2, 1);
|
| 666 | + if (ata_identify_data[82] & BIT(5)) PASS_RC(ata_set_feature(0x02, 0), 2, 2);
|
| 667 | + if (ata_identify_data[82] & BIT(6)) PASS_RC(ata_set_feature(0x55, 0), 2, 3);
|
| 668 | + ATA_PIO_TIME = piotime;
|
| 669 | + ATA_MDMA_TIME = mdmatime;
|
| 670 | + ATA_UDMA_TIME = udmatime;
|
274 | 671 | }
|
275 | | - ata_dma = param ? true : false;
|
276 | | - PASS_RC(ata_set_feature(0xef, param), 2, 1);
|
277 | | - if (ata_identify_data[82] & BIT(5)) PASS_RC(ata_set_feature(0x02, 0), 2, 2);
|
278 | | - if (ata_identify_data[82] & BIT(6)) PASS_RC(ata_set_feature(0x55, 0), 2, 3);
|
279 | | - ATA_PIO_TIME = piotime;
|
280 | | - ATA_MDMA_TIME = mdmatime;
|
281 | | - ATA_UDMA_TIME = udmatime;
|
| 672 | + if (ata_lba48)
|
| 673 | + ata_total_sectors = ata_identify_data[100]
|
| 674 | + | (((uint64_t)ata_identify_data[101]) << 16)
|
| 675 | + | (((uint64_t)ata_identify_data[102]) << 32)
|
| 676 | + | (((uint64_t)ata_identify_data[103]) << 48);
|
| 677 | + else ata_total_sectors = ata_identify_data[60] | (((uint32_t)ata_identify_data[61]) << 16);
|
| 678 | + ata_total_sectors >>= 3;
|
282 | 679 | ata_powered = true;
|
283 | 680 | ata_set_active();
|
284 | 681 | return 0;
|
— | — | @@ -287,93 +684,125 @@ |
288 | 685 | {
|
289 | 686 | if (!ata_powered) return;
|
290 | 687 | ata_powered = false;
|
291 | | - ata_wait_for_rdy(1000000);
|
292 | | - ata_write_cbr(&ATA_PIO_DVR, 0);
|
293 | | - ata_write_cbr(&ATA_PIO_CSD, 0xe0);
|
294 | | - ata_wait_for_rdy(1000000);
|
295 | | - sleep(30000);
|
296 | | - ATA_CONTROL = 0;
|
297 | | - while (!(ATA_CONTROL & BIT(1))) yield();
|
298 | | - clockgate_enable(5, false);
|
| 688 | + if (ceata)
|
| 689 | + {
|
| 690 | + memset(ceata_taskfile, 0, 16);
|
| 691 | + ceata_taskfile[0xf] = 0xe0;
|
| 692 | + ceata_wait_idle();
|
| 693 | + ceata_write_multiple_register(0, ceata_taskfile, 16);
|
| 694 | + wakeup_wait(&mmc_comp_wakeup, CEATA_COMMAND_TIMEOUT);
|
| 695 | + sleep(30000);
|
| 696 | + clockgate_enable(9, false);
|
| 697 | + }
|
| 698 | + else
|
| 699 | + {
|
| 700 | + ata_wait_for_rdy(1000000);
|
| 701 | + ata_write_cbr(&ATA_PIO_DVR, 0);
|
| 702 | + ata_write_cbr(&ATA_PIO_CSD, 0xe0);
|
| 703 | + ata_wait_for_rdy(1000000);
|
| 704 | + sleep(30000);
|
| 705 | + ATA_CONTROL = 0;
|
| 706 | + while (!(ATA_CONTROL & BIT(1))) yield();
|
| 707 | + clockgate_enable(5, false);
|
| 708 | + }
|
299 | 709 | i2c_sendbyte(0, 0xe6, 0x1b, 0);
|
300 | 710 | }
|
301 | 711 |
|
302 | 712 | int ata_rw_chunk(uint64_t sector, uint32_t cnt, void* buffer, bool write)
|
303 | 713 | {
|
304 | | - PASS_RC(ata_wait_for_rdy(100000), 2, 0);
|
305 | | - ata_write_cbr(&ATA_PIO_DVR, 0);
|
306 | | - if (ata_lba48)
|
| 714 | + if (ceata)
|
307 | 715 | {
|
308 | | - ata_write_cbr(&ATA_PIO_SCR, cnt >> 5);
|
309 | | - ata_write_cbr(&ATA_PIO_SCR, (cnt << 3) & 0xff);
|
310 | | - ata_write_cbr(&ATA_PIO_LHR, (sector >> 37) & 0xff);
|
311 | | - ata_write_cbr(&ATA_PIO_LMR, (sector >> 29) & 0xff);
|
312 | | - ata_write_cbr(&ATA_PIO_LLR, (sector >> 21) & 0xff);
|
313 | | - ata_write_cbr(&ATA_PIO_LHR, (sector >> 13) & 0xff);
|
314 | | - ata_write_cbr(&ATA_PIO_LMR, (sector >> 5) & 0xff);
|
315 | | - ata_write_cbr(&ATA_PIO_LLR, (sector << 3) & 0xff);
|
316 | | - ata_write_cbr(&ATA_PIO_DVR, BIT(6));
|
317 | | - if (write) ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0x35 : 0x39);
|
318 | | - else ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0x25 : 0x29);
|
| 716 | + memset(ceata_taskfile, 0, 16);
|
| 717 | + ceata_taskfile[0x2] = cnt >> 5;
|
| 718 | + ceata_taskfile[0x3] = sector >> 21;
|
| 719 | + ceata_taskfile[0x4] = sector >> 29;
|
| 720 | + ceata_taskfile[0x5] = sector >> 37;
|
| 721 | + ceata_taskfile[0xa] = cnt << 3;
|
| 722 | + ceata_taskfile[0xb] = sector << 3;
|
| 723 | + ceata_taskfile[0xc] = sector >> 5;
|
| 724 | + ceata_taskfile[0xd] = sector >> 13;
|
| 725 | + ceata_taskfile[0xf] = write ? 0x35 : 0x25;
|
| 726 | + PASS_RC(ceata_wait_idle(), 2, 0);
|
| 727 | + PASS_RC(ceata_write_multiple_register(0, ceata_taskfile, 16), 2, 1);
|
| 728 | + PASS_RC(ceata_rw_multiple_block(write, buffer, cnt, CEATA_COMMAND_TIMEOUT), 2, 2);
|
319 | 729 | }
|
320 | 730 | else
|
321 | 731 | {
|
322 | | - ata_write_cbr(&ATA_PIO_SCR, (cnt << 3) & 0xff);
|
323 | | - ata_write_cbr(&ATA_PIO_LHR, (sector >> 13) & 0xff);
|
324 | | - ata_write_cbr(&ATA_PIO_LMR, (sector >> 5) & 0xff);
|
325 | | - ata_write_cbr(&ATA_PIO_LLR, (sector << 3) & 0xff);
|
326 | | - ata_write_cbr(&ATA_PIO_DVR, BIT(6) | ((sector >> 21) & 0xf));
|
327 | | - if (write) ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0xca : 0x30);
|
328 | | - else ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0xc8 : 0xc4);
|
329 | | - }
|
330 | | - if (ata_dma)
|
331 | | - {
|
332 | | - PASS_RC(ata_wait_for_start_of_transfer(500000), 2, 1);
|
333 | | - if (write)
|
| 732 | + PASS_RC(ata_wait_for_rdy(100000), 2, 0);
|
| 733 | + ata_write_cbr(&ATA_PIO_DVR, 0);
|
| 734 | + if (ata_lba48)
|
334 | 735 | {
|
335 | | - ATA_SBUF_START = buffer;
|
336 | | - ATA_SBUF_SIZE = SECTOR_SIZE * cnt;
|
337 | | - ATA_CFG |= BIT(4);
|
| 736 | + ata_write_cbr(&ATA_PIO_SCR, cnt >> 5);
|
| 737 | + ata_write_cbr(&ATA_PIO_SCR, (cnt << 3) & 0xff);
|
| 738 | + ata_write_cbr(&ATA_PIO_LHR, (sector >> 37) & 0xff);
|
| 739 | + ata_write_cbr(&ATA_PIO_LMR, (sector >> 29) & 0xff);
|
| 740 | + ata_write_cbr(&ATA_PIO_LLR, (sector >> 21) & 0xff);
|
| 741 | + ata_write_cbr(&ATA_PIO_LHR, (sector >> 13) & 0xff);
|
| 742 | + ata_write_cbr(&ATA_PIO_LMR, (sector >> 5) & 0xff);
|
| 743 | + ata_write_cbr(&ATA_PIO_LLR, (sector << 3) & 0xff);
|
| 744 | + ata_write_cbr(&ATA_PIO_DVR, BIT(6));
|
| 745 | + if (write) ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0x35 : 0x39);
|
| 746 | + else ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0x25 : 0x29);
|
338 | 747 | }
|
339 | 748 | else
|
340 | 749 | {
|
341 | | - ATA_TBUF_START = buffer;
|
342 | | - ATA_TBUF_SIZE = SECTOR_SIZE * cnt;
|
343 | | - ATA_CFG &= ~BIT(4);
|
| 750 | + ata_write_cbr(&ATA_PIO_SCR, (cnt << 3) & 0xff);
|
| 751 | + ata_write_cbr(&ATA_PIO_LHR, (sector >> 13) & 0xff);
|
| 752 | + ata_write_cbr(&ATA_PIO_LMR, (sector >> 5) & 0xff);
|
| 753 | + ata_write_cbr(&ATA_PIO_LLR, (sector << 3) & 0xff);
|
| 754 | + ata_write_cbr(&ATA_PIO_DVR, BIT(6) | ((sector >> 21) & 0xf));
|
| 755 | + if (write) ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0xca : 0x30);
|
| 756 | + else ata_write_cbr(&ATA_PIO_CSD, ata_dma ? 0xc8 : 0xc4);
|
344 | 757 | }
|
345 | | - ATA_XFR_NUM = SECTOR_SIZE * cnt - 1;
|
346 | | - ATA_CFG |= ata_dma_flags;
|
347 | | - ATA_CFG &= ~(BIT(7) | BIT(8));
|
348 | | - wakeup_wait(&ata_wakeup, TIMEOUT_NONE);
|
349 | | - ATA_IRQ = BITRANGE(0, 4);
|
350 | | - ATA_IRQ_MASK = BIT(0);
|
351 | | - ATA_COMMAND = BIT(0);
|
352 | | - if (wakeup_wait(&ata_wakeup, 500000) == THREAD_TIMEOUT)
|
| 758 | + if (ata_dma)
|
353 | 759 | {
|
| 760 | + PASS_RC(ata_wait_for_start_of_transfer(500000), 2, 1);
|
| 761 | + if (write)
|
| 762 | + {
|
| 763 | + ATA_SBUF_START = buffer;
|
| 764 | + ATA_SBUF_SIZE = SECTOR_SIZE * cnt;
|
| 765 | + ATA_CFG |= BIT(4);
|
| 766 | + }
|
| 767 | + else
|
| 768 | + {
|
| 769 | + ATA_TBUF_START = buffer;
|
| 770 | + ATA_TBUF_SIZE = SECTOR_SIZE * cnt;
|
| 771 | + ATA_CFG &= ~BIT(4);
|
| 772 | + }
|
| 773 | + ATA_XFR_NUM = SECTOR_SIZE * cnt - 1;
|
| 774 | + ATA_CFG |= ata_dma_flags;
|
| 775 | + ATA_CFG &= ~(BIT(7) | BIT(8));
|
| 776 | + wakeup_wait(&ata_wakeup, TIMEOUT_NONE);
|
| 777 | + ATA_IRQ = BITRANGE(0, 4);
|
| 778 | + ATA_IRQ_MASK = BIT(0);
|
| 779 | + ATA_COMMAND = BIT(0);
|
| 780 | + if (wakeup_wait(&ata_wakeup, 500000) == THREAD_TIMEOUT)
|
| 781 | + {
|
| 782 | + ATA_COMMAND = BIT(1);
|
| 783 | + ATA_CFG &= ~(BITRANGE(2, 3) | BIT(12));
|
| 784 | + RET_ERR(2);
|
| 785 | + }
|
354 | 786 | ATA_COMMAND = BIT(1);
|
355 | 787 | ATA_CFG &= ~(BITRANGE(2, 3) | BIT(12));
|
356 | | - RET_ERR(2);
|
357 | 788 | }
|
358 | | - ATA_COMMAND = BIT(1);
|
359 | | - ATA_CFG &= ~(BITRANGE(2, 3) | BIT(12));
|
360 | | - }
|
361 | | - else
|
362 | | - {
|
363 | | - cnt *= SECTOR_SIZE / 512;
|
364 | | - while (cnt--)
|
| 789 | + else
|
365 | 790 | {
|
366 | | - int i;
|
367 | | - PASS_RC(ata_wait_for_start_of_transfer(500000), 2, 1);
|
368 | | - if (write)
|
369 | | - for (i = 0; i < 256; i++)
|
370 | | - ata_write_cbr(&ATA_PIO_DTR, ((uint16_t*)buffer)[i]);
|
371 | | - else
|
372 | | - for (i = 0; i < 256; i++)
|
373 | | - ((uint16_t*)buffer)[i] = ata_read_cbr(&ATA_PIO_DTR);
|
374 | | - buffer += 512;
|
| 791 | + cnt *= SECTOR_SIZE / 512;
|
| 792 | + while (cnt--)
|
| 793 | + {
|
| 794 | + int i;
|
| 795 | + PASS_RC(ata_wait_for_start_of_transfer(500000), 2, 1);
|
| 796 | + if (write)
|
| 797 | + for (i = 0; i < 256; i++)
|
| 798 | + ata_write_cbr(&ATA_PIO_DTR, ((uint16_t*)buffer)[i]);
|
| 799 | + else
|
| 800 | + for (i = 0; i < 256; i++)
|
| 801 | + ((uint16_t*)buffer)[i] = ata_read_cbr(&ATA_PIO_DTR);
|
| 802 | + buffer += 512;
|
| 803 | + }
|
375 | 804 | }
|
| 805 | + PASS_RC(ata_wait_for_end_of_transfer(100000), 2, 3);
|
376 | 806 | }
|
377 | | - PASS_RC(ata_wait_for_end_of_transfer(100000), 2, 3);
|
378 | 807 | return 0;
|
379 | 808 | }
|
380 | 809 |
|
— | — | @@ -465,7 +894,7 @@ |
466 | 895 | ata_set_active();
|
467 | 896 | if (ata_dma && write) clean_dcache();
|
468 | 897 | else if (ata_dma) invalidate_dcache();
|
469 | | - ATA_COMMAND = BIT(1);
|
| 898 | + if (!ceata) ATA_COMMAND = BIT(1);
|
470 | 899 | while (count)
|
471 | 900 | {
|
472 | 901 | uint32_t cnt = MIN(ata_lba48 ? 8192 : 32, count);
|
— | — | @@ -513,13 +942,18 @@ |
514 | 943 | /* API Functions */
|
515 | 944 | int ata_soft_reset()
|
516 | 945 | {
|
| 946 | + int rc;
|
517 | 947 | mutex_lock(&ata_mutex, TIMEOUT_BLOCK);
|
518 | 948 | if (!ata_powered) ata_power_up();
|
519 | 949 | ata_set_active();
|
520 | | - ata_write_cbr(&ATA_PIO_DAD, BIT(1) | BIT(2));
|
521 | | - sleep(10);
|
522 | | - ata_write_cbr(&ATA_PIO_DAD, 0);
|
523 | | - int rc = ata_wait_for_rdy(20000000);
|
| 950 | + if (ceata) rc = ceata_soft_reset();
|
| 951 | + else
|
| 952 | + {
|
| 953 | + ata_write_cbr(&ATA_PIO_DAD, BIT(1) | BIT(2));
|
| 954 | + sleep(10);
|
| 955 | + ata_write_cbr(&ATA_PIO_DAD, 0);
|
| 956 | + rc = ata_wait_for_rdy(20000000);
|
| 957 | + }
|
524 | 958 | if (IS_ERR(rc))
|
525 | 959 | {
|
526 | 960 | ata_power_down();
|
— | — | @@ -658,10 +1092,26 @@ |
659 | 1093 | {
|
660 | 1094 | mutex_init(&ata_mutex);
|
661 | 1095 | wakeup_init(&ata_wakeup);
|
662 | | - PCON(7) = 0x44444444;
|
663 | | - PCON(8) = 0x44444444;
|
664 | | - PCON(9) = 0x44444444;
|
665 | | - PCON(10) = (PCON(10) & ~0xffff) | 0x4444;
|
| 1096 | + wakeup_init(&mmc_wakeup);
|
| 1097 | + wakeup_init(&mmc_comp_wakeup);
|
| 1098 | + ceata = PDAT(11) & BIT(1);
|
| 1099 | + if (ceata)
|
| 1100 | + {
|
| 1101 | + ata_lba48 = true;
|
| 1102 | + ata_dma = true;
|
| 1103 | + PCON(8) = 0x33333333;
|
| 1104 | + PCON(9) = (PCON(9) & ~0xff) | 0x33;
|
| 1105 | + PCON(11) |= 0xf;
|
| 1106 | + *((uint32_t volatile*)0x38a00000) = 0;
|
| 1107 | + *((uint32_t volatile*)0x38700000) = 0;
|
| 1108 | + }
|
| 1109 | + else
|
| 1110 | + {
|
| 1111 | + PCON(7) = 0x44444444;
|
| 1112 | + PCON(8) = 0x44444444;
|
| 1113 | + PCON(9) = 0x44444444;
|
| 1114 | + PCON(10) = (PCON(10) & ~0xffff) | 0x4444;
|
| 1115 | + }
|
666 | 1116 | ata_powered = false;
|
667 | 1117 | ata_total_sectors = 0;
|
668 | 1118 | #ifdef ATA_HAVE_BBT
|
— | — | @@ -689,3 +1139,11 @@ |
690 | 1140 | if (ata_irq & ATA_IRQ_MASK) wakeup_signal(&ata_wakeup);
|
691 | 1141 | ATA_IRQ_MASK = 0;
|
692 | 1142 | }
|
| 1143 | +
|
| 1144 | +void INT_MMC()
|
| 1145 | +{
|
| 1146 | + uint32_t irq = SDCI_IRQ;
|
| 1147 | + if (irq & SDCI_IRQ_DAT_DONE_INT) wakeup_signal(&mmc_wakeup);
|
| 1148 | + if (irq & SDCI_IRQ_IOCARD_IRQ_INT) wakeup_signal(&mmc_comp_wakeup);
|
| 1149 | + SDCI_IRQ = irq;
|
| 1150 | +}
|
Index: emcore/trunk/constants/mmc.h |
— | — | @@ -0,0 +1,302 @@ |
| 2 | +// |
| 3 | +// |
| 4 | +// Copyright 2010 TheSeven |
| 5 | +// |
| 6 | +// |
| 7 | +// This file is part of emCORE. |
| 8 | +// |
| 9 | +// emCORE is free software: you can redistribute it and/or |
| 10 | +// modify it under the terms of the GNU General Public License as |
| 11 | +// published by the Free Software Foundation, either version 2 of the |
| 12 | +// License, or (at your option) any later version. |
| 13 | +// |
| 14 | +// emCORE is distributed in the hope that it will be useful, |
| 15 | +// but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
| 17 | +// See the GNU General Public License for more details. |
| 18 | +// |
| 19 | +// You should have received a copy of the GNU General Public License along |
| 20 | +// with emCORE. If not, see <http://www.gnu.org/licenses/>. |
| 21 | +// |
| 22 | +// |
| 23 | + |
| 24 | + |
| 25 | +#ifndef __CONSTANTS_MMC_H__
|
| 26 | +#define __CONSTANTS_MMC_H__
|
| 27 | + |
| 28 | + |
| 29 | +#include "global.h" |
| 30 | + |
| 31 | + |
| 32 | +#define MMC_CMD_GO_IDLE_STATE 0 |
| 33 | +#define MMC_CMD_SEND_OP_COND 1 |
| 34 | +#define MMC_CMD_ALL_SEND_CID 2 |
| 35 | +#define MMC_CMD_SET_RELATIVE_ADDR 3 |
| 36 | +#define MMC_CMD_SET_DSR 4 |
| 37 | +#define MMC_CMD_SLEEP_AWAKE 5 |
| 38 | +#define MMC_CMD_SWITCH 6 |
| 39 | +#define MMC_CMD_SELECT_CARD 7 |
| 40 | +#define MMC_CMD_SEND_EXT_CSD 8 |
| 41 | +#define MMC_CMD_SEND_CSD 9 |
| 42 | +#define MMC_CMD_SEND_CID 10 |
| 43 | +#define MMC_CMD_READ_DAT_UNTIL_STOP 11 |
| 44 | +#define MMC_CMD_STOP_TRANSMISSION 12 |
| 45 | +#define MMC_CMD_SEND_STATUS 13 |
| 46 | +#define MMC_CMD_BUSTEST_R 14 |
| 47 | +#define MMC_CMD_GO_INAVTIVE_STATE 15 |
| 48 | +#define MMC_CMD_SET_BLOCKLEN 16 |
| 49 | +#define MMC_CMD_READ_SINGLE_BLOCK 17 |
| 50 | +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 |
| 51 | +#define MMC_CMD_BUSTEST_W 19 |
| 52 | +#define MMC_CMD_WRITE_DAT_UNTIL_STOP 20 |
| 53 | +#define MMC_CMD_SET_BLOCK_COUNT 23 |
| 54 | +#define MMC_CMD_WRITE_BLOCK 24 |
| 55 | +#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 |
| 56 | +#define MMC_CMD_PROGRAM_CID 26 |
| 57 | +#define MMC_CMD_PROGRAM_CSD 27 |
| 58 | +#define MMC_CMD_SET_WRITE_PROT 28 |
| 59 | +#define MMC_CMD_CLR_WRITE_PROT 29 |
| 60 | +#define MMC_CMD_SEND_WRITE_PROT 30 |
| 61 | +#define MMC_CMD_ERASE_GROUP_START 35 |
| 62 | +#define MMC_CMD_ERASE_GROUP_END 36 |
| 63 | +#define MMC_CMD_ERASE 38 |
| 64 | +#define MMC_CMD_FAST_IO 39 |
| 65 | +#define MMC_CMD_GO_IRQ_STATE 40 |
| 66 | +#define MMC_CMD_LOCK_UNLOCK 42 |
| 67 | +#define MMC_CMD_APP_CMD 55 |
| 68 | +#define MMC_CMD_GEN_CMD 56 |
| 69 | +#define MMC_CMD_CEATA_RW_MULTIPLE_REG 60 |
| 70 | +#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK 61 |
| 71 | + |
| 72 | +#define MMC_CMD_SEND_OP_COND_OCR_MASK BITRANGE(0, 31) |
| 73 | +#define MMC_CMD_SEND_OP_COND_OCR_SHIFT 0 |
| 74 | +#define MMC_CMD_SEND_OP_COND_OCR(x) (x) |
| 75 | + |
| 76 | +#define MMC_CMD_SET_RELATIVE_ADDR_RCA_MASK BITRANGE(16, 31) |
| 77 | +#define MMC_CMD_SET_RELATIVE_ADDR_RCA_SHIFT 16 |
| 78 | +#define MMC_CMD_SET_RELATIVE_ADDR_RCA(x) ((x) << 16) |
| 79 | + |
| 80 | +#define MMC_CMD_SET_DSR_DSR_MASK BITRANGE(16, 31) |
| 81 | +#define MMC_CMD_SET_DSR_DSR_SHIFT 16 |
| 82 | +#define MMC_CMD_SET_DSR_DSR(x) ((x) << 16) |
| 83 | + |
| 84 | +#define MMC_CMD_SLEEP_AWAKE_SLEEP_AWAKE_MASK BIT(15) |
| 85 | +#define MMC_CMD_SLEEP_AWAKE_SLEEP_AWAKE_AWAKE 0 |
| 86 | +#define MMC_CMD_SLEEP_AWAKE_SLEEP_AWAKE_SLEEP BIT(15) |
| 87 | +#define MMC_CMD_SLEEP_AWAKE_RCA_MASK BITRANGE(16, 31) |
| 88 | +#define MMC_CMD_SLEEP_AWAKE_RCA_SHIFT 16 |
| 89 | +#define MMC_CMD_SLEEP_AWAKE_RCA(x) ((x) << 16) |
| 90 | + |
| 91 | +#define MMC_CMD_SWITCH_ACCESS_MASK BITRANGE(24, 25); |
| 92 | +#define MMC_CMD_SWITCH_ACCESS_CMDSET 0 |
| 93 | +#define MMC_CMD_SWITCH_ACCESS_SET_BITS BIT(24) |
| 94 | +#define MMC_CMD_SWITCH_ACCESS_CLEAR_BITS BIT(25) |
| 95 | +#define MMC_CMD_SWITCH_ACCESS_WRITE_BYTE (BIT(24) | BIT(25)) |
| 96 | +#define MMC_CMD_SWTICH_INDEX_MASK BITRANGE(16, 23); |
| 97 | +#define MMC_CMD_SWITCH_INDEX_SHIFT 16 |
| 98 | +#define MMC_CMD_SWITCH_INDEX(x) ((x) << 16) |
| 99 | +#define MMC_CMD_SWTICH_VALUE_MASK BITRANGE(8, 15); |
| 100 | +#define MMC_CMD_SWITCH_VALUE_SHIFT 8 |
| 101 | +#define MMC_CMD_SWITCH_VALUE(x) ((x) << 8) |
| 102 | +#define MMC_CMD_SWTICH_CMDSET_MASK BITRANGE(0, 2); |
| 103 | +#define MMC_CMD_SWITCH_CMDSET_STANDARD_MMC 0 |
| 104 | + |
| 105 | +#define MMC_CMD_SELECT_CARD_RCA_MASK BITRANGE(16, 31) |
| 106 | +#define MMC_CMD_SELECT_CARD_RCA_SHIFT 16 |
| 107 | +#define MMC_CMD_SELECT_CARD_RCA(x) ((x) << 16) |
| 108 | + |
| 109 | +#define MMC_CMD_SEND_CSD_RCA_MASK BITRANGE(16, 31) |
| 110 | +#define MMC_CMD_SEND_CSD_RCA_SHIFT 16 |
| 111 | +#define MMC_CMD_SEND_CSD_RCA(x) ((x) << 16) |
| 112 | + |
| 113 | +#define MMC_CMD_SEND_CID_RCA_MASK BITRANGE(16, 31) |
| 114 | +#define MMC_CMD_SEND_CID_RCA_SHIFT 16 |
| 115 | +#define MMC_CMD_SEND_CID_RCA(x) ((x) << 16) |
| 116 | + |
| 117 | +#define MMC_CMD_READ_DAT_UNTIL_STOP_ADDRESS_MASK BITRANGE(0, 31) |
| 118 | +#define MMC_CMD_READ_DAT_UNTIL_STOP_ADDRESS_SHIFT 0 |
| 119 | +#define MMC_CMD_READ_DAT_UNTIL_STOP_ADDRESS(x) (x) |
| 120 | + |
| 121 | +#define MMC_CMD_SEND_STATUS_RCA_MASK BITRANGE(16, 31) |
| 122 | +#define MMC_CMD_SEND_STATUS_RCA_SHIFT 16 |
| 123 | +#define MMC_CMD_SEND_STATUS_RCA(x) ((x) << 16) |
| 124 | + |
| 125 | +#define MMC_CMD_GO_INACTIVE_STATE_RCA_MASK BITRANGE(16, 31) |
| 126 | +#define MMC_CMD_GO_INACTIVE_STATE_RCA_SHIFT 16 |
| 127 | +#define MMC_CMD_GO_INACTIVE_STATE_RCA(x) ((x) << 16) |
| 128 | + |
| 129 | +#define MMC_CMD_SET_BLOCKLEN_LENGTH_MASK BITRANGE(0, 31) |
| 130 | +#define MMC_CMD_SET_BLOCKLEN_LENGTH_SHIFT 0 |
| 131 | +#define MMC_CMD_SET_BLOCKLEN_LENGTH(x) (x) |
| 132 | + |
| 133 | +#define MMC_CMD_READ_SINGLE_BLOCK_ADDRESS_MASK BITRANGE(0, 31) |
| 134 | +#define MMC_CMD_READ_SINGLE_BLOCK_ADDRESS_SHIFT 0 |
| 135 | +#define MMC_CMD_READ_SINGLE_BLOCK_ADDRESS(x) (x) |
| 136 | + |
| 137 | +#define MMC_CMD_READ_MULTIPLE_BLOCK_ADDRESS_MASK BITRANGE(0, 31) |
| 138 | +#define MMC_CMD_READ_MULTIPLE_BLOCK_ADDRESS_SHIFT 0 |
| 139 | +#define MMC_CMD_READ_MULTIPLE_BLOCK_ADDRESS(x) (x) |
| 140 | + |
| 141 | +#define MMC_CMD_WRITE_DAT_UNTIL_STOP_ADDRESS_MASK BITRANGE(0, 31) |
| 142 | +#define MMC_CMD_WRITE_DAT_UNTIL_STOP_ADDRESS_SHIFT 0 |
| 143 | +#define MMC_CMD_WRITE_DAT_UNTIL_STOP_ADDRESS(x) (x) |
| 144 | + |
| 145 | +#define MMC_CMD_SET_BLOCK_COUNT_RELIABLE BIT(31) |
| 146 | +#define MMC_CMD_SET_BLOCK_COUNT_COUNT_MASK BITRANGE(0, 15) |
| 147 | +#define MMC_CMD_SET_BLOCK_COUNT_COUNT_SHIFT 0 |
| 148 | +#define MMC_CMD_SET_BLOCK_COUNT_COUNT(x) (x) |
| 149 | + |
| 150 | +#define MMC_CMD_WRITE_BLOCK_ADDRESS_MASK BITRANGE(0, 31) |
| 151 | +#define MMC_CMD_WRITE_BLOCK_ADDRESS_SHIFT 0 |
| 152 | +#define MMC_CMD_WRITE_BLOCK_ADDRESS(x) (x) |
| 153 | + |
| 154 | +#define MMC_CMD_WRITE_MULTIPLE_BLOCK_ADDRESS_MASK BITRANGE(0, 31) |
| 155 | +#define MMC_CMD_WRITE_MULTIPLE_BLOCK_ADDRESS_SHIFT 0 |
| 156 | +#define MMC_CMD_WRITE_MULTIPLE_BLOCK_ADDRESS(x) (x) |
| 157 | + |
| 158 | +#define MMC_CMD_SET_WRITE_PROT_ADDRESS_MASK BITRANGE(0, 31) |
| 159 | +#define MMC_CMD_SET_WRITE_PROT_ADDRESS_SHIFT 0 |
| 160 | +#define MMC_CMD_SET_WRITE_PROT_ADDRESS(x) (x) |
| 161 | + |
| 162 | +#define MMC_CMD_CLR_WRITE_PROT_ADDRESS_MASK BITRANGE(0, 31) |
| 163 | +#define MMC_CMD_CLR_WRITE_PROT_ADDRESS_SHIFT 0 |
| 164 | +#define MMC_CMD_CLR_WRITE_PROT_ADDRESS(x) (x) |
| 165 | + |
| 166 | +#define MMC_CMD_SEND_WRITE_PROT_ADDRESS_MASK BITRANGE(0, 31) |
| 167 | +#define MMC_CMD_SEND_WRITE_PROT_ADDRESS_SHIFT 0 |
| 168 | +#define MMC_CMD_SEND_WRITE_PROT_ADDRESS(x) (x) |
| 169 | + |
| 170 | +#define MMC_CMD_ERASE_GROUP_START_ADDRESS_MASK BITRANGE(0, 31) |
| 171 | +#define MMC_CMD_ERASE_GROUP_START_ADDRESS_SHIFT 0 |
| 172 | +#define MMC_CMD_ERASE_GROUP_START_ADDRESS(x) (x) |
| 173 | + |
| 174 | +#define MMC_CMD_ERASE_GROUP_END_ADDRESS_MASK BITRANGE(0, 31) |
| 175 | +#define MMC_CMD_ERASE_GROUP_END_ADDRESS_SHIFT 0 |
| 176 | +#define MMC_CMD_ERASE_GROUP_END_ADDRESS(x) (x) |
| 177 | + |
| 178 | +#define MMC_CMD_FAST_IO_RCA_MASK BITRANGE(16, 31) |
| 179 | +#define MMC_CMD_FAST_IO_RCA_SHIFT 16 |
| 180 | +#define MMC_CMD_FAST_IO_RCA(x) ((x) << 16) |
| 181 | +#define MMC_CMD_FAST_IO_DIRECTION_MASK BIT(15) |
| 182 | +#define MMC_CMD_FAST_IO_DIRECTION_READ 0 |
| 183 | +#define MMC_CMD_FAST_IO_DIRECTION_WRITE BIT(15) |
| 184 | +#define MMC_CMD_FAST_IO_ADDRESS_MASK BITRANGE(8, 14) |
| 185 | +#define MMC_CMD_FAST_IO_ADDRESS_SHIFT 8 |
| 186 | +#define MMC_CMD_FAST_IO_ADDRESS(x) ((x) << 8) |
| 187 | +#define MMC_CMD_FAST_IO_DATA_MASK BITRANGE(0, 7) |
| 188 | +#define MMC_CMD_FAST_IO_DATA_SHIFT 0 |
| 189 | +#define MMC_CMD_FAST_IO_DATA(x) (x) |
| 190 | + |
| 191 | +#define MMC_CMD_APP_CMD_RCA_MASK BITRANGE(16, 31) |
| 192 | +#define MMC_CMD_APP_CMD_RCA_SHIFT 16 |
| 193 | +#define MMC_CMD_APP_CMD_RCA(x) ((x) << 16) |
| 194 | + |
| 195 | +#define MMC_CMD_GEN_CMD_DIRECTION_MASK BIT(0) |
| 196 | +#define MMC_CMD_GEN_CMD_DIRECTION_READ 0 |
| 197 | +#define MMC_CMD_GEN_CMD_DIRECTION_WRITE BIT(0) |
| 198 | + |
| 199 | +#define MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_MASK BIT(31) |
| 200 | +#define MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_READ 0 |
| 201 | +#define MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_WRITE BIT(31) |
| 202 | +#define MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS_MASK BITRANGE(16, 23) |
| 203 | +#define MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS_SHIFT 16 |
| 204 | +#define MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(x) ((x) << 16) |
| 205 | +#define MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT_MASK BITRANGE(0, 7) |
| 206 | +#define MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT_SHIFT 0 |
| 207 | +#define MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(x) (x) |
| 208 | + |
| 209 | +#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_MASK BIT(31) |
| 210 | +#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_READ 0 |
| 211 | +#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_WRITE BIT(31) |
| 212 | +#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT_MASK BITRANGE(0, 15) |
| 213 | +#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT_SHIFT 0 |
| 214 | +#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT(x) (x) |
| 215 | + |
| 216 | +#define MMC_CMD_SWITCH_FIELD_ERASE_GROUP_DEF 175 |
| 217 | +#define MMC_CMD_SWITCH_FIELD_BOOT_BUS_WIDTH 177 |
| 218 | +#define MMC_CMD_SWITCH_FIELD_BOOT_CONFIG 179 |
| 219 | +#define MMC_CMD_SWITCH_FIELD_ERASED_MEM_CONT 181 |
| 220 | +#define MMC_CMD_SWITCH_FIELD_BUS_WIDTH 183 |
| 221 | +#define MMC_CMD_SWITCH_FIELD_HS_TIMING 185 |
| 222 | +#define MMC_CMD_SWITCH_FIELD_POWER_CLASS 187 |
| 223 | +#define MMC_CMD_SWITCH_FIELD_CMD_SET_REV 189 |
| 224 | +#define MMC_CMD_SWITCH_FIELD_CMD_SET 191 |
| 225 | +#define MMC_CMD_SWITCH_FIELD_EXT_CSD_REV 192 |
| 226 | +#define MMC_CMD_SWITCH_FIELD_CSD_STRUCTURE 194 |
| 227 | +#define MMC_CMD_SWITCH_FIELD_CARD_TYPE 196 |
| 228 | +#define MMC_CMD_SWITCH_FIELD_PWR_CL_52_195 200 |
| 229 | +#define MMC_CMD_SWITCH_FIELD_PWR_CL_26_195 201 |
| 230 | +#define MMC_CMD_SWITCH_FIELD_PWR_CL_52_360 202 |
| 231 | +#define MMC_CMD_SWITCH_FIELD_PWR_CL_26_360 203 |
| 232 | +#define MMC_CMD_SWITCH_FIELD_MIN_PERF_R_4_26 205 |
| 233 | +#define MMC_CMD_SWITCH_FIELD_MIN_PERF_W_4_26 206 |
| 234 | +#define MMC_CMD_SWITCH_FIELD_MIN_PERF_R_8_26_4_52 207 |
| 235 | +#define MMC_CMD_SWITCH_FIELD_MIN_PERF_W_8_26_4_52 208 |
| 236 | +#define MMC_CMD_SWITCH_FIELD_MIN_PERF_R_8_52 209 |
| 237 | +#define MMC_CMD_SWITCH_FIELD_MIN_PERF_W_8_52 210 |
| 238 | +#define MMC_CMD_SWITCH_FIELD_SEC_COUNT_0 212 |
| 239 | +#define MMC_CMD_SWITCH_FIELD_SEC_COUNT_1 213 |
| 240 | +#define MMC_CMD_SWITCH_FIELD_SEC_COUNT_2 214 |
| 241 | +#define MMC_CMD_SWITCH_FIELD_SEC_COUNT_3 215 |
| 242 | +#define MMC_CMD_SWITCH_FIELD_S_A_TIMEOUT 217 |
| 243 | +#define MMC_CMD_SWITCH_FIELD_S_C_VCCQ 219 |
| 244 | +#define MMC_CMD_SWITCH_FIELD_S_C_VCC 220 |
| 245 | +#define MMC_CMD_SWITCH_FIELD_HC_WP_GRP_SIZE 221 |
| 246 | +#define MMC_CMD_SWITCH_FIELD_REL_WR_SEC_C 222 |
| 247 | +#define MMC_CMD_SWITCH_FIELD_ERASE_TIMEOUT_MULT 223 |
| 248 | +#define MMC_CMD_SWITCH_FIELD_HC_ERASE_GRP_SIZE 224 |
| 249 | +#define MMC_CMD_SWITCH_FIELD_ACC_SIZE 225 |
| 250 | +#define MMC_CMD_SWITCH_FIELD_BOOT_SIZE_MULTI 226 |
| 251 | +#define MMC_CMD_SWITCH_FIELD_S_CMD_SET 504 |
| 252 | + |
| 253 | +#define MMC_CMD_SWITCH_FIELD_BUS_WIDTH_1BIT 0 |
| 254 | +#define MMC_CMD_SWITCH_FIELD_BUS_WIDTH_4BIT 1 |
| 255 | +#define MMC_CMD_SWITCH_FIELD_BUS_WIDTH_8BIT 2 |
| 256 | + |
| 257 | +#define MMC_CMD_SWITCH_FIELD_HS_TIMING_LOW_SPEED 0 |
| 258 | +#define MMC_CMD_SWITCH_FIELD_HS_TIMING_HIGH_SPEED 1 |
| 259 | + |
| 260 | +#define MMC_STATUS_APP_CMD BIT(5) |
| 261 | +#define MMC_STATUS_SWITCH_ERROR BIT(7) |
| 262 | +#define MMC_STATUS_READY_FOR_DATA BIT(8) |
| 263 | +#define MMC_STATUS_CURRENT_STATE_MASK BITRANGE(9, 12) |
| 264 | +#define MMC_STATUS_CURRENT_STATE_IDLE 0 |
| 265 | +#define MMC_STATUS_CURRENT_STATE_READY BIT(9) |
| 266 | +#define MMC_STATUS_CURRENT_STATE_IDENT BIT(10) |
| 267 | +#define MMC_STATUS_CURRENT_STATE_STBY (BIT(9) | BIT(10)) |
| 268 | +#define MMC_STATUS_CURRENT_STATE_TRAN BIT(11) |
| 269 | +#define MMC_STATUS_CURRENT_STATE_DATA (BIT(9) | BIT(11)) |
| 270 | +#define MMC_STATUS_CURRENT_STATE_RCV (BIT(10) | BIT(11)) |
| 271 | +#define MMC_STATUS_CURRENT_STATE_PRG (BIT(9) | BIT(10) | BIT(11)) |
| 272 | +#define MMC_STATUS_CURRENT_STATE_DIS BIT(12) |
| 273 | +#define MMC_STATUS_CURRENT_STATE_BTST (BIT(9) | BIT(12)) |
| 274 | +#define MMC_STATUS_CURRENT_STATE_SLP (BIT(10) | BIT(12)) |
| 275 | +#define MMC_STATUS_ERASE_RESET BIT(13) |
| 276 | +#define MMC_STATUS_WP_ERASE_SKIP BIT(15) |
| 277 | +#define MMC_STATUS_CID_CSD_OVERWRITE BIT(16) |
| 278 | +#define MMC_STATUS_OVERRUN BIT(17) |
| 279 | +#define MMC_STATUS_UNDERRUN BIT(18) |
| 280 | +#define MMC_STATUS_ERROR BIT(19) |
| 281 | +#define MMC_STATUS_CC_ERROR BIT(20) |
| 282 | +#define MMC_STATUS_CARD_ECC_FAILED BIT(21) |
| 283 | +#define MMC_STATUS_ILLEGAL_COMMAND BIT(22) |
| 284 | +#define MMC_STATUS_COM_CRC_ERROR BIT(23) |
| 285 | +#define MMC_STATUS_LOCK_UNLOCK_FAILED BIT(24) |
| 286 | +#define MMC_STATUS_CARD_IS_LOCKED BIT(25) |
| 287 | +#define MMC_STATUS_WP_VIOLATION BIT(26) |
| 288 | +#define MMC_STATUS_ERASE_PARAM BIT(27) |
| 289 | +#define MMC_STATUS_ERASE_SEQ_ERROR BIT(28) |
| 290 | +#define MMC_STATUS_BLOCK_LEN_ERROR BIT(29) |
| 291 | +#define MMC_STATUS_ADDRESS_MISALIGN BIT(30) |
| 292 | +#define MMC_STATUS_ADDRESS_OUT_OF_RANGE BIT(31) |
| 293 | + |
| 294 | +#define MMC_OCR_170_195 BIT(7) |
| 295 | +#define MMC_OCR_200_260 BITRANGE(8, 14) |
| 296 | +#define MMC_OCR_270_360 BITRANGE(15, 23) |
| 297 | +#define MMC_OCR_ACCESS_MODE_MASK BITRANGE(29, 30) |
| 298 | +#define MMC_OCR_ACCESS_MODE_BYTE 0 |
| 299 | +#define MMC_OCR_ACCESS_MODE_SECTOR BIT(30) |
| 300 | +#define MMC_OCR_POWER_UP_DONE BIT(31) |
| 301 | + |
| 302 | + |
| 303 | +#endif |