| Index: apps/installer-ipodnano4g/tools/stubembed.py |
| — | — | @@ -0,0 +1,38 @@ |
| | 2 | +#!/usr/bin/env python
|
| | 3 | +#
|
| | 4 | +#
|
| | 5 | +# Copyright 2010 TheSeven
|
| | 6 | +#
|
| | 7 | +#
|
| | 8 | +# This file is part of emCORE.
|
| | 9 | +#
|
| | 10 | +# emCORE is free software: you can redistribute it and/or
|
| | 11 | +# modify it under the terms of the GNU General Public License as
|
| | 12 | +# published by the Free Software Foundation, either version 2 of the
|
| | 13 | +# License, or (at your option) any later version.
|
| | 14 | +#
|
| | 15 | +# emCORE is distributed in the hope that it will be useful,
|
| | 16 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| | 17 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
| | 18 | +# See the GNU General Public License for more details.
|
| | 19 | +#
|
| | 20 | +# You should have received a copy of the GNU General Public License along
|
| | 21 | +# with emCORE. If not, see <http://www.gnu.org/licenses/>.
|
| | 22 | +#
|
| | 23 | +#
|
| | 24 | +
|
| | 25 | +
|
| | 26 | +import sys
|
| | 27 | +import struct
|
| | 28 | +
|
| | 29 | +file = open(sys.argv[1], "rb")
|
| | 30 | +stub = file.read()
|
| | 31 | +file.close()
|
| | 32 | +
|
| | 33 | +file = open(sys.argv[2], "rb")
|
| | 34 | +payload = file.read()
|
| | 35 | +file.close()
|
| | 36 | +
|
| | 37 | +file = open(sys.argv[3], "wb")
|
| | 38 | +file.write(stub + struct.pack("<I", len(payload)) + payload)
|
| | 39 | +file.close()
|
| Index: apps/installer-ipodnano4g/bootstub/bootstub.S |
| — | — | @@ -0,0 +1,922 @@ |
| | 2 | +@
|
| | 3 | +@
|
| | 4 | +@ emCORE Loader for iPod Nano 4G
|
| | 5 | +@
|
| | 6 | +@ Copyright 2011 TheSeven, Farthen
|
| | 7 | +@
|
| | 8 | +@
|
| | 9 | +@ This file is part of emCORE.
|
| | 10 | +@
|
| | 11 | +@ emCORE is free software: you can redistribute it and/or
|
| | 12 | +@ modify it under the terms of the GNU General Public License as
|
| | 13 | +@ published by the Free Software Foundation, either version 2 of the
|
| | 14 | +@ License, or (at your option) any later version.
|
| | 15 | +@
|
| | 16 | +@ emCORE is distributed in the hope that it will be useful,
|
| | 17 | +@ but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| | 18 | +@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
| | 19 | +@ See the GNU General Public License for more details.
|
| | 20 | +@
|
| | 21 | +@ You should have received a copy of the GNU General Public License along
|
| | 22 | +@ with emCORE. If not, see <http://www.gnu.org/licenses/>.
|
| | 23 | +@
|
| | 24 | +@
|
| | 25 | +
|
| | 26 | +.global _start
|
| | 27 | +_start:
|
| | 28 | +
|
| | 29 | + msr cpsr_c, #0xd3
|
| | 30 | + mrc p15, 0, r0,c1,c0
|
| | 31 | + bic r0, r0, #1
|
| | 32 | + mcr p15, 0, r0,c1,c0 @ disable mmu
|
| | 33 | +
|
| | 34 | + mov lr, #0
|
| | 35 | + adr sp, values1
|
| | 36 | + mcr p15, 0, lr,c7,c14,0 @ clean & invalidate data cache
|
| | 37 | + mcr p15, 0, lr,c7,c10,4 @ drain write buffer
|
| | 38 | + mcr p15, 0, lr,c7,c5 @ invalidate instruction cache
|
| | 39 | + mcr p15, 0, lr,c8,c7 @ invalidate all unlocked entries in the TLB
|
| | 40 | + mcr p15, 0, lr,c13,c0,0 @ disable context id register
|
| | 41 | +
|
| | 42 | +.macro block0_constpool @ Block 0 (MMU, DMA) register map:
|
| | 43 | + @ R0: Unused
|
| | 44 | + @ R1: Unused
|
| | 45 | + @ R2: Unused
|
| | 46 | + @ R3: Scratchpad
|
| | 47 | + @ R4: Unused
|
| | 48 | + @ R5: Unused
|
| | 49 | + @ R6: Unused
|
| | 50 | + @ R7: Unused
|
| | 51 | + @ R8: Unused
|
| | 52 | + @ R9: Unused
|
| | 53 | + .word 0x0005107D @ R10: CP15r1
|
| | 54 | + .word 0x2202C000 @ R11: First level page table
|
| | 55 | + .word 0x00000C1E @ R12: Default segment flags
|
| | 56 | + @ R13: Constant pool pointer
|
| | 57 | +.endm @ R14: 0
|
| | 58 | +
|
| | 59 | + ldmia sp!, {r10-r12}
|
| | 60 | + mcr p15, 0, r11,c2,c0 @ set first level translation table
|
| | 61 | + mov r3, #-1
|
| | 62 | + mcr p15, 0, r3,c3,c0 @ disable domain access control @ R3: Unused
|
| | 63 | +mmuloop:
|
| | 64 | + str r12, [r11], #4
|
| | 65 | + add r12, r12, #0x00100000
|
| | 66 | + cmp r12, #0x38000000
|
| | 67 | + biccs r12, r12, #0xc
|
| | 68 | + tst r12, #0x40000000
|
| | 69 | + beq mmuloop
|
| | 70 | + @ R11: Unused
|
| | 71 | + @ R12: Unused
|
| | 72 | + mcr p15, 0, r10,c1,c0 @ R10: Unused
|
| | 73 | +
|
| | 74 | +.macro block1_constpool @ Block 1 (SYSCON) register map:
|
| | 75 | + .word 0x000327E5 @ R0: PWRCON(0)
|
| | 76 | + .word 0xFE2BED6D @ R1: PWRCON(1)
|
| | 77 | + .word 0x00DCF779 @ R2: PWRCON(4)
|
| | 78 | + .word 0x003E3E00 @ R3
|
| | 79 | + .word 0x06008501 @ R4
|
| | 80 | + .word 0x00009DBC @ R5
|
| | 81 | + .word 0x00404040 @ R6
|
| | 82 | + .word 0x40001000 @ R7
|
| | 83 | + .word 0x80008000 @ R8
|
| | 84 | + .word 0x38501000 @ R9
|
| | 85 | + .word 0xE02BED4D @ R10: PWRCON(1) during timer setup
|
| | 86 | + .word 0x001CF700 @ R11: PWRCON(4) during timer setup
|
| | 87 | + .word 0x3C500000 @ R12: SYSCON base address
|
| | 88 | + @ R13: Constant pool pointer
|
| | 89 | +.endm @ R14: 0
|
| | 90 | +
|
| | 91 | + ldmia sp!, {r0-r12}
|
| | 92 | + str r0, [r12,#0x48] @ PWRCON0 ... @ R0: Scratchpad
|
| | 93 | + str r1, [r12,#0x4c]
|
| | 94 | + mov r0, #0x73
|
| | 95 | + str r0, [r12,#0x58]
|
| | 96 | + mov r0, #0xff
|
| | 97 | + str r0, [r12,#0x68]
|
| | 98 | + str r2, [r12,#0x6c] @ ... PWRCON4
|
| | 99 | + str lr, [r12]
|
| | 100 | +sysconwait1:
|
| | 101 | + ldr r0, [r12]
|
| | 102 | + tst r0, #0xf
|
| | 103 | + bne sysconwait1 @ while ([SYSCON] & 0xf)
|
| | 104 | +
|
| | 105 | + str lr, [r12,#0x04]
|
| | 106 | +sysconwait2:
|
| | 107 | + ldr r0, [r12,#0x04]
|
| | 108 | + tst r0, r3
|
| | 109 | + bne sysconwait2 @ while ([SYSCON+4] & 0x003E3E00)
|
| | 110 | +
|
| | 111 | + mov r0, #0x7
|
| | 112 | + str r0, [r12,#0x44]
|
| | 113 | + str lr, [r12,#0x44]
|
| | 114 | + str lr, [r12,#0x3c]
|
| | 115 | + str r4, [r12,#0x20] @ R4: Scratchpad
|
| | 116 | + str r5, [r12,#0x30]
|
| | 117 | + mov r5, #1 @ R5: 1
|
| | 118 | + str r5, [r12,#0x44]
|
| | 119 | + orr r4, r0, #0x10000
|
| | 120 | + str r4, [r12,#0x44]
|
| | 121 | +sysconwait3:
|
| | 122 | + ldr r4, [r12,#0x40]
|
| | 123 | + tst r4, #0x1
|
| | 124 | + beq sysconwait3 @ while (!([SYSCON+0x40] & 1))
|
| | 125 | +
|
| | 126 | + str r6, [r12,#0x04] @ R6: Unused
|
| | 127 | + add r3, r3, #0x3e @ R3: 0x003E3E3E
|
| | 128 | +sysconwait4:
|
| | 129 | + ldr r4, [r12,#0x04]
|
| | 130 | + tst r4, r3 @ R3: Unused
|
| | 131 | + bne sysconwait4
|
| | 132 | +
|
| | 133 | + str r7, [r12] @ R7: Unused
|
| | 134 | +sysconwait5:
|
| | 135 | + ldr r2, [r12]
|
| | 136 | + tst r4, #0xf
|
| | 137 | + bne sysconwait5
|
| | 138 | +
|
| | 139 | + str r8, [r12,#0x08]
|
| | 140 | + orr r4, r8, r8,lsr#1 @ R8: Unused
|
| | 141 | + str r4, [r12,#0x0c]
|
| | 142 | + mov r4, #0xc000
|
| | 143 | + str r4, [r12,#0x10]
|
| | 144 | + mov r4, #0x8000
|
| | 145 | + str r4, [r12,#0x14]
|
| | 146 | + str r4, [r12,#0x70]
|
| | 147 | + mov r4, #2
|
| | 148 | + str r4, [r9] @ R9: Unused
|
| | 149 | + mov r0, #0x10 @ R5: 0x10
|
| | 150 | +
|
| | 151 | + @ Block 2 (TIMER) register map:
|
| | 152 | + @ R0: 1
|
| | 153 | + @ R1: PWRCON(1)
|
| | 154 | + @ R2: PWRCON(4)
|
| | 155 | + @ R3: Scratchpad
|
| | 156 | + @ R4: Scratchpad
|
| | 157 | + @ R5: 0x10
|
| | 158 | + @ R6: Unused
|
| | 159 | + @ R7: Unused
|
| | 160 | + @ R8: Unused
|
| | 161 | + @ R9: Unused
|
| | 162 | + @ R10: PWRCON(1) during timer setup
|
| | 163 | + @ R11: PWRCON(4) during timer setup
|
| | 164 | + @ R12: SYSCON base address
|
| | 165 | + @ R13: Constant pool pointer
|
| | 166 | + @ R14: 0
|
| | 167 | +
|
| | 168 | + str r10, [r12,#0x4c] @ PWRCON(1) for timer setup @ R10: Unused
|
| | 169 | + mov r4, #0x13
|
| | 170 | + str r4, [r12,#0x58] @ PWRCON(2) for timer setup
|
| | 171 | + str r11, [r12,#0x6c] @ PWRCON(4) for timer setup @ R11: Unused
|
| | 172 | + orr r11, r12, #0x00200000 @ R11: TIMER base address
|
| | 173 | + str r0, [r11,#0x4] @ TACMD = 0x10
|
| | 174 | + str r0, [r11,#0x24] @ TBCMD = 0x10
|
| | 175 | + str r0, [r11,#0x44] @ TCCMD = 0x10
|
| | 176 | + str r0, [r11,#0x64] @ TDCMD = 0x10
|
| | 177 | + mov r3, #0x40
|
| | 178 | + str r3, [r11,#0xa0] @ TECON = 0x40
|
| | 179 | + mov r3, #0xb
|
| | 180 | + str r3, [r11,#0xb0] @ TEPRE = 0xb
|
| | 181 | + mov r4, #-1 @ R4: -1
|
| | 182 | + str r4, [r11,#0xa8] @ TEDATA0 = 0xFFFFFFFF
|
| | 183 | + mov r3, #0x3
|
| | 184 | + str r3, [r11,#0xa4] @ TECMD = 0x3
|
| | 185 | + str r0, [r11,#0xc4] @ TFCMD = 0x10
|
| | 186 | + str r0, [r11,#0xe4] @ TGCMD = 0x10
|
| | 187 | + str r0, [r11,#0x104] @ THCMD = 0x10
|
| | 188 | + str r4, [r11,#0x118] @ THCMD = 0xFFFFFFFF
|
| | 189 | + str r1, [r12,#0x4c] @ PWRCON(1) @ R1: Unused
|
| | 190 | + mov r3, #0x73
|
| | 191 | + str r3, [r12,#0x58] @ PWRCON(2)
|
| | 192 | + str r2, [r12,#0x6c] @ PWRCON(4) @ R2: Unused
|
| | 193 | + orr r10, r11, #0x00800000 @ R10: GPIO base address
|
| | 194 | +
|
| | 195 | + @ Block 3 (GPIO) register map:
|
| | 196 | + @ R0: Unused
|
| | 197 | + @ R1: Unused
|
| | 198 | + @ R2: Unused
|
| | 199 | + @ R3: Scratchpad
|
| | 200 | + @ R4: -1
|
| | 201 | + @ R5: 1
|
| | 202 | + @ R6: Unused
|
| | 203 | + @ R7: Unused
|
| | 204 | + @ R8: Unused
|
| | 205 | + @ R9: Unused
|
| | 206 | + @ R10: GPIO base address
|
| | 207 | + @ R11: TIMER base address
|
| | 208 | + @ R12: SYSCON base address
|
| | 209 | + @ R13: Constant pool pointer
|
| | 210 | + @ R14: 0
|
| | 211 | +
|
| | 212 | +.macro gpio_initdata
|
| | 213 | + .word 0x3202EEEE @ PCON0
|
| | 214 | + .word 0xE0EE2253 @ PCON1
|
| | 215 | + .word 0x2223EEEE @ PCON2
|
| | 216 | + .word 0x33333332 @ PCON3
|
| | 217 | + .word 0xFF333E33 @ PCON4
|
| | 218 | + .word 0xE0FEE200 @ PCON5
|
| | 219 | + .word 0x2222222E @ PCON6
|
| | 220 | + .word 0x22222222 @ PCON7
|
| | 221 | + .word 0xEEEEEEE2 @ PCON8
|
| | 222 | + .word 0xEEE0EEEE @ PCON9
|
| | 223 | + .word 0x2EEEEEEE @ PCONA
|
| | 224 | + .word 0xEEEE0222 @ PCONB
|
| | 225 | + .word 0xEEEEE00E @ PCONC
|
| | 226 | + .word 0xEEEEEEEE @ PCOND
|
| | 227 | + .word 0xEEEEEEEE @ PCONE
|
| | 228 | +.endm
|
| | 229 | +
|
| | 230 | + ldr r3, [sp], #0x4
|
| | 231 | + str r3, [r10], #0xc @ R10: PCONx iterator
|
| | 232 | + mov r3, #0x20
|
| | 233 | + str r3, [r10], #0x4 @ PCON0 + 0xc = 0x20
|
| | 234 | + mov r3, #0x40
|
| | 235 | + str r3, [r10], #0x10 @ PCON0 + 0x10 = 0x40
|
| | 236 | + add r9, r10, #0x1a0 @ R9: Iterator limit
|
| | 237 | +gpioloop1:
|
| | 238 | + ldr r3, [sp], #0x4
|
| | 239 | + str r3, [r10], #0xc
|
| | 240 | + str lr, [r10], #0x4 @ PCON + 0xc = 0
|
| | 241 | + str lr, [r10], #0x10 @ PCON + 0x10 = 0
|
| | 242 | + cmp r10, r9
|
| | 243 | + bls gpioloop1
|
| | 244 | + @ R10: 0x3CF001E0
|
| | 245 | + ldr r3, [r10,#0x1a8]
|
| | 246 | + bic r3, r3, #2
|
| | 247 | + orr r3, r3, #1
|
| | 248 | + str r3, [r10,#0x1a8]
|
| | 249 | + sub r8, r11, #0x00300000 @ R8: 0x39700000 (iterator)
|
| | 250 | + mov r9, #6 @ R9: Iterations remaining
|
| | 251 | +gpioloop2:
|
| | 252 | + str r14, [r8,#0x80]
|
| | 253 | + str r4, [r8,#0xa0]
|
| | 254 | + str r14, [r8,#0xc0]
|
| | 255 | + str r14, [r8,#0xe0]
|
| | 256 | + add r8, r8, #4
|
| | 257 | + subs r9, r9, #1
|
| | 258 | + bne gpioloop2
|
| | 259 | + @ R9: 0
|
| | 260 | + ldr r8, [r10,#-0x180] @ R8: PCON3 backup
|
| | 261 | + and r3, r8, #0xff
|
| | 262 | + str r3, [r10,#-0x180] @ *PCON3 &= 0xff
|
| | 263 | + mov r0, #0x3e8 @ R0: Scratchpad
|
| | 264 | + bl udelay @ R14: Return address
|
| | 265 | + ldr r3, [r10,#-0x17c]
|
| | 266 | + and r3, r3, #0xfc
|
| | 267 | + mov r6, r3, lsr #0x2 @ R6: Data for first PMU access
|
| | 268 | + str r8, [r10,#-0x180]
|
| | 269 | + bic r10, r11, #0x00100000 @ R10: I2C base address
|
| | 270 | +
|
| | 271 | + @ Block 4 (I2C) register map:
|
| | 272 | + @ R0: Scratchpad
|
| | 273 | + @ R1: Scratchpad
|
| | 274 | + @ R2: Unused
|
| | 275 | + @ R3: Unused
|
| | 276 | + @ R4: -1
|
| | 277 | + @ R5: 1
|
| | 278 | + @ R6: Data for first PMU access
|
| | 279 | + @ R7: Unused
|
| | 280 | + @ R8: Unused
|
| | 281 | + @ R9: 0
|
| | 282 | + @ R10: I2C base address
|
| | 283 | + @ R11: TIMER base address
|
| | 284 | + @ R12: SYSCON base address
|
| | 285 | + @ R13: Constant pool pointer
|
| | 286 | + @ R14: Return address / Scratchpad
|
| | 287 | +
|
| | 288 | + bl i2cwaitrdy
|
| | 289 | + mov r1, #0x40
|
| | 290 | + str r1, [r10,#0x08]
|
| | 291 | + bl i2cwaitrdy
|
| | 292 | + str r5, [r10,#0x14]
|
| | 293 | + bl i2cwaitrdy
|
| | 294 | + str r9, [r10,#0x18]
|
| | 295 | + bl i2cwaitrdy
|
| | 296 | + mov r0, #0x80
|
| | 297 | + str r0, [r10,#0x04]
|
| | 298 | + bl i2cwaitrdy
|
| | 299 | + str r9, [r10]
|
| | 300 | + bl i2cwaitrdy
|
| | 301 | + str r9, [r10,#0x04]
|
| | 302 | + bl i2cwaitrdy
|
| | 303 | + str r1, [r10,#0x0c]
|
| | 304 | + bl i2cwaitrdy
|
| | 305 | + orr r0, r5, #0x180
|
| | 306 | + str r0, [r10]
|
| | 307 | + bl i2cwaitrdy
|
| | 308 | + mov r0, #0x10
|
| | 309 | + str r0, [r10,#0x04]
|
| | 310 | + bl i2cwaitrdy
|
| | 311 | +
|
| | 312 | + @ Block 5 (PMU) register map:
|
| | 313 | + @ R0: Address / Scratchpad (trashed by pmubatch)
|
| | 314 | + @ R1: Data / Scratchpad (trashed by pmubatch)
|
| | 315 | + @ R2: Scratchpad (set to 0xb7 by pmu accesses)
|
| | 316 | + @ R3: Scratchpad (set to 0x10 by pmu accesses)
|
| | 317 | + @ R4: Scratchpad (trashed by pmu accesses)
|
| | 318 | + @ R5: 1
|
| | 319 | + @ R6: Data for first PMU access
|
| | 320 | + @ R7: Scratchpad (trashed by pmubatch)
|
| | 321 | + @ R8: Used to store warmboot flag
|
| | 322 | + @ R9: 0 / pmubatch transfer count (reset to 0 by pmubatch)
|
| | 323 | + @ R10: I2C base address
|
| | 324 | + @ R11: TIMER base address
|
| | 325 | + @ R12: SYSCON base address
|
| | 326 | + @ R13: Constant pool / pmubatch data pointer
|
| | 327 | + @ R14: Return address / Scratchpad
|
| | 328 | +
|
| | 329 | + mov r0, #0x7f
|
| | 330 | + mov r1, r6
|
| | 331 | + bl pmuwrite
|
| | 332 | + mov r0, #0x02
|
| | 333 | + bl pmuread
|
| | 334 | + ands r8, r1, #0x80 @ R8: Warmboot flag
|
| | 335 | + beq pmu_coldboot
|
| | 336 | + mov r1, #0x80
|
| | 337 | + bl pmuwrite
|
| | 338 | +pmu_coldboot:
|
| | 339 | +.macro pmu_batch_1
|
| | 340 | +pmu_batch_1_begin:
|
| | 341 | + .byte 0x14, 0x13
|
| | 342 | + .byte 0x15, 0x0d
|
| | 343 | + .byte 0x0b, 0x22
|
| | 344 | +pmu_batch_1_end:
|
| | 345 | +.endm
|
| | 346 | + mov r9, #(pmu_batch_1_end - pmu_batch_1_begin) / 2
|
| | 347 | + bl pmubatch
|
| | 348 | + tst r6, #1 @ R6: Unused
|
| | 349 | + beq pmu_skip
|
| | 350 | + mov r0, #0x0d
|
| | 351 | + bl pmuread
|
| | 352 | + and r1, r1, #0xdf
|
| | 353 | + bl pmuwrite
|
| | 354 | +pmu_skip:
|
| | 355 | +.macro pmu_batch_2
|
| | 356 | +pmu_batch_2_begin:
|
| | 357 | + .byte 0x1f, 0x14
|
| | 358 | + .byte 0x1a, 0xb2
|
| | 359 | + .byte 0x1a, 0xb2
|
| | 360 | + .byte 0x19, 0x14
|
| | 361 | + .byte 0x21, 0x06
|
| | 362 | + .byte 0x1d, 0x12
|
| | 363 | +pmu_batch_2_end:
|
| | 364 | +.endm
|
| | 365 | + mov r9, #(pmu_batch_2_end - pmu_batch_2_begin) / 2
|
| | 366 | + bl pmubatch
|
| | 367 | + mov r0, #0x10
|
| | 368 | + bl pmuread
|
| | 369 | + bic r1, r1, #0x80
|
| | 370 | + orr r1, r1, #0x60
|
| | 371 | +nop@ bl pmuwrite
|
| | 372 | +.macro pmu_batch_3
|
| | 373 | +pmu_batch_3_begin:
|
| | 374 | + .byte 0x44, 0x72
|
| | 375 | +pmu_batch_3_end:
|
| | 376 | +.endm
|
| | 377 | + mov r9, #(pmu_batch_3_end - pmu_batch_3_begin) / 2
|
| | 378 | + bl pmubatch
|
| | 379 | + mov r0, #0x40
|
| | 380 | + bl pmuread
|
| | 381 | + orr r1, r1, #0x40
|
| | 382 | + bl pmuwrite
|
| | 383 | + mov r0, #0x33
|
| | 384 | + bl pmuread
|
| | 385 | + and r1, r1, #0x03
|
| | 386 | + orr r1, r1, #0x50
|
| | 387 | + bl pmuwrite
|
| | 388 | + mov r0, #0x34
|
| | 389 | + bl pmuread
|
| | 390 | + and r1, r1, #0x80
|
| | 391 | + orr r1, r1, #0x54
|
| | 392 | + bl pmuwrite
|
| | 393 | +.macro pmu_batch_4
|
| | 394 | +pmu_batch_4_begin:
|
| | 395 | + .byte 0x22, 0x00
|
| | 396 | + .byte 0x07, 0x50
|
| | 397 | + .byte 0x08, 0xfe
|
| | 398 | + .byte 0x09, 0x2b
|
| | 399 | + .byte 0x01, 0xff
|
| | 400 | + .byte 0x02, 0xff
|
| | 401 | + .byte 0x03, 0xff
|
| | 402 | +pmu_batch_4_end:
|
| | 403 | +.endm
|
| | 404 | + mov r9, #(pmu_batch_4_end - pmu_batch_4_begin) / 2
|
| | 405 | + bl pmubatch
|
| | 406 | + cmp r8, #0
|
| | 407 | + bne pmu_warmboot
|
| | 408 | + mov r0, #0x30
|
| | 409 | + mov r1, #0x64
|
| | 410 | + bl pmuwrite
|
| | 411 | +pmu_warmboot:
|
| | 412 | + mov r0, #0x31
|
| | 413 | + bl pmuread
|
| | 414 | + bic r1, r1, #0x01
|
| | 415 | + bl pmuwrite
|
| | 416 | +.macro pmu_batch_5
|
| | 417 | +pmu_batch_5_begin:
|
| | 418 | + .byte 0x0a, 0x70
|
| | 419 | + .byte 0x13, 0x02
|
| | 420 | +pmu_batch_5_end:
|
| | 421 | +.endm
|
| | 422 | + mov r9, #(pmu_batch_5_end - pmu_batch_5_begin) / 2
|
| | 423 | + bl pmubatch
|
| | 424 | +
|
| | 425 | + orr lr, r11, #0x00800000 @ R14: GPIO base address
|
| | 426 | + str r9, [lr,#0x384]
|
| | 427 | + orr lr, r11, #0x01000000 @ R14: MIU base address
|
| | 428 | + str r5, [lr]
|
| | 429 | + ldrh r0, [sp], #2
|
| | 430 | + str r0, [lr,#0x100]
|
| | 431 | + mov r0, #0xff
|
| | 432 | + str r0, [lr,#0x11c]
|
| | 433 | + str r0, [lr,#0x120]
|
| | 434 | +
|
| | 435 | +.macro block6_constpool @ Block 6 (SDRAM) register map:
|
| | 436 | + .hword 0x1030
|
| | 437 | + .word 0x008AAC25 @ R0
|
| | 438 | + .word 0x050D67E5 @ R1
|
| | 439 | + .word 0x0002000B @ R2
|
| | 440 | + .word 0x0003B3B2 @ R3
|
| | 441 | + .word 0xFF53B3B0 @ R4
|
| | 442 | + .word 0x00008040 @ R5
|
| | 443 | + .word 0x8000100F @ R6: For LCD init at end of block
|
| | 444 | + .word 0x41100DB8 @ R7: For LCD init at end of block
|
| | 445 | + @ R8: Warmboot flag
|
| | 446 | + @ R9: 0
|
| | 447 | + @ R10: I2C base address
|
| | 448 | + @ R11: TIMER base address
|
| | 449 | + @ R12: SYSCON base address
|
| | 450 | + @ R13: Constant pool pointer
|
| | 451 | +.endm @ R14: MIU base address
|
| | 452 | +
|
| | 453 | + ldmia sp!, {r0-r7}
|
| | 454 | + str r0, [lr,#0x114] @ R0: Unused
|
| | 455 | + str r1, [lr,#0x124] @ R1: Unused
|
| | 456 | + mov r0, #0x18 @ R0: Scratchpad
|
| | 457 | + str r0, [lr,#0x118]
|
| | 458 | + str r2, [lr,#0x108]
|
| | 459 | + mov r0, #4
|
| | 460 | + str r0, [lr,#0x148]
|
| | 461 | + str r9, [lr,#0x14c]
|
| | 462 | + str r3, [lr,#0x140]
|
| | 463 | +miu_wait1:
|
| | 464 | + ldr r0, [lr,#0x140]
|
| | 465 | + tst r0, #2
|
| | 466 | + beq miu_wait1
|
| | 467 | + add r0, r3, #1 @ R3: Unused
|
| | 468 | + str r0, [lr,#0x140]
|
| | 469 | +miu_wait2:
|
| | 470 | + ldr r0, [lr,#0x144]
|
| | 471 | + mvn r0, r0
|
| | 472 | + tst r0, #3
|
| | 473 | + bne miu_wait2
|
| | 474 | + ldr r1, [lr,#0x144] @ R1: Scratchpad
|
| | 475 | + mov r0, #0x0ff00000
|
| | 476 | + and r0, r0, r1, lsl #0x2
|
| | 477 | + add r0, r0, r4 @ R4: Unused
|
| | 478 | + str r0, [lr,#0x140]
|
| | 479 | + mov r0, #0x10
|
| | 480 | + str r0, [lr,#0x150]
|
| | 481 | + cmp r8, #0 @ R8: Unused
|
| | 482 | + sub r8, r10, #0x04300000 @ R8: LCD base address
|
| | 483 | + str r6, [r12,#0x08] @ R6: Unused
|
| | 484 | + str r7, [r8] @ R7: Unused
|
| | 485 | + mov r0, #0x11
|
| | 486 | + str r0, [r8,#0x20]
|
| | 487 | + mov r3, #0x33 @ R3: 0x33
|
| | 488 | + beq miu_coldboot
|
| | 489 | + str r0, [lr,#0x104]
|
| | 490 | + b miu_common
|
| | 491 | +miu_coldboot:
|
| | 492 | + str r3, [lr,#0x104]
|
| | 493 | + orr r0, r3, #0x200
|
| | 494 | + str r0, [lr,#0x104]
|
| | 495 | +miu_wait3:
|
| | 496 | + ldr r0, [lr,#0x104]
|
| | 497 | + tst r0, #0x110000
|
| | 498 | + bne miu_wait3
|
| | 499 | + str r3, [lr,#0x104]
|
| | 500 | + str r3, [lr,#0x104]
|
| | 501 | + str r3, [lr,#0x104]
|
| | 502 | + orr r1, r3, #0x300
|
| | 503 | + str r1, [lr,#0x104]
|
| | 504 | +miu_wait4:
|
| | 505 | + ldr r0, [lr,#0x104]
|
| | 506 | + tst r0, #0x110000
|
| | 507 | + bne miu_wait4
|
| | 508 | + str r3, [lr,#0x104]
|
| | 509 | + str r3, [lr,#0x104]
|
| | 510 | + str r3, [lr,#0x104]
|
| | 511 | + str r1, [lr,#0x104]
|
| | 512 | +miu_wait5:
|
| | 513 | + ldr r0, [lr,#0x104]
|
| | 514 | + tst r0, #0x110000
|
| | 515 | + bne miu_wait5
|
| | 516 | + str r3, [lr,#0x104]
|
| | 517 | + str r3, [lr,#0x104]
|
| | 518 | + str r3, [lr,#0x104]
|
| | 519 | + str r3, [lr,#0x110]
|
| | 520 | + orr r1, r3, #0x100
|
| | 521 | + str r1, [lr,#0x104]
|
| | 522 | +miu_wait6:
|
| | 523 | + ldr r0, [lr,#0x104]
|
| | 524 | + tst r0, #0x110000
|
| | 525 | + bne miu_wait6
|
| | 526 | + str r3, [lr,#0x104]
|
| | 527 | + str r3, [lr,#0x104]
|
| | 528 | + str r3, [lr,#0x104]
|
| | 529 | + str r5, [lr,#0x110] @ R5: Unused
|
| | 530 | + str r1, [lr,#0x104]
|
| | 531 | +miu_wait7:
|
| | 532 | + ldr r0, [lr,#0x104]
|
| | 533 | + tst r0, #0x110000
|
| | 534 | + bne miu_wait7
|
| | 535 | + str r3, [lr,#0x104]
|
| | 536 | + str r3, [lr,#0x104]
|
| | 537 | +miu_common:
|
| | 538 | + str r3, [lr,#0x104] @ R3: Unused
|
| | 539 | + mov r0, #0x40
|
| | 540 | + str r0, [lr,#0x10c]
|
| | 541 | + ldr r0, [lr,#0x100]
|
| | 542 | + orr r0, r0, #0x9100000
|
| | 543 | + str r0, [lr,#0x100]
|
| | 544 | + mov r0, #0x19
|
| | 545 | + str r0, [lr,#0x11c]
|
| | 546 | + mov r0, #1
|
| | 547 | + str r0, [lr,#0x120]
|
| | 548 | + orr r1, r2, #0x1000 @ R2: Unused
|
| | 549 | + str r1, [lr,#0x108]
|
| | 550 | + str r0, [lr,#0x08]
|
| | 551 | + mov r1, #0x3e000000
|
| | 552 | + mov r0, #0x1f
|
| | 553 | + str r0, [r1,#0x08]
|
| | 554 | +
|
| | 555 | + @ Block 7 (LCD) register map:
|
| | 556 | + @ R0: Cmd/Data to be written / Scratchpad
|
| | 557 | + @ R1: Scratchpad
|
| | 558 | + @ R2: Scratchpad
|
| | 559 | + @ R3: Scratchpad
|
| | 560 | + @ R4: Scratchpad
|
| | 561 | + @ R5: Scratchpad
|
| | 562 | + @ R6: Unused
|
| | 563 | + @ R7: Unused
|
| | 564 | + @ R8: LCD base address
|
| | 565 | + @ R9: 0
|
| | 566 | + @ R10: I2C base address
|
| | 567 | + @ R11: TIMER base address
|
| | 568 | + @ R12: SYSCON base address
|
| | 569 | + @ R13: LCD init script pointer / Scratchpad
|
| | 570 | + @ R14: Return address / Scratchpad
|
| | 571 | +
|
| | 572 | +.macro lcd_sequences
|
| | 573 | +lcd_sequences_begin:
|
| | 574 | + .word lcd_sequence_c4 - lcd_sequences_begin
|
| | 575 | + .word lcd_sequence_d5 - lcd_sequences_begin
|
| | 576 | + .word lcd_sequence_e6 - lcd_sequences_begin
|
| | 577 | + .word lcd_sequence_b3 - lcd_sequences_begin
|
| | 578 | +lcd_sequence_b3:
|
| | 579 | + .byte 0x01, 0x11
|
| | 580 | + .byte 0xf8
|
| | 581 | + .byte 0x02, 0xfe, 0x00
|
| | 582 | + .byte 0x02, 0xef, 0x80
|
| | 583 | + .byte 0x02, 0xc0, 0x0c
|
| | 584 | + .byte 0x02, 0xc1, 0x03
|
| | 585 | + .byte 0x03, 0xc2, 0x12, 0x00
|
| | 586 | + .byte 0x03, 0xc3, 0x12, 0x00
|
| | 587 | + .byte 0x03, 0xc4, 0x12, 0x00
|
| | 588 | + .byte 0x03, 0xc5, 0x3a, 0x3e
|
| | 589 | + .byte 0x03, 0xb1, 0x6a, 0x15
|
| | 590 | + .byte 0x03, 0xb2, 0x5f, 0x3f
|
| | 591 | + .byte 0x03, 0xb3, 0x5f, 0x3f
|
| | 592 | + .byte 0x02, 0xb4, 0x02
|
| | 593 | + .byte 0x03, 0xb6, 0x12, 0x02
|
| | 594 | + .byte 0x02, 0x35, 0x00
|
| | 595 | + .byte 0x02, 0x26, 0x10
|
| | 596 | + .byte 0x0c, 0xe0, 0x0f, 0x42, 0x24, 0x01, 0x00, 0x02, 0xa6, 0x98, 0x05, 0x04, 0x15
|
| | 597 | + .byte 0x0c, 0xe1, 0x00, 0x21, 0x44, 0x02, 0x0f, 0x05, 0x89, 0x6a, 0x02, 0x15, 0x04
|
| | 598 | + .byte 0x0c, 0xe2, 0x7e, 0x04, 0x43, 0x40, 0x00, 0x02, 0x13, 0x00, 0x00, 0x01, 0x0b
|
| | 599 | + .byte 0x0c, 0xe3, 0x40, 0x40, 0x03, 0x74, 0x0e, 0x00, 0x00, 0x31, 0x02, 0x0b, 0x01
|
| | 600 | + .byte 0x0c, 0xe4, 0x5a, 0x43, 0x67, 0x56, 0x00, 0x02, 0x67, 0x72, 0x00, 0x05, 0x12
|
| | 601 | + .byte 0x0c, 0xe5, 0x50, 0x66, 0x47, 0x53, 0x0a, 0x00, 0x27, 0x76, 0x02, 0x12, 0x02
|
| | 602 | + .byte 0x02, 0x3a, 0x06
|
| | 603 | + .byte 0x01, 0x13
|
| | 604 | + .byte 0x01, 0x29
|
| | 605 | + .byte 0x80
|
| | 606 | +lcd_sequence_c4:
|
| | 607 | + .byte 0x01, 0x01
|
| | 608 | + .byte 0x85
|
| | 609 | + .byte 0x02, 0xc0, 0x00
|
| | 610 | + .byte 0x02, 0xc1, 0x03
|
| | 611 | + .byte 0x02, 0xc2, 0x34
|
| | 612 | + .byte 0x03, 0xc3, 0x72, 0x03
|
| | 613 | + .byte 0x03, 0xc4, 0x73, 0x03
|
| | 614 | + .byte 0x03, 0xc5, 0x3c, 0x3c
|
| | 615 | + .byte 0x02, 0xfe, 0x00
|
| | 616 | +@ .byte 0x03, 0xb1, 0x6a, 0x15
|
| | 617 | + .byte 0x03, 0xb2, 0x6a, 0x15
|
| | 618 | + .byte 0x03, 0xb3, 0x6a, 0x15
|
| | 619 | + .byte 0x02, 0xb4, 0x02
|
| | 620 | + .byte 0x03, 0xb6, 0x12, 0x02
|
| | 621 | + .byte 0x02, 0x35, 0x00
|
| | 622 | + .byte 0x02, 0x26, 0x10
|
| | 623 | + .byte 0x0c, 0xe0, 0x77, 0x52, 0x76, 0x53, 0x03, 0x03, 0x57, 0x42, 0x10, 0x18, 0x09
|
| | 624 | + .byte 0x0c, 0xe1, 0x0d, 0x00, 0x23, 0x66, 0x0f, 0x15, 0x4d, 0x85, 0x08, 0x02, 0x10
|
| | 625 | + .byte 0x0c, 0xe2, 0x39, 0x60, 0x77, 0x05, 0x03, 0x07, 0x96, 0x64, 0x0d, 0x1a, 0x0a
|
| | 626 | + .byte 0x0c, 0xe3, 0x3f, 0x10, 0x16, 0x44, 0x0e, 0x04, 0x6c, 0x44, 0x04, 0x03, 0x0b
|
| | 627 | + .byte 0x0c, 0xe4, 0x00, 0x61, 0x77, 0x04, 0x02, 0x04, 0x72, 0x32, 0x09, 0x19, 0x06
|
| | 628 | + .byte 0x0c, 0xe5, 0x4f, 0x42, 0x27, 0x67, 0x0f, 0x02, 0x26, 0x33, 0x01, 0x03, 0x09
|
| | 629 | +@ .byte 0x02, 0x3a, 0x66
|
| | 630 | + .byte 0x02, 0x36, 0x00
|
| | 631 | + .byte 0x01, 0x11
|
| | 632 | + .byte 0x01, 0x29
|
| | 633 | + .byte 0x80
|
| | 634 | +lcd_sequence_d5:
|
| | 635 | + .byte 0x02, 0xfe, 0x00
|
| | 636 | + .byte 0x02, 0xc0, 0x01
|
| | 637 | + .byte 0x02, 0xc1, 0x01
|
| | 638 | + .byte 0x03, 0xc2, 0x03, 0x00
|
| | 639 | + .byte 0x03, 0xc3, 0x01, 0x00
|
| | 640 | + .byte 0x03, 0xc4, 0x03, 0x00
|
| | 641 | + .byte 0x03, 0xc5, 0x34, 0x34
|
| | 642 | + .byte 0x02, 0xc7, 0x00
|
| | 643 | + .byte 0x03, 0xb1, 0x6d, 0x15
|
| | 644 | + .byte 0x03, 0xb2, 0x6d, 0x15
|
| | 645 | + .byte 0x03, 0xb3, 0x6d, 0x15
|
| | 646 | + .byte 0x02, 0xb4, 0x03
|
| | 647 | + .byte 0x03, 0xb6, 0x11, 0x02
|
| | 648 | + .byte 0x02, 0x35, 0x00
|
| | 649 | + .byte 0x02, 0x26, 0x10
|
| | 650 | + .byte 0x0c, 0xe0, 0x23, 0x42, 0x20, 0x42, 0x0e, 0x01, 0xf5, 0xeb, 0x1e, 0x05, 0x18
|
| | 651 | + .byte 0x0c, 0xe1, 0x5f, 0x22, 0x36, 0x21, 0x03, 0x1e, 0xfe, 0x7b, 0x02, 0x07, 0x18
|
| | 652 | + .byte 0x0c, 0xe2, 0x5f, 0x34, 0x53, 0x77, 0x0a, 0x00, 0x70, 0xf4, 0x14, 0x06, 0x0f
|
| | 653 | + .byte 0x0c, 0xe3, 0x0f, 0x23, 0x31, 0x54, 0x0f, 0x0b, 0x8e, 0x08, 0x00, 0x05, 0x15
|
| | 654 | + .byte 0x0c, 0xe4, 0x5f, 0x33, 0x42, 0x14, 0x0e, 0x04, 0xa6, 0xf7, 0x0e, 0x00, 0x14
|
| | 655 | + .byte 0x0c, 0xe5, 0x0c, 0x43, 0x44, 0x44, 0x0d, 0x0d, 0x7f, 0x39, 0x03, 0x02, 0x10
|
| | 656 | + .byte 0x02, 0x3a, 0x66
|
| | 657 | + .byte 0x02, 0x36, 0x00
|
| | 658 | + .byte 0x01, 0x11
|
| | 659 | + .byte 0x01, 0x29
|
| | 660 | + .byte 0x80
|
| | 661 | +lcd_sequence_e6:
|
| | 662 | + .byte 0x01, 0x11
|
| | 663 | + .byte 0xf8
|
| | 664 | + .byte 0x02, 0xfe, 0x00
|
| | 665 | + .byte 0x02, 0xef, 0x80
|
| | 666 | + .byte 0x02, 0xc0, 0x13
|
| | 667 | + .byte 0x02, 0xc1, 0x03
|
| | 668 | + .byte 0x03, 0xc2, 0x12, 0x00
|
| | 669 | + .byte 0x03, 0xc3, 0x12, 0x00
|
| | 670 | + .byte 0x03, 0xc4, 0x12, 0x00
|
| | 671 | + .byte 0x03, 0xc5, 0x2a, 0x3c
|
| | 672 | + .byte 0x03, 0xb1, 0x6a, 0x15
|
| | 673 | + .byte 0x03, 0xb2, 0x5f, 0x3f
|
| | 674 | + .byte 0x03, 0xb3, 0x5f, 0x3f
|
| | 675 | + .byte 0x02, 0xb4, 0x02
|
| | 676 | + .byte 0x03, 0xb6, 0x12, 0x02
|
| | 677 | + .byte 0x02, 0x35, 0x00
|
| | 678 | + .byte 0x02, 0x26, 0x10
|
| | 679 | + .byte 0x0c, 0xe0, 0x0f, 0x53, 0x45, 0x07, 0x00, 0x00, 0xb9, 0xf6, 0x08, 0x04, 0x18
|
| | 680 | + .byte 0x0c, 0xe1, 0x00, 0x47, 0x55, 0x03, 0x0f, 0x08, 0x6f, 0x9b, 0x00, 0x18, 0x04
|
| | 681 | + .byte 0x0c, 0xe2, 0x7e, 0x03, 0x54, 0x75, 0x00, 0x00, 0x3a, 0x52, 0x03, 0x02, 0x10
|
| | 682 | + .byte 0x0c, 0xe3, 0x70, 0x55, 0x04, 0x73, 0x0e, 0x03, 0x25, 0xa3, 0x00, 0x10, 0x02
|
| | 683 | + .byte 0x0c, 0xe4, 0x1a, 0x72, 0x33, 0x76, 0x00, 0x00, 0xeb, 0x97, 0x03, 0x05, 0x17
|
| | 684 | + .byte 0x0c, 0xe5, 0x70, 0x36, 0x73, 0x12, 0x0a, 0x03, 0x79, 0xbe, 0x00, 0x17, 0x05
|
| | 685 | + .byte 0x02, 0x3a, 0x06
|
| | 686 | + .byte 0x01, 0x13
|
| | 687 | + .byte 0x01, 0x29
|
| | 688 | + .byte 0x80
|
| | 689 | +lcd_sequences_end:
|
| | 690 | +.endm
|
| | 691 | +
|
| | 692 | + mov r0, #4
|
| | 693 | + bl sendlcdc
|
| | 694 | + bl readlcd
|
| | 695 | + bl readlcd
|
| | 696 | + bl readlcd
|
| | 697 | + and r0, r0, #3
|
| | 698 | + ldr r0, [sp,r0,lsl#2]
|
| | 699 | + add sp, sp, r0
|
| | 700 | +lcdloop:
|
| | 701 | + ldrb r1, [sp], #1
|
| | 702 | + tst r1, #0x80
|
| | 703 | + beq lcddata
|
| | 704 | + bics r1, r1, #0x80
|
| | 705 | + beq lcddone
|
| | 706 | + mov r0, r1,lsl#10
|
| | 707 | + bl udelay
|
| | 708 | + b lcdloop
|
| | 709 | +lcddata:
|
| | 710 | + ldrb r0, [sp], #1
|
| | 711 | + bl sendlcdc
|
| | 712 | +lcdbyte:
|
| | 713 | + subs r1, r1, #1
|
| | 714 | + beq lcdloop
|
| | 715 | + ldrb r0, [sp], #1
|
| | 716 | + bl sendlcdd
|
| | 717 | + b lcdbyte
|
| | 718 | +
|
| | 719 | + @ udelay register map:
|
| | 720 | + @ R0: Microseconds
|
| | 721 | + @ R1: Trashed
|
| | 722 | + @ R11: TIMER base address
|
| | 723 | + @ R14: Return address
|
| | 724 | +
|
| | 725 | +udelay:
|
| | 726 | + ldr r1, [r11,#0xb4]
|
| | 727 | + add r0, r0, r1
|
| | 728 | +udelayloop:
|
| | 729 | + ldr r1, [r11,#0xb4]
|
| | 730 | + cmp r1, r0
|
| | 731 | + bmi udelayloop
|
| | 732 | + mov pc, lr
|
| | 733 | +
|
| | 734 | + @ i2cwaitrdy register map:
|
| | 735 | + @ R9: Set to 0
|
| | 736 | + @ R10: I2C base address
|
| | 737 | + @ R14: Return address
|
| | 738 | +
|
| | 739 | +i2cwaitrdy:
|
| | 740 | + ldr r9, [r10,#0x10]
|
| | 741 | + cmp r9, #0
|
| | 742 | + bne i2cwaitrdy
|
| | 743 | + mov pc, lr
|
| | 744 | +
|
| | 745 | + @ i2cwait register map:
|
| | 746 | + @ R3: Set to 0x10
|
| | 747 | + @ R10: I2C base address
|
| | 748 | + @ R14: Return address
|
| | 749 | +
|
| | 750 | +i2cwait:
|
| | 751 | + ldr r3, [r10]
|
| | 752 | + ands r3, #0x10
|
| | 753 | + beq i2cwait
|
| | 754 | + mov pc, lr
|
| | 755 | +
|
| | 756 | + @ pmuwrite register map:
|
| | 757 | + @ R0: Address
|
| | 758 | + @ R1: Data
|
| | 759 | + @ R2: Set to 0xb7
|
| | 760 | + @ R3: Set to 0x10
|
| | 761 | + @ R4: Return address backup
|
| | 762 | + @ R10: I2C base address
|
| | 763 | + @ R14: Return address / Scratchpad
|
| | 764 | +
|
| | 765 | +pmuwrite:
|
| | 766 | + mov r4, lr
|
| | 767 | + mov lr, #0xe6
|
| | 768 | + str lr, [r10,#0x0c]
|
| | 769 | + mov lr, #0xf0
|
| | 770 | + str lr, [r10,#0x04]
|
| | 771 | + mov r2, #0xb7
|
| | 772 | + str r2, [r10]
|
| | 773 | + bl i2cwait
|
| | 774 | + str r0, [r10,#0x0c]
|
| | 775 | + str r2, [r10]
|
| | 776 | + bl i2cwait
|
| | 777 | + str r1, [r10,#0x0c]
|
| | 778 | + str r2, [r10]
|
| | 779 | + bl i2cwait
|
| | 780 | + mov lr, #0xd0
|
| | 781 | + str lr, [r10,#0x04]
|
| | 782 | + str r2, [r10]
|
| | 783 | +pmuwrite_wait:
|
| | 784 | + ldr lr, [r10,#0x04]
|
| | 785 | + tst lr, #0x20
|
| | 786 | + bne pmuwrite_wait
|
| | 787 | + mov pc, r4
|
| | 788 | +
|
| | 789 | + @ pmuread register map:
|
| | 790 | + @ R0: Address
|
| | 791 | + @ R1: Data
|
| | 792 | + @ R2: Set to 0xb7
|
| | 793 | + @ R3: Set to 0x10
|
| | 794 | + @ R4: Return address backup
|
| | 795 | + @ R10: I2C base address
|
| | 796 | + @ R14: Return address / Scratchpad
|
| | 797 | +
|
| | 798 | +pmuread:
|
| | 799 | + mov r4, lr
|
| | 800 | + mov lr, #0xe6
|
| | 801 | + str lr, [r10,#0x0c]
|
| | 802 | + mov lr, #0xf0
|
| | 803 | + str lr, [r10,#0x04]
|
| | 804 | + mov r2, #0xb7
|
| | 805 | + str r2, [r10]
|
| | 806 | + bl i2cwait
|
| | 807 | + str r0, [r10,#0x0c]
|
| | 808 | + str r2, [r10]
|
| | 809 | + bl i2cwait
|
| | 810 | + mov r1, #0xe7
|
| | 811 | + str r1, [r10,#0x0c]
|
| | 812 | + mov r1, #0xb0
|
| | 813 | + str r1, [r10,#0x04]
|
| | 814 | + str r2, [r10]
|
| | 815 | + bl i2cwait
|
| | 816 | + mov r1, #0x37
|
| | 817 | + str r1, [r10]
|
| | 818 | + bl i2cwait
|
| | 819 | + ldr r1, [r10,#0x0c]
|
| | 820 | + mov lr, #0x90
|
| | 821 | + str lr, [r10,#0x04]
|
| | 822 | + str r2, [r10]
|
| | 823 | +pmuread_wait:
|
| | 824 | + ldr r1, [r10,#0x04]
|
| | 825 | + tst r1, #0x20
|
| | 826 | + bne pmuread_wait
|
| | 827 | + mov pc, r4
|
| | 828 | +
|
| | 829 | + @ pmubatch register map:
|
| | 830 | + @ R0: Scratchpad
|
| | 831 | + @ R1: Scratchpad
|
| | 832 | + @ R2: Set to 0xb7
|
| | 833 | + @ R3: Set to 0x10
|
| | 834 | + @ R4: Inner return address backup
|
| | 835 | + @ R7: Outer return address backup
|
| | 836 | + @ R9: Number of address-data pairs to be sent (must be >0), will be reset to 0
|
| | 837 | + @ R10: I2C base address
|
| | 838 | + @ R13: Address-data pair list pointer (will be incremented)
|
| | 839 | + @ R14: Return address / Scratchpad
|
| | 840 | +
|
| | 841 | +pmubatch:
|
| | 842 | + mov r7, lr
|
| | 843 | +pmubatch_loop:
|
| | 844 | + ldrb r0, [sp], #1
|
| | 845 | + ldrb r1, [sp], #1
|
| | 846 | + bl pmuwrite
|
| | 847 | + subs r9, r9, #1
|
| | 848 | + bne pmubatch_loop
|
| | 849 | + mov pc, r7
|
| | 850 | +
|
| | 851 | + @ sendlcdc register map:
|
| | 852 | + @ R0: Command to be sent
|
| | 853 | + @ R8: LCD base address
|
| | 854 | + @ R9: Will be set to 0
|
| | 855 | + @ R14: Return address
|
| | 856 | +
|
| | 857 | +sendlcdc:
|
| | 858 | + ldr r9, [r8,#0x1c]
|
| | 859 | + ands r9, r9, #0x10
|
| | 860 | + bne sendlcdc
|
| | 861 | + str r0, [r8,#0x04]
|
| | 862 | + mov pc, lr
|
| | 863 | +
|
| | 864 | + @ sendlcdd register map:
|
| | 865 | + @ R0: Data to be sent
|
| | 866 | + @ R8: LCD base address
|
| | 867 | + @ R9: Will be set to 0
|
| | 868 | + @ R14: Return address
|
| | 869 | +
|
| | 870 | +sendlcdd:
|
| | 871 | + ldr r9, [r8,#0x1c]
|
| | 872 | + ands r9, r9, #0x10
|
| | 873 | + bne sendlcdd
|
| | 874 | + str r0, [r8,#0x40]
|
| | 875 | + mov pc, lr
|
| | 876 | +
|
| | 877 | + @ readlcd register map:
|
| | 878 | + @ R0: Result data
|
| | 879 | + @ R8: LCD base address
|
| | 880 | + @ R14: Return address
|
| | 881 | +
|
| | 882 | +readlcd:
|
| | 883 | + ldr r0, [r8,#0x1c]
|
| | 884 | + tst r0, #2
|
| | 885 | + beq readlcd
|
| | 886 | + str r0, [r8,#0x10]
|
| | 887 | +readlcd_wait:
|
| | 888 | + ldr r0, [r8,#0x1c]
|
| | 889 | + tst r0, #0x1
|
| | 890 | + beq readlcd_wait
|
| | 891 | + ldr r0, [r8,#0x14]
|
| | 892 | + mov r0, r0,lsr#1
|
| | 893 | + mov pc, lr
|
| | 894 | +
|
| | 895 | +lcddone:
|
| | 896 | + ldr r0, _stubend
|
| | 897 | + adr r1, _stubend + 4
|
| | 898 | + mov r2, #0x08000000
|
| | 899 | + add r0, r1, r0
|
| | 900 | +movepayloadloop:
|
| | 901 | + cmp r0, r1
|
| | 902 | + ldrhi r3, [r1], #4
|
| | 903 | + strhi r3, [r2], #4
|
| | 904 | + bhi movepayloadloop
|
| | 905 | + mcr p15, 0, r9,c7,c14,0 @ clean & invalidate data cache
|
| | 906 | + mcr p15, 0, r9,c7,c10,4 @ drain write buffer
|
| | 907 | + mcr p15, 0, r9,c7,c5 @ invalidate instruction cache
|
| | 908 | + mov pc, #0x08000000
|
| | 909 | +
|
| | 910 | +values1:
|
| | 911 | + block0_constpool
|
| | 912 | + block1_constpool
|
| | 913 | + gpio_initdata
|
| | 914 | + pmu_batch_1
|
| | 915 | + pmu_batch_2
|
| | 916 | + pmu_batch_3
|
| | 917 | + pmu_batch_4
|
| | 918 | + pmu_batch_5
|
| | 919 | + block6_constpool
|
| | 920 | + lcd_sequences
|
| | 921 | + .align 2
|
| | 922 | +
|
| | 923 | +_stubend:
|
| Index: apps/installer-ipodnano4g/bootstub/ls.x |
| — | — | @@ -0,0 +1,15 @@ |
| | 2 | +OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
|
| | 3 | + "elf32-littlearm")
|
| | 4 | +OUTPUT_ARCH(arm)
|
| | 5 | +ENTRY(_start)
|
| | 6 | +
|
| | 7 | +SECTIONS
|
| | 8 | +{
|
| | 9 | + . = 0x22000050;
|
| | 10 | +
|
| | 11 | + .text :
|
| | 12 | + {
|
| | 13 | + *(.text)
|
| | 14 | + }
|
| | 15 | +
|
| | 16 | +}
|
| Index: apps/installer-ipodnano4g/SOURCES |
| — | — | @@ -0,0 +1,2 @@ |
| | 2 | +main.c
|
| | 3 | +resources.S
|
| Index: apps/installer-ipodnano4g/version.h |
| — | — | @@ -0,0 +1,36 @@ |
| | 2 | +//
|
| | 3 | +//
|
| | 4 | +// Copyright 2010 TheSeven
|
| | 5 | +//
|
| | 6 | +//
|
| | 7 | +// This file is part of emCORE.
|
| | 8 | +//
|
| | 9 | +// emCORE is free software: you can redistribute it and/or
|
| | 10 | +// modify it under the terms of the GNU General Public License as
|
| | 11 | +// published by the Free Software Foundation, either version 2 of the
|
| | 12 | +// License, or (at your option) any later version.
|
| | 13 | +//
|
| | 14 | +// emCORE is distributed in the hope that it will be useful,
|
| | 15 | +// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| | 16 | +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
| | 17 | +// See the GNU General Public License for more details.
|
| | 18 | +//
|
| | 19 | +// You should have received a copy of the GNU General Public License along
|
| | 20 | +// with emCORE. If not, see <http://www.gnu.org/licenses/>.
|
| | 21 | +//
|
| | 22 | +//
|
| | 23 | +
|
| | 24 | +
|
| | 25 | +#ifndef __VERSION_H__
|
| | 26 | +#define __VERSION_H__
|
| | 27 | +
|
| | 28 | +
|
| | 29 | +#define VERSION "0.0.1"
|
| | 30 | +#define VERSION_MAJOR 0
|
| | 31 | +#define VERSION_MINOR 0
|
| | 32 | +#define VERSION_PATCH 1
|
| | 33 | +#define VERSION_SVN "$REVISION$"
|
| | 34 | +#define VERSION_SVN_INT $REVISIONINT$
|
| | 35 | +
|
| | 36 | +
|
| | 37 | +#endif |
| \ No newline at end of file |
| Index: apps/installer-ipodnano4g/Makefile |
| — | — | @@ -0,0 +1,238 @@ |
| | 2 | +NAME := installer-ipodnano4g
|
| | 3 | +STACKSIZE := 4096
|
| | 4 | +COMPRESS := false
|
| | 5 | +AUTOBUILD_FLASHFILES ?= true
|
| | 6 | +
|
| | 7 | +EMCOREDIR ?= ../../emcore/trunk/
|
| | 8 | +BOOTMENUDIR ?= ../bootmenu-ipodnano4g/
|
| | 9 | +LIBBOOTDIR ?= ../../libs/boot/
|
| | 10 | +LIBPNGDIR ?= ../../libs/png/
|
| | 11 | +LIBUIDIR ?= ../../libs/ui/
|
| | 12 | +LIBMKFAT32DIR ?= ../../libs/mkfat32/
|
| | 13 | +UMSBOOTDIR ?= ../../umsboot/
|
| | 14 | +TOOLSDIR ?= ../../tools/
|
| | 15 | +
|
| | 16 | +FLASHFILES = flashfiles/boot.emcorelib flashfiles/png.emcorelib flashfiles/ui.emcorelib flashfiles/mkfat32.emcorelib \
|
| | 17 | + flashfiles/bootmenu-ipodnano4g.emcoreapp flashfiles/background.png flashfiles/icons.png flashfiles/rockbox.png \
|
| | 18 | + flashfiles/emcoreldr-ipodnano4g.bin flashfiles/emcore-ipodnano4g.ucl flashfiles/umsboot-ipodnano4g.ucl
|
| | 19 | +
|
| | 20 | +ifeq ($(shell uname),WindowsNT)
|
| | 21 | +CCACHE :=
|
| | 22 | +else
|
| | 23 | +CCACHE := $(shell which ccache)
|
| | 24 | +endif
|
| | 25 | +
|
| | 26 | +CROSS ?= arm-elf-eabi-
|
| | 27 | +CC := $(CCACHE) $(CROSS)gcc
|
| | 28 | +AS := $(CROSS)as
|
| | 29 | +LD := $(CROSS)ld
|
| | 30 | +OBJCOPY := $(CROSS)objcopy
|
| | 31 | +ELF2ECA := $(CROSS)elf2emcoreapp
|
| | 32 | +UCLPACK := ucl2e10singleblk
|
| | 33 | +STUBEMBED := python tools/stubembed.py
|
| | 34 | +EMCOREBOOTCFG := python $(EMCOREDIR)/tools/emcorebootcfg.py
|
| | 35 | +EMCOREEMBEDAPP := python $(EMCOREDIR)/tools/emcoreembedapp.py
|
| | 36 | +GENPWN := python $(EMCOREDIR)/tools/ipodcrypt.py s5l8720-genpwnage
|
| | 37 | +
|
| | 38 | +LIBINCLUDES := -I$(LIBPNGDIR)/export -I$(LIBUIDIR)/export -I$(LIBMKFAT32DIR)/export
|
| | 39 | +
|
| | 40 | +CFLAGS += -Os -fno-pie -fno-stack-protector -fomit-frame-pointer -I. -I$(EMCOREDIR)/export $(LIBINCLUDES) -ffunction-sections -fdata-sections -mcpu=arm940t -DARM_ARCH=4
|
| | 41 | +LDFLAGS += "$(shell $(CC) -print-libgcc-file-name)" --emit-relocs --gc-sections
|
| | 42 | +
|
| | 43 | +preprocess = $(shell $(CC) $(PPCFLAGS) $(2) -E -P -x c $(1) | grep -v "^\#")
|
| | 44 | +preprocesspaths = $(shell $(CC) $(PPCFLAGS) $(2) -E -P -x c $(1) | grep -v "^\#" | sed -e "s:^..*:$(dir $(1))&:" | sed -e "s:^\\./::")
|
| | 45 | +
|
| | 46 | +REVISION := $(shell svnversion .)
|
| | 47 | +REVISIONINT := $(shell echo $(REVISION) | sed -e "s/[^0-9].*$$//")
|
| | 48 | +
|
| | 49 | +HELPERS := build/__emcore_armhelpers.o
|
| | 50 | +
|
| | 51 | +SRC := $(call preprocesspaths,SOURCES,-I. -I..)
|
| | 52 | +OBJ := $(SRC:%.c=build/%.o)
|
| | 53 | +OBJ := $(OBJ:%.S=build/%.o) $(HELPERS)
|
| | 54 | +
|
| | 55 | +all: $(NAME)
|
| | 56 | +
|
| | 57 | +-include $(OBJ:%=%.dep)
|
| | 58 | +
|
| | 59 | +$(NAME): build/bootstrap-ipodnano4g.dfu build/$(NAME).ubi
|
| | 60 | +
|
| | 61 | +build/bootstrap-ipodnano4g.dfu: build/bootstrap.bin
|
| | 62 | + @echo [GENPWN] $<
|
| | 63 | + @$(GENPWN) $< $@
|
| | 64 | +
|
| | 65 | +build/bootstrap.bin: build/bootstub.bin $(UMSBOOTDIR)/build/ipodnano4g/umsboot.bin
|
| | 66 | + @echo [STUBEM] $@
|
| | 67 | + @$(STUBEMBED) $^ $@
|
| | 68 | +
|
| | 69 | +build/$(NAME).ubi: $(EMCOREDIR)/build/ipodnano4g/emcore.bin build/$(NAME).emcoreapp
|
| | 70 | + @echo [EMBAPP] $@
|
| | 71 | + @$(EMCOREEMBEDAPP) $^ $@
|
| | 72 | +
|
| | 73 | +build/bootstub.bin: build/bootstub.elf
|
| | 74 | + @echo [OC] $<
|
| | 75 | + @$(OBJCOPY) -O binary $^ $@
|
| | 76 | +
|
| | 77 | +build/bootstub.elf: bootstub/ls.x build/bootstub/bootstub.o
|
| | 78 | + @echo [LD] $@
|
| | 79 | + @$(LD) $(LDFLAGS) -o $@ -T bootstub/ls.x build/bootstub/bootstub.o
|
| | 80 | +
|
| | 81 | +build/$(NAME).emcoreapp: build/$(NAME).elf
|
| | 82 | + @echo [EMCAPP] $<
|
| | 83 | +ifeq ($(COMPRESS),true)
|
| | 84 | + @$(ELF2ECA) -z -s $(STACKSIZE) -o $@ $^
|
| | 85 | +else
|
| | 86 | + @$(ELF2ECA) -s $(STACKSIZE) -o $@ $^
|
| | 87 | +endif
|
| | 88 | +
|
| | 89 | +ifeq ($(AUTOBUILD_FLASHFILES),true)
|
| | 90 | +build/resources.o: $(FLASHFILES)
|
| | 91 | +else
|
| | 92 | +build/resources.o: flashfiles.built
|
| | 93 | +endif
|
| | 94 | +
|
| | 95 | +build/$(NAME).elf: ls.x $(OBJ)
|
| | 96 | + @echo [LD] $@
|
| | 97 | + @$(LD) $(LDFLAGS) -o $@ -T ls.x $(OBJ)
|
| | 98 | +
|
| | 99 | +build/%.o: %.c build/version.h
|
| | 100 | + @echo [CC] $<
|
| | 101 | +ifeq ($(shell uname),WindowsNT)
|
| | 102 | + @-if not exist $(subst /,\,$(dir $@)) md $(subst /,\,$(dir $@))
|
| | 103 | +else
|
| | 104 | + @-mkdir -p $(dir $@)
|
| | 105 | +endif
|
| | 106 | + @$(CC) -c $(CFLAGS) -o $@ $<
|
| | 107 | + @$(CC) -MM $(CFLAGS) $< > $@.dep.tmp
|
| | 108 | + @sed -e "s|.*:|$@:|" < $@.dep.tmp > $@.dep
|
| | 109 | +ifeq ($(shell uname),WindowsNT)
|
| | 110 | + @sed -e "s/.*://" -e "s/\\$$//" < $@.dep.tmp | fmt -1 | sed -e "s/^ *//" -e "s/$$/:/" >> $@.dep
|
| | 111 | +else
|
| | 112 | + @sed -e 's/.*://' -e 's/\\$$//' < $@.dep.tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $@.dep
|
| | 113 | +endif
|
| | 114 | + @rm -f $@.dep.tmp
|
| | 115 | +
|
| | 116 | +build/%.o: %.S build/version.h
|
| | 117 | + @echo [CC] $<
|
| | 118 | +ifeq ($(shell uname),WindowsNT)
|
| | 119 | + @-if not exist $(subst /,\,$(dir $@)) md $(subst /,\,$(dir $@))
|
| | 120 | +else
|
| | 121 | + @-mkdir -p $(dir $@)
|
| | 122 | +endif
|
| | 123 | + @$(CC) -c $(CFLAGS) -o $@ $<
|
| | 124 | + @$(CC) -MM $(CFLAGS) $< > $@.dep.tmp
|
| | 125 | + @sed -e "s|.*:|$@:|" < $@.dep.tmp > $@.dep
|
| | 126 | +ifeq ($(shell uname),WindowsNT)
|
| | 127 | + @sed -e "s/.*://" -e "s/\\$$//" < $@.dep.tmp | fmt -1 | sed -e "s/^ *//" -e "s/$$/:/" >> $@.dep
|
| | 128 | +else
|
| | 129 | + @sed -e 's/.*://' -e 's/\\$$//' < $@.dep.tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $@.dep
|
| | 130 | +endif
|
| | 131 | + @rm -f $@.dep.tmp
|
| | 132 | +
|
| | 133 | +build/__emcore_%.o: $(EMCOREDIR)/export/%.c
|
| | 134 | + @echo [CC] $<
|
| | 135 | +ifeq ($(shell uname),WindowsNT)
|
| | 136 | + @-if not exist $(subst /,\,$(dir $@)) md $(subst /,\,$(dir $@))
|
| | 137 | +else
|
| | 138 | + @-mkdir -p $(dir $@)
|
| | 139 | +endif
|
| | 140 | + @$(CC) -c $(CFLAGS) -o $@ $<
|
| | 141 | +
|
| | 142 | +build/__emcore_%.o: $(EMCOREDIR)/export/%.S
|
| | 143 | + @echo [CC] $<
|
| | 144 | +ifeq ($(shell uname),WindowsNT)
|
| | 145 | + @-if not exist $(subst /,\,$(dir $@)) md $(subst /,\,$(dir $@))
|
| | 146 | +else
|
| | 147 | + @-mkdir -p $(dir $@)
|
| | 148 | +endif
|
| | 149 | + @$(CC) -c $(CFLAGS) -o $@ $<
|
| | 150 | +
|
| | 151 | +build/version.h: version.h .svn/entries
|
| | 152 | + @echo [PP] $<
|
| | 153 | +ifeq ($(shell uname),WindowsNT)
|
| | 154 | + @-if not exist build md build
|
| | 155 | + @sed -e "s/\$$REVISION\$$/$(REVISION)/" -e "s/\$$REVISIONINT\$$/$(REVISIONINT)/" < $< > $@
|
| | 156 | +else
|
| | 157 | + @-mkdir -p build
|
| | 158 | + @sed -e 's/\$$REVISION\$$/$(REVISION)/' -e 's/\$$REVISIONINT\$$/$(REVISIONINT)/' < $< > $@
|
| | 159 | +endif
|
| | 160 | +
|
| | 161 | +flashfiles: $(FLASHFILES)
|
| | 162 | + @touch flashfiles.built
|
| | 163 | +
|
| | 164 | +$(LIBBOOTDIR)/build/boot.emcorelib: libboot
|
| | 165 | + @$(MAKE) -C $(LIBBOOTDIR)
|
| | 166 | +
|
| | 167 | +flashfiles/boot.emcorelib: $(LIBBOOTDIR)/build/boot.emcorelib
|
| | 168 | + @echo [CP] $@
|
| | 169 | + @cp $< $@
|
| | 170 | +
|
| | 171 | +$(LIBPNGDIR)/build/png.emcorelib: libpng
|
| | 172 | + @$(MAKE) -C $(LIBPNGDIR)
|
| | 173 | +
|
| | 174 | +flashfiles/png.emcorelib: $(LIBPNGDIR)/build/png.emcorelib
|
| | 175 | + @echo [CP] $@
|
| | 176 | + @cp $< $@
|
| | 177 | +
|
| | 178 | +$(LIBUIDIR)/build/ui.emcorelib: libui
|
| | 179 | + @$(MAKE) -C $(LIBUIDIR)
|
| | 180 | +
|
| | 181 | +flashfiles/ui.emcorelib: $(LIBUIDIR)/build/ui.emcorelib
|
| | 182 | + @echo [CP] $@
|
| | 183 | + @cp $< $@
|
| | 184 | +
|
| | 185 | +$(LIBMKFAT32DIR)/build/mkfat32.emcorelib: libmkfat32
|
| | 186 | + @$(MAKE) -C $(LIBMKFAT32DIR)
|
| | 187 | +
|
| | 188 | +flashfiles/mkfat32.emcorelib: $(LIBMKFAT32DIR)/build/mkfat32.emcorelib
|
| | 189 | + @echo [CP] $@
|
| | 190 | + @cp $< $@
|
| | 191 | +
|
| | 192 | +$(UMSBOOTDIR)/build/ipodnano4g/umsboot-ipodnano4g.ucl $(UMSBOOTDIR)/build/ipodnano4g/umsboot.bin: umsboot
|
| | 193 | + @$(MAKE) -C $(UMSBOOTDIR) ipodnano4g
|
| | 194 | +
|
| | 195 | +flashfiles/umsboot-ipodnano4g.ucl: $(UMSBOOTDIR)/build/ipodnano4g/umsboot-ipodnano4g.ucl
|
| | 196 | + @echo [CP] $@
|
| | 197 | + @cp $< $@
|
| | 198 | +
|
| | 199 | +$(BOOTMENUDIR)/build/bootmenu-ipodnano4g.emcoreapp: bootmenu-ipodnano4g
|
| | 200 | + @$(MAKE) -C $(BOOTMENUDIR)
|
| | 201 | +
|
| | 202 | +flashfiles/bootmenu-ipodnano4g.emcoreapp: $(BOOTMENUDIR)/build/bootmenu-ipodnano4g.emcoreapp
|
| | 203 | + @echo [CP] $@
|
| | 204 | + @cp $< $@
|
| | 205 | +
|
| | 206 | +flashfiles/background.png: $(BOOTMENUDIR)/images/background.png
|
| | 207 | + @echo [CP] $@
|
| | 208 | + @cp $< $@
|
| | 209 | +
|
| | 210 | +flashfiles/icons.png: $(BOOTMENUDIR)/images/icons.png
|
| | 211 | + @echo [CP] $@
|
| | 212 | + @cp $< $@
|
| | 213 | +
|
| | 214 | +flashfiles/rockbox.png: $(BOOTMENUDIR)/images/rockbox.png
|
| | 215 | + @echo [CP] $@
|
| | 216 | + @cp $< $@
|
| | 217 | +
|
| | 218 | +$(EMCOREDIR)/loader/ipodnano4g/build/emcoreldr-ipodnano4g.bin: emcoreldr-ipodnano4g
|
| | 219 | + @$(MAKE) -C $(EMCOREDIR)/loader/ipodnano4g
|
| | 220 | +
|
| | 221 | +flashfiles/emcoreldr-ipodnano4g.bin: $(EMCOREDIR)/loader/ipodnano4g/build/emcoreldr-ipodnano4g.bin
|
| | 222 | + @echo [CP] $@
|
| | 223 | + @cp $< $@
|
| | 224 | +
|
| | 225 | +flashfiles/emcore-ipodnano4g.ucl: flashfiles/emcore-ipodnano4g.bin
|
| | 226 | + @echo [UCL] $<
|
| | 227 | + @$(UCLPACK) $< $@
|
| | 228 | +
|
| | 229 | +$(EMCOREDIR)/build/ipodnano4g/emcore.bin: emcore
|
| | 230 | + @$(MAKE) -C $(EMCOREDIR) ipodnano4g
|
| | 231 | +
|
| | 232 | +flashfiles/emcore-ipodnano4g.bin: $(EMCOREDIR)/build/ipodnano4g/emcore.bin
|
| | 233 | + @echo [EMBCFG] $@
|
| | 234 | + @$(EMCOREBOOTCFG) $< $@ "(3, '/.boot/init.emcoreapp', None, (2, 'bootmenu', None, None))"
|
| | 235 | +
|
| | 236 | +clean:
|
| | 237 | + @rm -rf build
|
| | 238 | +
|
| | 239 | +.PHONY: all clean emcore emcoreldr-ipodnano4g bootmenu-ipodnano4g libboot libpng libui libmkfat32 umsboot libucl flashfiles $(NAME)
|
| Index: apps/installer-ipodnano4g |
| Property changes on: apps/installer-ipodnano4g |
| ___________________________________________________________________ |
| Added: svn:ignore |
| ## -0,0 +1 ## |
| | 240 | +build |
