https://freemyipod.org/index.php?action=history&feed=atom&title=USB_OTG_features 2026-05-08T08:17:29Z Revision history for this page on the wiki MediaWiki 1.45.1 https://freemyipod.org/index.php?title=USB_OTG_features&diff=4147&oldid=prev 2011-12-31T22:41:23Z

<p>Created page with &quot;Nano2G: Connected to emCORE Debugger v0.2.2 r836 running on iPod nano 2g 38800040: 00000264 228DD9D0 050004E8 | d... ...&quot;....| 38800050: 01F08001 ...&quot;</p> <p><b>New page</b></p><div>Nano2G:<br /> Connected to emCORE Debugger v0.2.2 r836 running on iPod nano 2g<br /> 38800040: 00000264 228DD9D0 050004E8 | d... ...&quot;....|<br /> 38800050: 01F08001 |.... |<br /> <br /> Device Mode IN Token Sequence Learning Queue Depth: 16<br /> Host Mode Periodic Request Queue Depth: 8<br /> Non-Periodic Request Queue Depth: 8<br /> Dynamic FIFO Sizing Enabled: Yes<br /> Periodic OUT Channels Supported in Host Mode: Yes<br /> Number of Host Channels: 8 (Indicates the number of host channels supported by the core in Host mode)<br /> Number of Device Endpoints: 6(Indicates the number of device endpoints supported by the core in Device mode in addition to control endpoint 0)<br /> Full-Speed PHY Interface Type: Dedicated full-speed interface<br /> High-Speed PHY Interface Type: UTMI+ and ULPI<br /> Point-to-Point: Multi-point application<br /> Architecture: Internal DMA<br /> Mode of Operation: HNP- and SRP-Capable OTG (Host &amp; Device)<br /> Endpoints: 0 (BIDI), 1 (IN), 2 (OUT), 3 (IN), 4 (OUT), 5 (BIDI), 6 (BIDI)<br /> DFIFO Depth: 1280 (This value is in terms of 32-bit words =&gt; 5120 bytes)<br /> AHB and PHY Synchronous: No (Indicates whether AHB and PHY clocks are synchronous to each other)<br /> Reset Style for Clocked always Blocks in RTL: Asynchronous reset is used in the core<br /> Optional Features Removed: Yes (Indicates whether the User ID register, GPIO interface ports, and SOF toggle and counter ports were removed for gate count optimization)<br /> Vendor Control Interface Support: Vendor Control Interface is not available on the core<br /> I2C Selection: I2C Interface is not available on the core<br /> OTG Function Enabled: OTG Capable (The application uses this bit to indicate the O2P USB core&#039;s OTG capabilities)<br /> Width of Packet Size Counters: 10 bits<br /> Width of Transfer Size Counters: 19 bits<br /> Number of IN endpoints: 0 (?)<br /> Enable dedicated transmit FIFO for device IN endpoints: No<br /> session_end Filter Enabled: Yes<br /> b_valid Filter Enabled: Yes<br /> a_valid Filter Enabled: Yes<br /> vbus_valid Filter Enabled: Yes<br /> iddig Filter Enabled: Yes<br /> Number of Device Mode Control Endpoints in Addition to Endpoint 0: 0<br /> UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width: 8/16 bits, software selectable (When a ULPI PHY is used, an internal wrapper converts ULPI to UTMI+)<br /> Minimum AHB Frequency Less Than 60 MHz: No<br /> Enable Power Optimization: No<br /> Number of Device Mode Periodic IN Endpoints: 1<br /> <br /> Classic:<br /> Connected to emCORE Debugger v0.2.2 r836 running on iPod classic<br /> 38400040: 00000264 228F60D0 082000E8 | d... .`.&quot;.. .|<br /> 38400050: 1BF08030 |0... |<br /> <br /> Device Mode IN Token Sequence Learning Queue Depth: 16<br /> Host Mode Periodic Request Queue Depth: 8<br /> Non-Periodic Request Queue Depth: 8<br /> Dynamic FIFO Sizing Enabled: Yes<br /> Periodic OUT Channels Supported in Host Mode: Yes<br /> Number of Host Channels: 14 (Indicates the number of host channels supported by the core in Host mode)<br /> Number of Device Endpoints: 8 (Indicates the number of device endpoints supported by the core in Device mode in addition to control endpoint 0)<br /> Full-Speed PHY Interface Type: Full-speed interface not supported<br /> High-Speed PHY Interface Type: UTMI+ and ULPI<br /> Point-to-Point: Multi-point application<br /> Architecture: Internal DMA<br /> Mode of Operation: HNP- and SRP-Capable OTG (Host &amp; Device)<br /> Endpoints: 0 (BIDI), 1 (IN), 2 (OUT), 3 (IN), 4 (OUT), 5 (BIDI), 6 (BIDI), 7 (BIDI), 8 (BIDI)<br /> DFIFO Depth: 2080 (This value is in terms of 32-bit words =&gt; 8320 bytes)<br /> AHB and PHY Synchronous: No (Indicates whether AHB and PHY clocks are synchronous to each other)<br /> Reset Style for Clocked always Blocks in RTL: Asynchronous reset is used in the core<br /> Optional Features Removed: No (Indicates whether the User ID register, GPIO interface ports, and SOF toggle and counter ports were removed for gate count optimization)<br /> Vendor Control Interface Support: Vendor Control Interface is not available on the core<br /> I2C Selection: I2C Interface is not available on the core<br /> OTG Function Enabled: OTG Capable (The application uses this bit to indicate the O2P USB core&#039;s OTG capabilities)<br /> Width of Packet Size Counters: 10 bits<br /> Width of Transfer Size Counters: 19 bits<br /> Number of IN endpoints: 5 (?)<br /> Enable dedicated transmit FIFO for device IN endpoints: Yes<br /> session_end Filter Enabled: Yes<br /> b_valid Filter Enabled: Yes<br /> a_valid Filter Enabled: Yes<br /> vbus_valid Filter Enabled: Yes<br /> iddig Filter Enabled: Yes<br /> Number of Device Mode Control Endpoints in Addition to Endpoint 0: 0<br /> UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width: 8/16 bits, software selectable (When a ULPI PHY is used, an internal wrapper converts ULPI to UTMI+)<br /> Minimum AHB Frequency Less Than 60 MHz: Yes<br /> Enable Power Optimization: Yes<br /> Number of Device Mode Periodic IN Endpoints: 0</div>

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