Nano 3G/Memory Map - Revision history

Yuriks at 01:10, 22 May 2011

2011-05-22T01:10:37Z

← Older revision		Revision as of 01:10, 22 May 2011
Line 33:		Line 33:
	\| <tt>0x3C80_0000<br />0x3C80_0004</tt> \|\| WDTCON<br />WDTCNT \|\| Watchdog timer<ref name="datasheet" />		\| <tt>0x3C80_0000<br />0x3C80_0004</tt> \|\| WDTCON<br />WDTCNT \|\| Watchdog timer<ref name="datasheet" />
	\|-		\|-
	\| <tt>0x38E0_0000 ~~- 0x38E0_1000~~<br />0x38E0_1000 ~~- 0x38E0_2000~~</tt> \|\| VIC0 Base<br />VIC1 Base \|\| Vectored Interrupt Controller<ref name="vic_ds" />		\| <tt>0x38E0_1000 - 0x38E0_0000<br />0x38E0_2000 - 0x38E0_1000</tt> \|\| VIC0 Base<br />VIC1 Base \|\| Vectored Interrupt Controller<ref name="vic_ds" />
	\|-		\|-
	\|}		\|}

Yuriks: Switched to open interval end addresses

2011-05-22T01:09:58Z

Switched to open interval end addresses

← Older revision		Revision as of 01:09, 22 May 2011
Line 3:		Line 3:
	! Address !! Description !! Notes		! Address !! Description !! Notes
	\|-		\|-
	\| <tt>~~0xFFFF_FFFF~~ - 0x4000_0000</tt> \|\| \|\|		\| <tt>0x100000000 - 0x4000_0000</tt> \|\| \|\|
	\|-		\|-
	\| <tt>~~0x3FFF_FFFF~~ - 0x3800_0000</tt> \|\| I/O Area \|\| See table below		\| <tt>0x4000_0000 - 0x3800_0000</tt> \|\| I/O Area \|\| See table below
	\|-		\|-
	\| <tt>~~0x37FF_FFFF~~ - 0x2204_0000</tt> \|\| \|\|		\| <tt>0x3800_0000 - 0x2204_0000</tt> \|\| \|\|
	\|-		\|-
	\| <tt>~~0x2203_FFFF~~ - 0x2200_0000</tt> \|\| On-chip SRAM \|\| Always accessible		\| <tt>0x2204_0000 - 0x2200_0000</tt> \|\| On-chip SRAM \|\| Always accessible
	\|-		\|-
	\| <tt>~~0x21FF_FFFF~~ - 0x2000_C800</tt> \|\| \|\|		\| <tt>0x2200_0000 - 0x2000_C800</tt> \|\| \|\|
	\|-		\|-
	\| <tt>~~0x2000_C7FF~~ - 0x2000_0000</tt> \|\| Boot ROM \|\| Executed by processor at start up		\| <tt>0x2000_C800 - 0x2000_0000</tt> \|\| Boot ROM \|\| Executed by processor at start up
	\|-		\|-
	\| <tt>~~0x1FFF_FFFF~~ - 0x0C00_0000</tt> \|\| \|\|		\| <tt>0x2000_0000 - 0x0C00_0000</tt> \|\| \|\|
	\|-		\|-
	\| <tt>~~0x0BFF_FFFF~~ - 0x0A00_0000</tt> \|\| SDRAM Mirror 2 \|\| Same contents as mirror 1		\| <tt>0x0C00_0000 - 0x0A00_0000</tt> \|\| SDRAM Mirror 2 \|\| Same contents as mirror 1
	\|-		\|-
	\| <tt>~~0x09FF_FFFF~~ - 0x0800_0000</tt> \|\| SDRAM Mirror 1 \|\| Needs initialization		\| <tt>0x0A00_0000 - 0x0800_0000</tt> \|\| SDRAM Mirror 1 \|\| Needs initialization
	\|-		\|-
	\| <tt>~~0x07FF_FFFF~~ - 0x0000_0000</tt> \|\| \|\|		\| <tt>0x0800_0000 - 0x0000_0000</tt> \|\| \|\|
	\|-		\|-
	\|}		\|}

Yuriks: Added _ spacers

2011-05-22T01:05:25Z

Added _ spacers

← Older revision		Revision as of 01:05, 22 May 2011
Line 3:		Line 3:
	! Address !! Description !! Notes		! Address !! Description !! Notes
	\|-		\|-
	\| <tt>~~0xFFFF FFFF~~ - ~~0x4000 0000~~</tt> \|\| \|\|		\| <tt>0xFFFF_FFFF - 0x4000_0000</tt> \|\| \|\|
	\|-		\|-
	\| <tt>~~0x3FFF FFFF~~ - ~~0x3800 0000~~</tt> \|\| I/O Area \|\| See table below		\| <tt>0x3FFF_FFFF - 0x3800_0000</tt> \|\| I/O Area \|\| See table below
	\|-		\|-
	\| <tt>~~0x37FF FFFF~~ - ~~0x2204 0000~~</tt> \|\| \|\|		\| <tt>0x37FF_FFFF - 0x2204_0000</tt> \|\| \|\|
	\|-		\|-
	\| <tt>~~0x2203 FFFF~~ - ~~0x2200 0000~~</tt> \|\| On-chip SRAM \|\| Always accessible		\| <tt>0x2203_FFFF - 0x2200_0000</tt> \|\| On-chip SRAM \|\| Always accessible
	\|-		\|-
	\| <tt>~~0x21FF FFFF~~ - ~~0x2000 C800~~</tt> \|\| \|\|		\| <tt>0x21FF_FFFF - 0x2000_C800</tt> \|\| \|\|
	\|-		\|-
	\| <tt>~~0x2000 C7FF~~ - ~~0x2000 0000~~</tt> \|\| Boot ROM \|\| Executed by processor at start up		\| <tt>0x2000_C7FF - 0x2000_0000</tt> \|\| Boot ROM \|\| Executed by processor at start up
	\|-		\|-
	\| <tt>~~0x1FFF FFFF~~ - ~~0x0C00 0000~~</tt> \|\| \|\|		\| <tt>0x1FFF_FFFF - 0x0C00_0000</tt> \|\| \|\|
	\|-		\|-
	\| <tt>~~0x0BFF FFFF~~ - ~~0x0A00 0000~~</tt> \|\| SDRAM Mirror 2 \|\| Same contents as mirror 1		\| <tt>0x0BFF_FFFF - 0x0A00_0000</tt> \|\| SDRAM Mirror 2 \|\| Same contents as mirror 1
	\|-		\|-
	\| <tt>~~0x09FF FFFF~~ - ~~0x0800 0000~~</tt> \|\| SDRAM Mirror 1 \|\| Needs initialization		\| <tt>0x09FF_FFFF - 0x0800_0000</tt> \|\| SDRAM Mirror 1 \|\| Needs initialization
	\|-		\|-
	\| <tt>~~0x07FF FFFF~~ - ~~0x0000 0000~~</tt> \|\| \|\|		\| <tt>0x07FF_FFFF - 0x0000_0000</tt> \|\| \|\|
	\|-		\|-
	\|}		\|}
Line 31:		Line 31:
	! Address !! Description !! Notes		! Address !! Description !! Notes
	\|-		\|-
	\| <tt>~~0x3C800000~~<br />~~0x3C800004~~</tt> \|\| WDTCON<br />WDTCNT \|\| Watchdog timer<ref name="datasheet" />		\| <tt>0x3C80_0000<br />0x3C80_0004</tt> \|\| WDTCON<br />WDTCNT \|\| Watchdog timer<ref name="datasheet" />
	\|-		\|-
	\| <tt>0x38E0_0000 - 0x38E0_1000<br />0x38E0_1000 - 0x38E0_2000</tt> \|\| VIC0 Base<br />VIC1 Base \|\| Vectored Interrupt Controller<ref name="vic_ds" />		\| <tt>0x38E0_0000 - 0x38E0_1000<br />0x38E0_1000 - 0x38E0_2000</tt> \|\| VIC0 Base<br />VIC1 Base \|\| Vectored Interrupt Controller<ref name="vic_ds" />

Yuriks: Added VIC

2011-05-22T01:03:59Z

Added VIC

← Older revision		Revision as of 01:03, 22 May 2011
Line 32:		Line 32:
	\|-		\|-
	\| <tt>0x3C800000<br />0x3C800004</tt> \|\| WDTCON<br />WDTCNT \|\| Watchdog timer<ref name="datasheet" />		\| <tt>0x3C800000<br />0x3C800004</tt> \|\| WDTCON<br />WDTCNT \|\| Watchdog timer<ref name="datasheet" />
			\|-
			\| <tt>0x38E0_0000 - 0x38E0_1000<br />0x38E0_1000 - 0x38E0_2000</tt> \|\| VIC0 Base<br />VIC1 Base \|\| Vectored Interrupt Controller<ref name="vic_ds" />
	\|-		\|-
	\|}		\|}
Line 37:		Line 39:
	<references>		<references>
	<ref name="datasheet">See [[S5L8700 datasheet]]</ref>		<ref name="datasheet">See [[S5L8700 datasheet]]</ref>
			<ref name="vic_ds">ARM PrimeCell Vectored Interrupt Controller (PL192) - [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0273a/DDI0273.pdf Datasheet]
	</references>		</references>

Yuriks at 11:18, 30 November 2010

2010-11-30T11:18:37Z

← Older revision		Revision as of 11:18, 30 November 2010
Line 30:		Line 30:
	\|-		\|-
	! Address !! Description !! Notes		! Address !! Description !! Notes
			\|-
			\| <tt>0x3C800000<br />0x3C800004</tt> \|\| WDTCON<br />WDTCNT \|\| Watchdog timer<ref name="datasheet" />
	\|-		\|-
	\|}		\|}

			<references>
			<ref name="datasheet">See [[S5L8700 datasheet]]</ref>
			</references>

Yuriks at 11:11, 30 November 2010

2010-11-30T11:11:59Z

← Older revision		Revision as of 11:11, 30 November 2010
Line 3:		Line 3:
	! Address !! Description !! Notes		! Address !! Description !! Notes
	\|-		\|-
	\| <tt>0xFFFF FFFF - 0x2204 0000</tt> \|\| \|\|		\| <tt>0xFFFF FFFF - 0x4000 0000</tt> \|\| \|\|
			\|-
			\| <tt>0x3FFF FFFF - 0x3800 0000</tt> \|\| I/O Area \|\| See table below
			\|-
			\| <tt>0x37FF FFFF - 0x2204 0000</tt> \|\| \|\|
	\|-		\|-
	\| <tt>0x2203 FFFF - 0x2200 0000</tt> \|\| On-chip SRAM \|\| Always accessible		\| <tt>0x2203 FFFF - 0x2200 0000</tt> \|\| On-chip SRAM \|\| Always accessible
Line 18:		Line 22:
	\|-		\|-
	\| <tt>0x07FF FFFF - 0x0000 0000</tt> \|\| \|\|		\| <tt>0x07FF FFFF - 0x0000 0000</tt> \|\| \|\|
			\|-
			\|}

			= IO Map =

			{\| class="wikitable"
			\|-
			! Address !! Description !! Notes
	\|-		\|-
	\|}		\|}

Yuriks: Some other stuff

2010-11-29T12:22:38Z

Some other stuff

← Older revision		Revision as of 12:22, 29 November 2010
Line 6:		Line 6:
	\|-		\|-
	\| <tt>0x2203 FFFF - 0x2200 0000</tt> \|\| On-chip SRAM \|\| Always accessible		\| <tt>0x2203 FFFF - 0x2200 0000</tt> \|\| On-chip SRAM \|\| Always accessible
			\|-
			\| <tt>0x21FF FFFF - 0x2000 C800</tt> \|\| \|\|
			\|-
			\| <tt>0x2000 C7FF - 0x2000 0000</tt> \|\| Boot ROM \|\| Executed by processor at start up
			\|-
			\| <tt>0x1FFF FFFF - 0x0C00 0000</tt> \|\| \|\|
	\|-		\|-
	\| <tt>0x0BFF FFFF - 0x0A00 0000</tt> \|\| SDRAM Mirror 2 \|\| Same contents as mirror 1		\| <tt>0x0BFF FFFF - 0x0A00 0000</tt> \|\| SDRAM Mirror 2 \|\| Same contents as mirror 1

Yuriks: Added blank sections and reversed address ranges

2010-11-29T12:06:25Z

Added blank sections and reversed address ranges

← Older revision		Revision as of 12:06, 29 November 2010
Line 3:		Line 3:
	! Address !! Description !! Notes		! Address !! Description !! Notes
	\|-		\|-
	\| <tt>~~0x2200~~ 0000 ~~- 0x2203 FFFF~~</tt> \|\| ~~On-chip SRAM~~ \|\| ~~Always accessible~~		\| <tt>0xFFFF FFFF - 0x2204 0000</tt> \|\| \|\|
	\|-		\|-
	\| <tt>~~0x0A00~~ 0000 ~~- 0x0BFF FFFF~~</tt> \|\| ~~SDRAM Mirror 2~~ \|\| ~~Same contents as mirror 1~~		\| <tt>0x2203 FFFF - 0x2200 0000</tt> \|\| On-chip SRAM \|\| Always accessible
	\|-		\|-
	\| <tt>~~0x0800~~ 0000 - 0x09FF FFFF</tt> \|\| SDRAM Mirror 1 \|\| Needs initialization		\| <tt>0x0BFF FFFF - 0x0A00 0000</tt> \|\| SDRAM Mirror 2 \|\| Same contents as mirror 1
			\|-
			\| <tt>0x09FF FFFF - 0x0800 0000</tt> \|\| SDRAM Mirror 1 \|\| Needs initialization
			\|-
			\| <tt>0x07FF FFFF - 0x0000 0000</tt> \|\| \|\|
	\|-		\|-
	\|}		\|}

Yuriks: crappy memory map

2010-11-29T12:03:06Z

crappy memory map

New page

{| class="wikitable"
|-
! Address !! Description !! Notes
|-
| <tt>0x2200 0000 - 0x2203 FFFF</tt> || On-chip SRAM || Always accessible
|-
| <tt>0x0A00 0000 - 0x0BFF FFFF</tt> || SDRAM Mirror 2 || Same contents as mirror 1
|-
| <tt>0x0800 0000 - 0x09FF FFFF</tt> || SDRAM Mirror 1 || Needs initialization
|-
|}