FMSS - Revision history

Q3k: /* CS (Code Sequencer) */

2023-10-11T00:57:44Z

CS (Code Sequencer)

← Older revision		Revision as of 00:57, 11 October 2023
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	! Offset !! Register Name !! Description		! Offset !! Register Name !! Description
	\|-		\|-
			\| 0xC04 \|\| CS_IP \|\| Sequencer's instruction pointer.
	\|-		\|-
	~~\| 0xC04 \|\| CS_IP \|\| Sequencer's instruction pointer.~~
	\| 0xC08 \|\| CS_STATUS \|\|		\| 0xC08 \|\| CS_STATUS \|\|
	\|-		\|-

2023-10-11T00:57:36Z

CS (Code Sequencer)

← Older revision		Revision as of 00:57, 11 October 2023
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	! Offset !! Register Name !! Description		! Offset !! Register Name !! Description
	\|-		\|-
			\|-
			\| 0xC04 \|\| CS_IP \|\| Sequencer's instruction pointer.
	\| 0xC08 \|\| CS_STATUS \|\|		\| 0xC08 \|\| CS_STATUS \|\|
	\|-		\|-

2023-10-11T00:54:16Z

CS (Code Sequencer)

2023-10-11T00:53:19Z

← Older revision		Revision as of 00:53, 11 October 2023
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	The bytecode is documented at [https://github.com/lemonjesus/S5L8702-FMISS-Tools lemonjesus/S5L8702-FMISS-Tools].		The bytecode is documented at [https://github.com/lemonjesus/S5L8702-FMISS-Tools lemonjesus/S5L8702-FMISS-Tools].

			{\| class="wikitable"
			\|-
			! Offset !! Register Name !! Description
			\|-
			\| 0xC08 \|\| CS_STATUS \|\|
			\|-
			\| 0xC60 \|\| CS_BUF_RST \|\|
			\|-
			\| 0xC64 \|\| CS_BUF_RST_OK \|\|
			\|-
			\| 0xC6C \|\| CS_BUF_START \|\|
			\|}

	== Other devices / SoCs ==		== Other devices / SoCs ==

2023-03-17T18:15:18Z

Other devices / SoCs

← Older revision		Revision as of 18:15, 17 March 2023
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	On the S5L8900 the built-in CalmRISC16e core that's part of the ADM (Audio DSP Module) is used as a code sequencer in iOS.		On the S5L8900 the built-in CalmRISC16e core that's part of the ADM (Audio DSP Module) is used as a code sequencer in iOS.

	~~=== S5L8950 / A6 ===~~

	~~The controller is called 'PPNFMSS' and seems to use the same CS bytecode, and a generally similar register layout.~~

2023-03-17T18:06:20Z

FMC (Flash Memory Controller)

← Older revision		Revision as of 18:06, 17 March 2023
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	\|-		\|-
	\| 0x048 \|\| FMSTAT \|\| Controller status.		\| 0x048 \|\| FMSTAT \|\| Controller status.
			* Bit 0: flash busy?
	* Bit 1: command done. Write to clear.		* Bit 1: command done. Write to clear.
	* Bit 2: address done. Write to clear.		* Bit 2: address done. Write to clear.
	* Bit 3: transfer done. Write to clear.		* Bit 3: transfer done. Write to clear.
			* Bit 23: flash has become busy? Write to clear.
	\|}		\|}

2023-03-17T17:59:09Z

FMC (Flash Memory Controller)

← Older revision		Revision as of 17:59, 17 March 2023
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	\|-		\|-
	\| 0x030 \|\| FMDNUM \|\| Number of bytes to transfer during data transfer minus one (ie. countdown counter).		\| 0x030 \|\| FMDNUM \|\| Number of bytes to transfer during data transfer minus one (ie. countdown counter).
			\|-
			\| 0x048 \|\| FMSTAT \|\| Controller status.
			* Bit 1: command done. Write to clear.
			* Bit 2: address done. Write to clear.
			* Bit 3: transfer done. Write to clear.
	\|}		\|}

2023-03-17T17:54:34Z

FMC (Flash Memory Controller)

← Older revision		Revision as of 17:54, 17 March 2023
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	* Bits [28..30]: EDO clocks		* Bits [28..30]: EDO clocks
	\|-		\|-
	\| 0x004 \|\| FMCTRL1 \|\| ~~Control~~ register ~~used to start transfers~~. Bit 0: ~~DOADDR,~~ Bit 1: ~~DORXDAT, Bit2~~: ~~DOTXDAT~~.		\| 0x004 \|\| FMCTRL1 \|\| Transfer control register.
			* Bit 0: Start address transfer.
			* Bit 1: Start read transfer.
			* Bit 2: Start write transfer.
			* Bit 4: ???
			* Bit 5: Clear ???
			* Bit 6: Clear write FIFO
			* Bit 7: Clear read FIFO
	\|-		\|-
	\| 0x008 \|\| FMCMD \|\| NAND command number. Eg. 0x90: read NAND ID. Documented in JEDEC docs and NAND chip datasheets.		\| 0x008 \|\| FMCMD \|\| NAND command number. Eg. 0x90: read NAND ID. Documented in JEDEC docs and NAND chip datasheets.

2023-03-17T17:51:09Z

FMC (Flash Memory Controller)

← Older revision		Revision as of 17:51, 17 March 2023
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	! Offset !! Register Name !! Description		! Offset !! Register Name !! Description
	\|-		\|-
	\| 0x000 \|\| FMCTRL0 \|\| General control register. Bit 10: ~~MASTER_EN, bit 24~~: ~~DMA_EN~~.		\| 0x000 \|\| FMCTRL0 \|\| General control register.
			* Bit 0: Enable
			* Bits [1..8]: CE/Bank number
			* Bit 10: DMA enable?
			* Bits [12..14]: Hold clocks
			* Bits [16..18]: Setup clocks
			* Bits [28..30]: EDO clocks
	\|-		\|-
	\| 0x004 \|\| FMCTRL1 \|\| Control register used to start transfers. Bit 0: DOADDR, Bit 1: DORXDAT, Bit2: DOTXDAT.		\| 0x004 \|\| FMCTRL1 \|\| Control register used to start transfers. Bit 0: DOADDR, Bit 1: DORXDAT, Bit2: DOTXDAT.

2023-03-17T17:41:28Z

CS (Code Sequencer)

← Older revision		Revision as of 17:41, 17 March 2023
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	=== CS (Code Sequencer) ===		=== CS (Code Sequencer) ===

	A little custom core that executes a custom bytecode. 9 32-bit general purpose registers. Controlled by the host CPU.		A little custom core that executes a custom bytecode. 9 32-bit general purpose registers. Controlled by the host CPU. It has access to the host memory and the rest of the FMSS peripherals, and operates by performing accesses to the FMC and ECC subsystems.

	The bytecode is documented at [https://github.com/lemonjesus/S5L8702-FMISS-Tools lemonjesus/S5L8702-FMISS-Tools].		The bytecode is documented at [https://github.com/lemonjesus/S5L8702-FMISS-Tools lemonjesus/S5L8702-FMISS-Tools].