920-0614-03 - Revision history

Q3k: /* CHIPID */

2025-05-05T01:20:48Z

CHIPID

← Older revision		Revision as of 01:20, 5 May 2025
Line 50:		Line 50:
	Effects:		Effects:

	# <code>CHIPIDL & 0x10 == 0</code>: The BootROM accepts an additional ~~top-level~~ serial: 0x01 0xFB '''0x00''' 0xFB in addition to the standard 0x01 0xFB '''0x01''' 0xFB		# <code>CHIPIDL & 0x10 == 0</code>: The BootROM accepts an additional leaf certificate serial: 0x01 0xFB '''0x00''' 0xFB in addition to the standard 0x01 0xFB '''0x01''' 0xFB
	# <code>CHIPIDL & (1 << 27) == 0</code>: The WTF's ChipID[2] function returns 2 instead of 3 in second argument.		# <code>CHIPIDL & (1 << 27) == 0</code>: The WTF's ChipID[2] function returns 2 instead of 3 in second argument.

Q3k at 01:10, 23 December 2024

2024-12-23T01:10:32Z

← Older revision		Revision as of 01:10, 23 December 2024
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	== Specs ==		== Specs ==

	'''SoC''': ~~S5L8729~~		'''SoC''': S5L8720

	'''Flash''': Usually desoldered		'''Flash''': Usually desoldered
Line 51:		Line 51:

	# <code>CHIPIDL & 0x10 == 0</code>: The BootROM accepts an additional top-level serial: 0x01 0xFB '''0x00''' 0xFB in addition to the standard 0x01 0xFB '''0x01''' 0xFB		# <code>CHIPIDL & 0x10 == 0</code>: The BootROM accepts an additional top-level serial: 0x01 0xFB '''0x00''' 0xFB in addition to the standard 0x01 0xFB '''0x01''' 0xFB
	# <code>CHIPIDL & (1 << 27) == 0</code>: The WTF's ChipID[2] function returns 2 instead of 3 in *second argument.		# <code>CHIPIDL & (1 << 27) == 0</code>: The WTF's ChipID[2] function returns 2 instead of 3 in second argument.

	== Pins ==		== Pins ==

Q3k: /* Pins */

2024-05-05T10:21:26Z

Pins

← Older revision		Revision as of 10:21, 5 May 2024
Line 63:		Line 63:
	\| 91 \|\| 'DFU' button		\| 91 \|\| 'DFU' button
	\|-		\|-
	\| 2 \|\| DB9 UART TX (~~J9205~~)		\| 5 \|\| DB9 UART TX (J9204)
	\|}		\|}

Q3k: /* Pins */

2024-05-04T14:42:08Z

Pins

← Older revision		Revision as of 14:42, 4 May 2024
Line 62:		Line 62:
	\|-		\|-
	\| 91 \|\| 'DFU' button		\| 91 \|\| 'DFU' button
			\|-
			\| 2 \|\| DB9 UART TX (J9205)
	\|}		\|}

Q3k at 16:56, 27 October 2023

2023-10-27T16:56:48Z

← Older revision		Revision as of 16:56, 27 October 2023
Line 63:		Line 63:
	\| 91 \|\| 'DFU' button		\| 91 \|\| 'DFU' button
	\|}		\|}

			== Case ==

			Protective case design: https://www.printables.com/model/628404-920-0614-03-ipod-nano-4g-prototype-case

Q3k: /* Differences from production device */

2023-10-27T15:49:41Z

Differences from production device

← Older revision		Revision as of 15:49, 27 October 2023
Line 51:		Line 51:

	# <code>CHIPIDL & 0x10 == 0</code>: The BootROM accepts an additional top-level serial: 0x01 0xFB '''0x00''' 0xFB in addition to the standard 0x01 0xFB '''0x01''' 0xFB		# <code>CHIPIDL & 0x10 == 0</code>: The BootROM accepts an additional top-level serial: 0x01 0xFB '''0x00''' 0xFB in addition to the standard 0x01 0xFB '''0x01''' 0xFB
	# <code>CHIPIDL & (1 << 27) == 1</code>: The WTF's ChipID[2] function returns 3 instead of 2 in *second argument.		# <code>CHIPIDL & (1 << 27) == 0</code>: The WTF's ChipID[2] function returns 2 instead of 3 in *second argument.

	== Pins ==		== Pins ==

Q3k: /* Differences from production device */

2023-10-27T15:47:16Z

Differences from production device

← Older revision		Revision as of 15:47, 27 October 2023
Line 50:		Line 50:
	Effects:		Effects:

	# <code>CHIPIDL & 10 == 0</code>: The BootROM accepts an additional top-level serial: 0x01 0xFB '''0x00''' 0xFB in addition to the standard 0x01 0xFB '''0x01''' 0xFB		# <code>CHIPIDL & 0x10 == 0</code>: The BootROM accepts an additional top-level serial: 0x01 0xFB '''0x00''' 0xFB in addition to the standard 0x01 0xFB '''0x01''' 0xFB
			# <code>CHIPIDL & (1 << 27) == 1</code>: The WTF's ChipID[2] function returns 3 instead of 2 in *second argument.

	== Pins ==		== Pins ==

Q3k at 15:26, 27 October 2023

2023-10-27T15:26:03Z

← Older revision		Revision as of 15:26, 27 October 2023
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	== Differences from production device ==		== Differences from production device ==

	~~So far, it seems like the SoC present on the board is no different from production SoCs.~~		=== CHIPID ===

	~~===~~ CHIPID ===		Different CHIPIDL/H values are present in the CHIPID peripheral:

			{\| class="wikitable"
			\|-
			! SoC !! CHIPIDL (<code>0x3d100_0004</code>) !! CHIPIDH (<code>0x3d100_0008</code>)
			\|-
			\| Nano 4G \|\| <code>19000011</code> \|\| <code>8720000f</code>
			\|-
			\| 920-0614-03 \|\| <code>11000001</code> \|\| <code>8720180f</code>
			\|}

	~~Seems like a perfectly standard S5L8720~~:		Effects:

	<~~pre~~>		# <code>CHIPIDL & 10 == 0</code>: The BootROM accepts an additional top-level serial: 0x01 0xFB '''0x00''' 0xFB in addition to the standard 0x01 0xFB '''0x01''' 0xFB
	~~3d100000: 0100 0000 0100 0011 0f18 2087 104f 6d76 .......... ..Omv~~
	~~3d100010: d700 0000 0300 0000 0000 0000 0000 0000 ................~~
	</~~pre~~>

	== Pins ==		== Pins ==

Q3k at 22:25, 18 October 2023

2023-10-18T22:25:35Z

← Older revision		Revision as of 22:25, 18 October 2023
Line 36:		Line 36:

	So far, it seems like the SoC present on the board is no different from production SoCs.		So far, it seems like the SoC present on the board is no different from production SoCs.

			=== CHIPID ===

			Seems like a perfectly standard S5L8720:

			<pre>
			3d100000: 0100 0000 0100 0011 0f18 2087 104f 6d76 .......... ..Omv
			3d100010: d700 0000 0300 0000 0000 0000 0000 0000 ................
			</pre>

	== Pins ==		== Pins ==

Q3k: Created page with "The 920-0614-03 is seemingly a development/prototype iPod Nano 4G (or possibly iPod Touch 2G board?). It appeared on a bunch of eBay auctions around September 2023. == Specs..."

2023-10-18T22:23:27Z

Created page with "The 920-0614-03 is seemingly a development/prototype iPod Nano 4G (or possibly iPod Touch 2G board?). It appeared on a bunch of eBay auctions around September 2023. == Specs..."

New page

The 920-0614-03 is seemingly a development/prototype iPod Nano 4G (or possibly iPod Touch 2G board?). It appeared on a bunch of eBay auctions around September 2023.

== Specs ==

'''SoC''': S5L8729

'''Flash''': Usually desoldered

'''DRAM''': To be checked

== UART ==

The boards has at least two ways to access UART:

# Over DE9 connector.

# Over USB/Serial bridge.

# Over 30-pin connector.

'''TODO''': Figure out which serial is which, and document reanimating DE9/USB.

== Power ==

The board runs from either the 30-pin connector by itself (although it can sometimes be unstable) or from 5V over a DC power jack (which provides a 4v-ish supply which simulates the devices' battery).

== JTAG ==

[[JTAG]] is available over the 30 pin connector, but is also seemingly locked out as on production devices.

== Getting code to run ==

[[wInd3x]] works on the device. On devices without Flash attempting to run the standard WTF causes a reset.

== Differences from production device ==

So far, it seems like the SoC present on the board is no different from production SoCs.

== Pins ==

As the board has clearly labeled and accessible GPIO pins / configuration straps, it's a good candidate to reverse engineer pin functionality as used in the production device.

{| class="wikitable"
|-
! S5L8720 GPIO !! Function on board
|-
| 91 || 'DFU' button
|}