freemyipod - User contributions [en]

Nano 3G/Memory Map

2011-05-22T01:10:37Z

Yuriks:

{| class="wikitable"
|-
! Address !! Description !! Notes
|-
| <tt>0x100000000 - 0x4000_0000</tt> || ||
|-
| <tt>0x4000_0000 - 0x3800_0000</tt> || I/O Area || See table below
|-
| <tt>0x3800_0000 - 0x2204_0000</tt> || ||
|-
| <tt>0x2204_0000 - 0x2200_0000</tt> || On-chip SRAM || Always accessible
|-
| <tt>0x2200_0000 - 0x2000_C800</tt> || ||
|-
| <tt>0x2000_C800 - 0x2000_0000</tt> || Boot ROM || Executed by processor at start up
|-
| <tt>0x2000_0000 - 0x0C00_0000</tt> || ||
|-
| <tt>0x0C00_0000 - 0x0A00_0000</tt> || SDRAM Mirror 2 || Same contents as mirror 1
|-
| <tt>0x0A00_0000 - 0x0800_0000</tt> || SDRAM Mirror 1 || Needs initialization
|-
| <tt>0x0800_0000 - 0x0000_0000</tt> || ||
|-
|}

= IO Map =

{| class="wikitable"
|-
! Address !! Description !! Notes
|-
| <tt>0x3C80_0000 0x3C80_0004</tt> || WDTCON WDTCNT || Watchdog timer<ref name="datasheet" />
|-
| <tt>0x38E0_1000 - 0x38E0_0000 0x38E0_2000 - 0x38E0_1000</tt> || VIC0 Base VIC1 Base || Vectored Interrupt Controller<ref name="vic_ds" />
|-
|}

<references>
<ref name="datasheet">See [[S5L8700 datasheet]]</ref>
<ref name="vic_ds">ARM PrimeCell Vectored Interrupt Controller (PL192) - [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0273a/DDI0273.pdf Datasheet]
</references>

Nano 3G/Memory Map

2011-05-22T01:09:58Z

Yuriks: Switched to open interval end addresses

{| class="wikitable"
|-
! Address !! Description !! Notes
|-
| <tt>0x100000000 - 0x4000_0000</tt> || ||
|-
| <tt>0x4000_0000 - 0x3800_0000</tt> || I/O Area || See table below
|-
| <tt>0x3800_0000 - 0x2204_0000</tt> || ||
|-
| <tt>0x2204_0000 - 0x2200_0000</tt> || On-chip SRAM || Always accessible
|-
| <tt>0x2200_0000 - 0x2000_C800</tt> || ||
|-
| <tt>0x2000_C800 - 0x2000_0000</tt> || Boot ROM || Executed by processor at start up
|-
| <tt>0x2000_0000 - 0x0C00_0000</tt> || ||
|-
| <tt>0x0C00_0000 - 0x0A00_0000</tt> || SDRAM Mirror 2 || Same contents as mirror 1
|-
| <tt>0x0A00_0000 - 0x0800_0000</tt> || SDRAM Mirror 1 || Needs initialization
|-
| <tt>0x0800_0000 - 0x0000_0000</tt> || ||
|-
|}

= IO Map =

{| class="wikitable"
|-
! Address !! Description !! Notes
|-
| <tt>0x3C80_0000 0x3C80_0004</tt> || WDTCON WDTCNT || Watchdog timer<ref name="datasheet" />
|-
| <tt>0x38E0_0000 - 0x38E0_1000 0x38E0_1000 - 0x38E0_2000</tt> || VIC0 Base VIC1 Base || Vectored Interrupt Controller<ref name="vic_ds" />
|-
|}

<references>
<ref name="datasheet">See [[S5L8700 datasheet]]</ref>
<ref name="vic_ds">ARM PrimeCell Vectored Interrupt Controller (PL192) - [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0273a/DDI0273.pdf Datasheet]
</references>

Nano 3G/Memory Map

2011-05-22T01:05:25Z

Yuriks: Added _ spacers

{| class="wikitable"
|-
! Address !! Description !! Notes
|-
| <tt>0xFFFF_FFFF - 0x4000_0000</tt> || ||
|-
| <tt>0x3FFF_FFFF - 0x3800_0000</tt> || I/O Area || See table below
|-
| <tt>0x37FF_FFFF - 0x2204_0000</tt> || ||
|-
| <tt>0x2203_FFFF - 0x2200_0000</tt> || On-chip SRAM || Always accessible
|-
| <tt>0x21FF_FFFF - 0x2000_C800</tt> || ||
|-
| <tt>0x2000_C7FF - 0x2000_0000</tt> || Boot ROM || Executed by processor at start up
|-
| <tt>0x1FFF_FFFF - 0x0C00_0000</tt> || ||
|-
| <tt>0x0BFF_FFFF - 0x0A00_0000</tt> || SDRAM Mirror 2 || Same contents as mirror 1
|-
| <tt>0x09FF_FFFF - 0x0800_0000</tt> || SDRAM Mirror 1 || Needs initialization
|-
| <tt>0x07FF_FFFF - 0x0000_0000</tt> || ||
|-
|}

= IO Map =

{| class="wikitable"
|-
! Address !! Description !! Notes
|-
| <tt>0x3C80_0000 0x3C80_0004</tt> || WDTCON WDTCNT || Watchdog timer<ref name="datasheet" />
|-
| <tt>0x38E0_0000 - 0x38E0_1000 0x38E0_1000 - 0x38E0_2000</tt> || VIC0 Base VIC1 Base || Vectored Interrupt Controller<ref name="vic_ds" />
|-
|}

<references>
<ref name="datasheet">See [[S5L8700 datasheet]]</ref>
<ref name="vic_ds">ARM PrimeCell Vectored Interrupt Controller (PL192) - [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0273a/DDI0273.pdf Datasheet]
</references>

Nano 3G/Memory Map

2011-05-22T01:03:59Z

Yuriks: Added VIC

{| class="wikitable"
|-
! Address !! Description !! Notes
|-
| <tt>0xFFFF FFFF - 0x4000 0000</tt> || ||
|-
| <tt>0x3FFF FFFF - 0x3800 0000</tt> || I/O Area || See table below
|-
| <tt>0x37FF FFFF - 0x2204 0000</tt> || ||
|-
| <tt>0x2203 FFFF - 0x2200 0000</tt> || On-chip SRAM || Always accessible
|-
| <tt>0x21FF FFFF - 0x2000 C800</tt> || ||
|-
| <tt>0x2000 C7FF - 0x2000 0000</tt> || Boot ROM || Executed by processor at start up
|-
| <tt>0x1FFF FFFF - 0x0C00 0000</tt> || ||
|-
| <tt>0x0BFF FFFF - 0x0A00 0000</tt> || SDRAM Mirror 2 || Same contents as mirror 1
|-
| <tt>0x09FF FFFF - 0x0800 0000</tt> || SDRAM Mirror 1 || Needs initialization
|-
| <tt>0x07FF FFFF - 0x0000 0000</tt> || ||
|-
|}

= IO Map =

{| class="wikitable"
|-
! Address !! Description !! Notes
|-
| <tt>0x3C800000 0x3C800004</tt> || WDTCON WDTCNT || Watchdog timer<ref name="datasheet" />
|-
| <tt>0x38E0_0000 - 0x38E0_1000 0x38E0_1000 - 0x38E0_2000</tt> || VIC0 Base VIC1 Base || Vectored Interrupt Controller<ref name="vic_ds" />
|-
|}

<references>
<ref name="datasheet">See [[S5L8700 datasheet]]</ref>
<ref name="vic_ds">ARM PrimeCell Vectored Interrupt Controller (PL192) - [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0273a/DDI0273.pdf Datasheet]
</references>

Nano 3G/Memory Map

2010-11-30T11:18:37Z

Yuriks:

{| class="wikitable"
|-
! Address !! Description !! Notes
|-
| <tt>0xFFFF FFFF - 0x4000 0000</tt> || ||
|-
| <tt>0x3FFF FFFF - 0x3800 0000</tt> || I/O Area || See table below
|-
| <tt>0x37FF FFFF - 0x2204 0000</tt> || ||
|-
| <tt>0x2203 FFFF - 0x2200 0000</tt> || On-chip SRAM || Always accessible
|-
| <tt>0x21FF FFFF - 0x2000 C800</tt> || ||
|-
| <tt>0x2000 C7FF - 0x2000 0000</tt> || Boot ROM || Executed by processor at start up
|-
| <tt>0x1FFF FFFF - 0x0C00 0000</tt> || ||
|-
| <tt>0x0BFF FFFF - 0x0A00 0000</tt> || SDRAM Mirror 2 || Same contents as mirror 1
|-
| <tt>0x09FF FFFF - 0x0800 0000</tt> || SDRAM Mirror 1 || Needs initialization
|-
| <tt>0x07FF FFFF - 0x0000 0000</tt> || ||
|-
|}

= IO Map =

{| class="wikitable"
|-
! Address !! Description !! Notes
|-
| <tt>0x3C800000 0x3C800004</tt> || WDTCON WDTCNT || Watchdog timer<ref name="datasheet" />
|-
|}

<references>
<ref name="datasheet">See [[S5L8700 datasheet]]</ref>
</references>

Nano 3G/Memory Map

2010-11-30T11:11:59Z

Yuriks:

Nano 3G/Memory Map

2010-11-29T12:22:38Z

Yuriks: Some other stuff

{| class="wikitable"
|-
! Address !! Description !! Notes
|-
| <tt>0xFFFF FFFF - 0x2204 0000</tt> || ||
|-
| <tt>0x2203 FFFF - 0x2200 0000</tt> || On-chip SRAM || Always accessible
|-
| <tt>0x21FF FFFF - 0x2000 C800</tt> || ||
|-
| <tt>0x2000 C7FF - 0x2000 0000</tt> || Boot ROM || Executed by processor at start up
|-
| <tt>0x1FFF FFFF - 0x0C00 0000</tt> || ||
|-
| <tt>0x0BFF FFFF - 0x0A00 0000</tt> || SDRAM Mirror 2 || Same contents as mirror 1
|-
| <tt>0x09FF FFFF - 0x0800 0000</tt> || SDRAM Mirror 1 || Needs initialization
|-
| <tt>0x07FF FFFF - 0x0000 0000</tt> || ||
|-
|}

Nano 3G/Memory Map

2010-11-29T12:06:25Z

Yuriks: Added blank sections and reversed address ranges

{| class="wikitable"
|-
! Address !! Description !! Notes
|-
| <tt>0xFFFF FFFF - 0x2204 0000</tt> || ||
|-
| <tt>0x2203 FFFF - 0x2200 0000</tt> || On-chip SRAM || Always accessible
|-
| <tt>0x0BFF FFFF - 0x0A00 0000</tt> || SDRAM Mirror 2 || Same contents as mirror 1
|-
| <tt>0x09FF FFFF - 0x0800 0000</tt> || SDRAM Mirror 1 || Needs initialization
|-
| <tt>0x07FF FFFF - 0x0000 0000</tt> || ||
|-
|}

Nano 3G/Memory Map

2010-11-29T12:03:06Z

Yuriks: crappy memory map

{| class="wikitable"
|-
! Address !! Description !! Notes
|-
| <tt>0x2200 0000 - 0x2203 FFFF</tt> || On-chip SRAM || Always accessible
|-
| <tt>0x0A00 0000 - 0x0BFF FFFF</tt> || SDRAM Mirror 2 || Same contents as mirror 1
|-
| <tt>0x0800 0000 - 0x09FF FFFF</tt> || SDRAM Mirror 1 || Needs initialization
|-
|}