<?xml version="1.0"?>
<feed xmlns="http://www.w3.org/2005/Atom" xml:lang="en">
	<id>https://freemyipod.org/api.php?action=feedcontributions&amp;feedformat=atom&amp;user=Q3k</id>
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	<updated>2026-05-17T01:54:40Z</updated>
	<subtitle>User contributions</subtitle>
	<generator>MediaWiki 1.45.1</generator>
	<entry>
		<id>https://freemyipod.org/index.php?title=Hardware&amp;diff=22250</id>
		<title>Hardware</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Hardware&amp;diff=22250"/>
		<updated>2026-04-05T14:18:35Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Overview ==&lt;br /&gt;
&lt;br /&gt;
This is just a basic comparison of each generation&#039;s main components. For a detailed hardware analysis of a generation, click on it&#039;s link.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Generation !! SoC !! CPU Core !! RAM !! NOR/Utility Flash !! Device Code Name !! SoC Family Code Name !! UpdaterFamilyID&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 1G]]&lt;br /&gt;
|PP5021C-TDF&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41856 SST39WF400A] (512KiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 14/17&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 2G]]&lt;br /&gt;
|S5L8701&lt;br /&gt;
|ARM940T&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41422 SST39WF800A] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
| M1&lt;br /&gt;
| 19/29&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|ARM926&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
| N46&lt;br /&gt;
| M1A&lt;br /&gt;
| 26&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 4G]]&lt;br /&gt;
|S5L8720&lt;br /&gt;
|ARM1176&lt;br /&gt;
|Integrated (32MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N58&lt;br /&gt;
| M2&lt;br /&gt;
| 31&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 5G]]&lt;br /&gt;
|S5L8730&lt;br /&gt;
|ARM1176&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N33&lt;br /&gt;
| M2&lt;br /&gt;
| 34&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 6G|Nano 6G]]&lt;br /&gt;
|S5L8723&lt;br /&gt;
|ARM1176&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N20&lt;br /&gt;
|&lt;br /&gt;
| 36&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 7G|Nano 7G]]&lt;br /&gt;
|S5L8740&lt;br /&gt;
|Cortex A5&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N31&lt;br /&gt;
| M2R&amp;lt;ref&amp;gt;m2rfmssWriteBLPage in 1.0.4 RetailOS&amp;lt;/ref&amp;gt;&lt;br /&gt;
| 37&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 1G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|ARM926&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|N25&lt;br /&gt;
| M1A&lt;br /&gt;
| 24&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 2G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|ARM926&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|N25&lt;br /&gt;
| M1A&lt;br /&gt;
| 33&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|ARM926&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X51163PE] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|N25&lt;br /&gt;
| M1A&lt;br /&gt;
| 35/38&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
=== Explanations ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Device Code Name&#039;&#039;&#039;: product code name, from early prototype phases to production run device. Most commonly used internal reference.&lt;br /&gt;
* &#039;&#039;&#039;SoC Family Code Name&#039;&#039;&#039;: device family code name, seems to follow large generational changes in SoC. Mostly seen around hardware (init) code, eg. flash interface, diags, etc.&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Chip analyses&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPod_Touch-whatsinside-57.aspx&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPhone-whatsinside-4.aspx&lt;br /&gt;
Additional information&lt;br /&gt;
*http://dendrites.blog.163.com/blog/static/165376178201082112922174/&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
==Notes==&lt;br /&gt;
&amp;lt;references /&amp;gt;&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Working_with_binaries&amp;diff=22174</id>
		<title>Working with binaries</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Working_with_binaries&amp;diff=22174"/>
		<updated>2025-09-25T21:44:39Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;==GNU ARM toolchain==&lt;br /&gt;
&lt;br /&gt;
Use gcc-arm-embedded from your Linux distribution package manager.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Hardware&amp;diff=22173</id>
		<title>Hardware</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Hardware&amp;diff=22173"/>
		<updated>2025-09-19T22:56:11Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Overview ==&lt;br /&gt;
&lt;br /&gt;
This is just a basic comparison of each generation&#039;s main components. For a detailed hardware analysis of a generation, click on it&#039;s link.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Generation !! SoC !! CPU Core !! RAM !! NOR/Utility Flash !! Device Code Name !! SoC Family Code Name !! UpdaterFamilyID&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 1G]]&lt;br /&gt;
|PP5021C-TDF&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41856 SST39WF400A] (512KiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 14/17&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 2G]]&lt;br /&gt;
|S5L8701&lt;br /&gt;
|ARM940T&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41422 SST39WF800A] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
| M1&lt;br /&gt;
| 19/29&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|ARM926&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
| N46&lt;br /&gt;
| M1A&lt;br /&gt;
| 26&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 4G]]&lt;br /&gt;
|S5L8720&lt;br /&gt;
|&lt;br /&gt;
|Integrated (32MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N58&lt;br /&gt;
| M2&lt;br /&gt;
| 31&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 5G]]&lt;br /&gt;
|S5L8730&lt;br /&gt;
|ARM1176&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N33&lt;br /&gt;
| M2&lt;br /&gt;
| 34&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 6G|Nano 6G]]&lt;br /&gt;
|S5L8723&lt;br /&gt;
|&lt;br /&gt;
|Integrated&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N20&lt;br /&gt;
|&lt;br /&gt;
| 36&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 7G|Nano 7G]]&lt;br /&gt;
|S5L8740&lt;br /&gt;
|Cortex A5&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N31&lt;br /&gt;
| H4&lt;br /&gt;
| 37&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 1G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 24&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 2G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 33&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X51163PE] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 35/38&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
=== Explanations ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Device Code Name&#039;&#039;&#039;: product code name, from early prototype phases to production run device. Most commonly used internal reference.&lt;br /&gt;
* &#039;&#039;&#039;SoC Family Code Name&#039;&#039;&#039;: device family code name, seems to follow large generational changes in SoC. Mostly seen around hardware (init) code, eg. flash interface, diags, etc.&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Chip analyses&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPod_Touch-whatsinside-57.aspx&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPhone-whatsinside-4.aspx&lt;br /&gt;
Additional information&lt;br /&gt;
*http://dendrites.blog.163.com/blog/static/165376178201082112922174/&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Hardware&amp;diff=22171</id>
		<title>Hardware</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Hardware&amp;diff=22171"/>
		<updated>2025-08-05T19:29:28Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* Overview */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Overview ==&lt;br /&gt;
&lt;br /&gt;
This is just a basic comparison of each generation&#039;s main components. For a detailed hardware analysis of a generation, click on it&#039;s link.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Generation !! SoC !! CPU Core !! RAM !! NOR/Utility Flash !! Device Code Name !! SoC Family Code Name !! UpdaterFamilyID&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 1G]]&lt;br /&gt;
|PP5021C-TDF&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41856 SST39WF400A] (512KiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 14/17&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 2G]]&lt;br /&gt;
|S5L8701&lt;br /&gt;
|ARM940T&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41422 SST39WF800A] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
| M1&lt;br /&gt;
| 19/29&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|ARM926&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
| N46&lt;br /&gt;
| M1&lt;br /&gt;
| 26&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 4G]]&lt;br /&gt;
|S5L8720&lt;br /&gt;
|&lt;br /&gt;
|Integrated (32MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N58&lt;br /&gt;
| M2&lt;br /&gt;
| 31&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 5G]]&lt;br /&gt;
|S5L8730&lt;br /&gt;
|ARM1176&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N33&lt;br /&gt;
| M2&lt;br /&gt;
| 34&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 6G|Nano 6G]]&lt;br /&gt;
|S5L8723&lt;br /&gt;
|&lt;br /&gt;
|Integrated&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N20&lt;br /&gt;
|&lt;br /&gt;
| 36&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 7G|Nano 7G]]&lt;br /&gt;
|S5L8740&lt;br /&gt;
|Cortex A5&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N31&lt;br /&gt;
| H4&lt;br /&gt;
| 37&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 1G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 24&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 2G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 33&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X51163PE] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 35/38&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
=== Explanations ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Device Code Name&#039;&#039;&#039;: product code name, from early prototype phases to production run device. Most commonly used internal reference.&lt;br /&gt;
* &#039;&#039;&#039;SoC Family Code Name&#039;&#039;&#039;: device family code name, seems to follow large generational changes in SoC. Mostly seen around hardware (init) code, eg. flash interface, diags, etc.&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Chip analyses&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPod_Touch-whatsinside-57.aspx&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPhone-whatsinside-4.aspx&lt;br /&gt;
Additional information&lt;br /&gt;
*http://dendrites.blog.163.com/blog/static/165376178201082112922174/&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Hardware&amp;diff=22170</id>
		<title>Hardware</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Hardware&amp;diff=22170"/>
		<updated>2025-08-05T19:28:55Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* Overview */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Overview ==&lt;br /&gt;
&lt;br /&gt;
This is just a basic comparison of each generation&#039;s main components. For a detailed hardware analysis of a generation, click on it&#039;s link.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Generation !! SoC !! CPU Core !! RAM !! NOR/Utility Flash !! Device Code Name !! SoC Family Code Name !! UpdaterFamilyID&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 1G]]&lt;br /&gt;
|PP5021C-TDF&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41856 SST39WF400A] (512KiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 14/17&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 2G]]&lt;br /&gt;
|S5L8701&lt;br /&gt;
|ARM940T&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41422 SST39WF800A] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
| M1&lt;br /&gt;
| 19/29&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|ARM926&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
| N46&lt;br /&gt;
| M1&lt;br /&gt;
| 26&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 4G]]&lt;br /&gt;
|S5L8720&lt;br /&gt;
|&lt;br /&gt;
|Integrated (32MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N58&lt;br /&gt;
| M2&lt;br /&gt;
| 31&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 5G]]&lt;br /&gt;
|S5L8730&lt;br /&gt;
|ARM1176&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N33&lt;br /&gt;
| M2&lt;br /&gt;
| 34&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 6G|Nano 6G]]&lt;br /&gt;
|S5L8723&lt;br /&gt;
|&lt;br /&gt;
|Integrated&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N20&lt;br /&gt;
|&lt;br /&gt;
| 36&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 7G|Nano 7G]]&lt;br /&gt;
|S5L8740&lt;br /&gt;
|&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N31&lt;br /&gt;
| H4&lt;br /&gt;
| 37&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 1G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 24&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 2G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 33&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X51163PE] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 35/38&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
=== Explanations ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Device Code Name&#039;&#039;&#039;: product code name, from early prototype phases to production run device. Most commonly used internal reference.&lt;br /&gt;
* &#039;&#039;&#039;SoC Family Code Name&#039;&#039;&#039;: device family code name, seems to follow large generational changes in SoC. Mostly seen around hardware (init) code, eg. flash interface, diags, etc.&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Chip analyses&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPod_Touch-whatsinside-57.aspx&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPhone-whatsinside-4.aspx&lt;br /&gt;
Additional information&lt;br /&gt;
*http://dendrites.blog.163.com/blog/static/165376178201082112922174/&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Hardware&amp;diff=22169</id>
		<title>Hardware</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Hardware&amp;diff=22169"/>
		<updated>2025-08-05T19:25:38Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Overview ==&lt;br /&gt;
&lt;br /&gt;
This is just a basic comparison of each generation&#039;s main components. For a detailed hardware analysis of a generation, click on it&#039;s link.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Generation !! SoC !! CPU Core !! RAM !! NOR/Utility Flash !! Device Code Name !! SoC Family Code Name !! UpdaterFamilyID&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 1G]]&lt;br /&gt;
|PP5021C-TDF&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41856 SST39WF400A] (512KiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 14/17&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 2G]]&lt;br /&gt;
|S5L8701&lt;br /&gt;
|ARM940T&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41422 SST39WF800A] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
| M1&lt;br /&gt;
| 19/29&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|ARM926&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
| N46&lt;br /&gt;
| M1&lt;br /&gt;
| 26&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 4G]]&lt;br /&gt;
|S5L8720&lt;br /&gt;
|&lt;br /&gt;
|Integrated (32MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N58&lt;br /&gt;
|&lt;br /&gt;
| 31&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 5G]]&lt;br /&gt;
|S5L8730&lt;br /&gt;
|ARM1176&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N33&lt;br /&gt;
| M2&lt;br /&gt;
| 34&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 6G|Nano 6G]]&lt;br /&gt;
|S5L8723&lt;br /&gt;
|&lt;br /&gt;
|Integrated&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N20&lt;br /&gt;
|&lt;br /&gt;
| 36&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 7G|Nano 7G]]&lt;br /&gt;
|S5L8740&lt;br /&gt;
|&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N31&lt;br /&gt;
| H4&lt;br /&gt;
| 37&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 1G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 24&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 2G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 33&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X51163PE] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 35/38&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
=== Explanations ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Device Code Name&#039;&#039;&#039;: product code name, from early prototype phases to production run device. Most commonly used internal reference.&lt;br /&gt;
* &#039;&#039;&#039;SoC Family Code Name&#039;&#039;&#039;: device family code name, seems to follow large generational changes in SoC. Mostly seen around hardware (init) code, eg. flash interface, diags, etc.&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Chip analyses&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPod_Touch-whatsinside-57.aspx&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPhone-whatsinside-4.aspx&lt;br /&gt;
Additional information&lt;br /&gt;
*http://dendrites.blog.163.com/blog/static/165376178201082112922174/&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Hardware&amp;diff=22168</id>
		<title>Hardware</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Hardware&amp;diff=22168"/>
		<updated>2025-08-05T19:22:54Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Overview ==&lt;br /&gt;
&lt;br /&gt;
This is just a basic comparison of each generation&#039;s main components. For a detailed hardware analysis of a generation, click on it&#039;s link.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Generation !! SoC !! RAM !! NOR/Utility Flash !! Device Code Name !! SoC Family Code Name !! UpdaterFamilyID&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 1G]]&lt;br /&gt;
|PP5021C-TDF&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41856 SST39WF400A] (512KiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 14/17&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 2G]]&lt;br /&gt;
|S5L8701&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41422 SST39WF800A] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
| M1&lt;br /&gt;
| 19/29&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
| N46&lt;br /&gt;
|&lt;br /&gt;
| 26&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 4G]]&lt;br /&gt;
|S5L8720&lt;br /&gt;
|Integrated (32MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N58&lt;br /&gt;
|&lt;br /&gt;
| 31&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 5G]]&lt;br /&gt;
|S5L8730&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N33&lt;br /&gt;
| M2&lt;br /&gt;
| 34&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 6G|Nano 6G]]&lt;br /&gt;
|S5L8723&lt;br /&gt;
|Integrated&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N20&lt;br /&gt;
|&lt;br /&gt;
| 36&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 7G|Nano 7G]]&lt;br /&gt;
|S5L8740&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N31&lt;br /&gt;
| H4&lt;br /&gt;
| 37&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 1G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 24&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 2G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 33&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X51163PE] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 35/38&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
=== Explanations ===&lt;br /&gt;
&lt;br /&gt;
* &#039;&#039;&#039;Device Code Name&#039;&#039;&#039;: product code name, from early prototype phases to production run device. Most commonly used internal reference.&lt;br /&gt;
* &#039;&#039;&#039;SoC Family Code Name&#039;&#039;&#039;: device family code name, seems to follow large generational changes in SoC. Mostly seen around hardware (init) code, eg. flash interface, diags, etc.&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Chip analyses&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPod_Touch-whatsinside-57.aspx&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPhone-whatsinside-4.aspx&lt;br /&gt;
Additional information&lt;br /&gt;
*http://dendrites.blog.163.com/blog/static/165376178201082112922174/&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Hardware&amp;diff=22167</id>
		<title>Hardware</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Hardware&amp;diff=22167"/>
		<updated>2025-08-05T19:17:51Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;This is just a basic comparison of each generation&#039;s main components. For a detailed hardware analysis of a generation, click on it&#039;s link.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Generation !! SoC !! RAM !! NOR/Utility Flash !! Device Code Name !! UpdaterFamilyID&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 1G]]&lt;br /&gt;
|PP5021C-TDF&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41856 SST39WF400A] (512KiB)&lt;br /&gt;
|&lt;br /&gt;
| 14/17&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 2G]]&lt;br /&gt;
|S5L8701&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41422 SST39WF800A] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
| 19/29&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
| N46&lt;br /&gt;
| 26&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 4G]]&lt;br /&gt;
|S5L8720&lt;br /&gt;
|Integrated (32MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N58&lt;br /&gt;
| 31&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 5G]]&lt;br /&gt;
|S5L8730&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N33&lt;br /&gt;
| 34&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 6G|Nano 6G]]&lt;br /&gt;
|S5L8723&lt;br /&gt;
|Integrated&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N20&lt;br /&gt;
| 36&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 7G|Nano 7G]]&lt;br /&gt;
|S5L8740&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N31&lt;br /&gt;
| 37&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 1G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
| 24&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 2G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
| 33&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X51163PE] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
| 35/38&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
Concerning the detailed generation pages: If you can prove or disprove any of these chip names, please let us know: [[Contact]]&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Chip analyses&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPod_Touch-whatsinside-57.aspx&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPhone-whatsinside-4.aspx&lt;br /&gt;
Additional information&lt;br /&gt;
*http://dendrites.blog.163.com/blog/static/165376178201082112922174/&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=IMG1&amp;diff=22117</id>
		<title>IMG1</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=IMG1&amp;diff=22117"/>
		<updated>2025-05-05T01:23:28Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* Verification Routine */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Introduction ==&lt;br /&gt;
&lt;br /&gt;
IMG1 is a pseudonym for the image format used by early iOS devices and all S5L-based iPods.&lt;br /&gt;
&lt;br /&gt;
It is sometimes called the &#039;8900&#039; image, which is how it was called on the original iPhone / S5L8900. It is also sometimes called the &#039;DFU image&#039; format (because it&#039;s used in DFU mode to load WTF).&lt;br /&gt;
&lt;br /&gt;
The iPhone Wiki has some basic [https://www.theiphonewiki.com/wiki/S5L_File_Formats#8900 information about the format]. However, that only describes the &#039;1.0&#039; version of IMG1. The lineage of IMG1 has continued in iPods long after iOS-based devices stopped its use, with IMG2/IMG3 never making it to the newer non-Touch iPods. Here we describe the known usage of IMG1, including its 2.0 version, in clickwheel iPods and non-iBoot bootroms.&lt;br /&gt;
&lt;br /&gt;
== Header Format ==&lt;br /&gt;
&lt;br /&gt;
  struct IMG1 {&lt;br /&gt;
    u8 magic[4];            // 0x0, SoC digits, eg. `8720`.&lt;br /&gt;
    u8 version[3];          // 0x4, `1.0` or `2.0`&lt;br /&gt;
    u8 format;              // 0x7, Encryption/signature format. See below.&lt;br /&gt;
    u32 entrypoint;         // 0x8, Offset to jump to within body (after header).&lt;br /&gt;
    u32 bodyLen;            // 0xC, Size of the image body, ie. the data loaded into memory, before the&lt;br /&gt;
                            // signature/certificates start, after the header.&lt;br /&gt;
    u32 dataLen;            // 0x10, Size of everything that&#039;s not the header (body + signature + certificates).&lt;br /&gt;
    u32 footerCertOffset;   // 0x14, Offset of certificate start (after header).&lt;br /&gt;
    u32 footerCertLen;      // 0x18, Size of certificate bundle.&lt;br /&gt;
    u8 salt[32];            // 0x1C, Random data.&lt;br /&gt;
    u16 unk1;               // 0x3C&lt;br /&gt;
    u16 unk2;               // 0x3E, Security epoch?&lt;br /&gt;
    u8 headerSign[16];      // 0x40, AES-encrypted SHA1 signature of everything up to headerSign.&lt;br /&gt;
    u8 headerLeftover[4];   // 0x50, Last four bytes of unencrypted SHA1, usually leftover in images, but not&lt;br /&gt;
                            // checked by firmware. Curiosity.&lt;br /&gt;
  }&lt;br /&gt;
&lt;br /&gt;
The body is padded to either 0x800 (S5L8900 (iOS)/S5L8702), 0x600 (S5L8720/S5L8930) or 0x400 (S5L8723/S5L8740) bytes. The different sections are a bit tricky to reason about, here&#039;s an attempted overview:&lt;br /&gt;
&lt;br /&gt;
  0:     Header (0x40 + 0x14 bytes, first 0x40 signed into last 0x14 bytes)&lt;br /&gt;
  0x54:  Padding until $header_size (magic dependent, 0x600 in this example) &lt;br /&gt;
  0x600: Body, bodyLen bytes.&lt;br /&gt;
  ...&lt;br /&gt;
  0x600 + bodyLen: body signature (for X509 formats)&lt;br /&gt;
  0x680 + bodyLen (also 0x600+footerCertLen): certificate bundle (for X509 formats)&lt;br /&gt;
  0x680 + bodyLen + footerCertLen: end of file.&lt;br /&gt;
&lt;br /&gt;
The body signature is always 0x80 bytes long, and its length is not counted into bodyLen or footerCertLen.&lt;br /&gt;
&lt;br /&gt;
A few assertions should hold for non-Touch iPods:&lt;br /&gt;
&lt;br /&gt;
# File size == $header_size + bodyLen + footerCertLen + 0x80&lt;br /&gt;
# dataLen = bodyLen + 0x80 + footerCertLen&lt;br /&gt;
&lt;br /&gt;
It is worth noting that for early iOS devices, dataLen is actually the offset to the body signature. It is unknown why Apple has changed this to the data length.&lt;br /&gt;
&lt;br /&gt;
=== Encryption/Signature Formats ===&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Format (number) !! Header signed (SHA1+AES) !! Body encrypted !! Body signed (X509/RSA) !! AES Operation !! Notes&lt;br /&gt;
|-&lt;br /&gt;
| SIGNED_ENCRYPTED (1) || ✅ || ✅ || ❌ || Encryption, Global/GID Key || Not accepted in 2.0.&lt;br /&gt;
|-&lt;br /&gt;
| SIGNED (2) || ✅ || ❌ || ❌ || Encryption, Global/GID Key || Not accepted in 2.0.&lt;br /&gt;
|-&lt;br /&gt;
| X509_SIGNED_ENCRYPTED (3) || ✅ || ✅ || ✅|| Decryption, Global/GID Key || Most (all?) released images have this type&lt;br /&gt;
|-&lt;br /&gt;
| X509_SIGNED (4) || ✅ || ❌ || ✅ || Decryption, Global/GID Key ||&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
DFU mode in N3G, N4G, N5G seems only accepts X509_SIGNED_ENCRYPTED.&lt;br /&gt;
&lt;br /&gt;
Other boot modes (notably in N3G) seem to accept other formats, but that&#039;s to be verified. N4G+/2.0 do not accept any non-X509 formats.&lt;br /&gt;
&lt;br /&gt;
=== Differences between v1.0 and 2.0 ===&lt;br /&gt;
&lt;br /&gt;
Nano4G+ use 2.0. Everything else uses 1.0.&lt;br /&gt;
&lt;br /&gt;
1.0 bootroms supports encryption formats 1, 2, 3 and 4. 2.0 only supports encryption formats 3 and 4.&lt;br /&gt;
&lt;br /&gt;
When uploading IMG1 images via DFU, 1.0 images need to be suffixed with a CRC32 of their content. 2.0 images don&#039;t need the CRC32.&lt;br /&gt;
&lt;br /&gt;
=== Differences between iBoot/SecureROM and iPod images ===&lt;br /&gt;
&lt;br /&gt;
The iPod images do not use &#039;Key 0x837&#039;, and in fact use the Global/GID key for all AES operations.&lt;br /&gt;
&lt;br /&gt;
The iPod images are sometimes decrypted using the encrypt direction of the AES engine (formats 1 and 2) and sometimes with the decrypt direction of the AES engine (formats 3 and 4). iBoot/SecureROM images seem to all use the decrypt direction.&lt;br /&gt;
&lt;br /&gt;
=== Leftover SHA in header ===&lt;br /&gt;
&lt;br /&gt;
It seems like whatever generates IMG1 images does so in the following pseudocode:&lt;br /&gt;
&lt;br /&gt;
  sha1(src=data, srcLen=0x40, dst=data+0x40)&lt;br /&gt;
  aes(src=data+0x40, size=0x10)&lt;br /&gt;
  // data is ready, ship it!&lt;br /&gt;
&lt;br /&gt;
As after the 0x10 bytes of the AES-encrypted SHA1 signature, there are 4 bytes of unencrypted SHA1 (because a SHA1 digest is 0x14 bytes, while an AES128 block is 0x10 bytes). This means that you can check the header signature yourself (or, well, 32 bits of the signature) by performing the following:&lt;br /&gt;
&lt;br /&gt;
  sha1(data[0:0x40]).digest()[-4:] == data[0x50:0x54]&lt;br /&gt;
&lt;br /&gt;
This has likely zero security implications, but is nonetheless a fascinating curiosity.&lt;br /&gt;
&lt;br /&gt;
== Verification Routine ==&lt;br /&gt;
&lt;br /&gt;
There are 2 signatures that are verified by the loader (BootROM or LLB/WTF), those being the header signature and the body signature. &lt;br /&gt;
&lt;br /&gt;
The header signature in full is verified by taking the SHA1 digest of data[0:0x40], encrypting it with the Global/GID key, and comparing it with the signature contained in the header.&lt;br /&gt;
&lt;br /&gt;
The body signature is verified by first finding the leaf certificate, taking the public key from it, then verifying the body signature with the body data (defined as data[bodyPad:bodyPad + bodyLen]) and the public key.&lt;br /&gt;
&lt;br /&gt;
The certificate bundle is verified by ensuring the leaf certificate in the chain has a serial starting with &amp;lt;code&amp;gt;01:fb:01:fb&amp;lt;/code&amp;gt; (production devices, dev devices) or &amp;lt;code&amp;gt;01:fb:00:fb&amp;lt;/code&amp;gt; (dev devices). The root certificate in the chain must have a SHA singerprint that matches one hardcoded in the BootROM (&amp;lt;code&amp;gt;61:1e:5b:66:2c:59:3a:08:ff:58:d1:4a:e2:24:52:d1:98:df:6c:60&amp;lt;/code&amp;gt;, Apple Root CA). In additional, string comparisons are performed against the root and leaf subject CNs.&lt;br /&gt;
&lt;br /&gt;
== Parsing Decrypted IMG1 Files ==&lt;br /&gt;
&lt;br /&gt;
With the development of the [[wInd3x]] exploit and its [https://github.com/freemyipod/wInd3x implementation] it has become possible to decrypt IMG1 files on the [[Nano_4G|iPod Nano 4g]] and [[Nano_5G|iPod Nano 5g]]. The [[Nano_4G|iPod Nano 4g]] has two separate sets of firmware available, firmware intended to interface with the [[Nano_4G|iPod Nano 4g]] hardware through DFU mode to assist with the restoration of the iPod to factory settings and the general retail firmware that is intended to be used by the consumer. Both sets of firmware can be obtained by following the links available [https://itunes.apple.com/WebObjects/MZStore.woa/wa/com.apple.jingle.appserver.client.MZITunesClientCheck/version?touchUpdate=true here]. In particular the `x12250000_Recovery.ipsw` file contains the WTF firmware (WTF.x1225.release.dfu) that interacts with DFU mode and the `iPod_31.1.0.4.ipsw` contains the bootloader (N58s.bootloader.release.rb3) and the rest of the [[RetailOS]].&lt;br /&gt;
&lt;br /&gt;
To assist with development for the Nano 4G hardware, it is important to understand the drivers that are included in these IMG1 files.&lt;br /&gt;
&lt;br /&gt;
These drivers are included as part of the (U)EFI image that is contained within the IMG1 file.&lt;br /&gt;
&lt;br /&gt;
For the nano4g, the first 0x700 bytes of the IMG1 contains a header that is discussed above. The rest of the file contains a what seems to be a UEFI firmware partition. Some of the information about UEFI firmware from the [https://en.wikipedia.org/wiki/UEFI Wikipedia page] seems relevant to understand this partition as well as the [https://wiki.osdev.org/UEFI OS Dev wiki page on UEFI development], which discusses UEFI applications and seems to be the format for some of the files included within the IMG1 volume.&lt;br /&gt;
&lt;br /&gt;
Using The uefi-firmware-parser package [https://github.com/theopolis/uefi-firmware-parser available here], it is possible to extract the files in this EFI volume. The files in the partition can be extracted by removing the first 0x700 bytes (Nano 4g) of the decrypted IMG1 file. This can be done with a hex editor or other tools. Furthermore, this step can be skipped if the option `-b` is used below. It is also recommended to setup a separate Conda environment to use with this tool. The files can be extracted as follows:&lt;br /&gt;
&lt;br /&gt;
  uefi-firmware-parser -o out/ -e decrypted_efi_firmware_filename_here&lt;br /&gt;
&lt;br /&gt;
The benefit of this approach is this will extracted all drivers included in the EFI firmware volume and also decompress each driver. The next step in the process is to identify the function of each driver. For this Apple was helpful enough to not strip out the name of each driver inside each driver file. The mapping from the file GUIDs to their functions can be recovered in many ways, but here is a simple script to print out the mapping:&lt;br /&gt;
&lt;br /&gt;
  for ii in `find out/ | grep &amp;quot;\.pe&amp;quot;`;&lt;br /&gt;
    do echo $ii | cut -d &#039;/&#039; -f 3 | cut -d &#039;-&#039; -f 2-; &lt;br /&gt;
    strings $ii | tail -n 1 | rev | cut -d &#039;/&#039; -f 1 | rev| cut -d &#039;.&#039; -f 1;&lt;br /&gt;
    echo; &lt;br /&gt;
  done&lt;br /&gt;
&lt;br /&gt;
There is an addition .te file that contains the executable code that is jumped to from Secure Boot.&lt;br /&gt;
&lt;br /&gt;
The extracted firmware PE files will contain a valid PE file header and will begin with the &amp;quot;MZ&amp;quot; magic bytes. It may be helpful to use [https://github.com/blackberry/pe_tree PE Tree] to parse these headers and inspect these files. Manual inspection with a hex editor can be done as well. Some information about PE file headers is available [https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#section-table-section-headers here].&lt;br /&gt;
&lt;br /&gt;
The above instructions assume a Nano 4g IMG1 WTF file or Bootloader. See [https://github.com/freemyipod/defs/blob/main/efi.py here] for more information about the Nano 5g IMG1 structure.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=IMG1&amp;diff=22116</id>
		<title>IMG1</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=IMG1&amp;diff=22116"/>
		<updated>2025-05-05T01:21:27Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Introduction ==&lt;br /&gt;
&lt;br /&gt;
IMG1 is a pseudonym for the image format used by early iOS devices and all S5L-based iPods.&lt;br /&gt;
&lt;br /&gt;
It is sometimes called the &#039;8900&#039; image, which is how it was called on the original iPhone / S5L8900. It is also sometimes called the &#039;DFU image&#039; format (because it&#039;s used in DFU mode to load WTF).&lt;br /&gt;
&lt;br /&gt;
The iPhone Wiki has some basic [https://www.theiphonewiki.com/wiki/S5L_File_Formats#8900 information about the format]. However, that only describes the &#039;1.0&#039; version of IMG1. The lineage of IMG1 has continued in iPods long after iOS-based devices stopped its use, with IMG2/IMG3 never making it to the newer non-Touch iPods. Here we describe the known usage of IMG1, including its 2.0 version, in clickwheel iPods and non-iBoot bootroms.&lt;br /&gt;
&lt;br /&gt;
== Header Format ==&lt;br /&gt;
&lt;br /&gt;
  struct IMG1 {&lt;br /&gt;
    u8 magic[4];            // 0x0, SoC digits, eg. `8720`.&lt;br /&gt;
    u8 version[3];          // 0x4, `1.0` or `2.0`&lt;br /&gt;
    u8 format;              // 0x7, Encryption/signature format. See below.&lt;br /&gt;
    u32 entrypoint;         // 0x8, Offset to jump to within body (after header).&lt;br /&gt;
    u32 bodyLen;            // 0xC, Size of the image body, ie. the data loaded into memory, before the&lt;br /&gt;
                            // signature/certificates start, after the header.&lt;br /&gt;
    u32 dataLen;            // 0x10, Size of everything that&#039;s not the header (body + signature + certificates).&lt;br /&gt;
    u32 footerCertOffset;   // 0x14, Offset of certificate start (after header).&lt;br /&gt;
    u32 footerCertLen;      // 0x18, Size of certificate bundle.&lt;br /&gt;
    u8 salt[32];            // 0x1C, Random data.&lt;br /&gt;
    u16 unk1;               // 0x3C&lt;br /&gt;
    u16 unk2;               // 0x3E, Security epoch?&lt;br /&gt;
    u8 headerSign[16];      // 0x40, AES-encrypted SHA1 signature of everything up to headerSign.&lt;br /&gt;
    u8 headerLeftover[4];   // 0x50, Last four bytes of unencrypted SHA1, usually leftover in images, but not&lt;br /&gt;
                            // checked by firmware. Curiosity.&lt;br /&gt;
  }&lt;br /&gt;
&lt;br /&gt;
The body is padded to either 0x800 (S5L8900 (iOS)/S5L8702), 0x600 (S5L8720/S5L8930) or 0x400 (S5L8723/S5L8740) bytes. The different sections are a bit tricky to reason about, here&#039;s an attempted overview:&lt;br /&gt;
&lt;br /&gt;
  0:     Header (0x40 + 0x14 bytes, first 0x40 signed into last 0x14 bytes)&lt;br /&gt;
  0x54:  Padding until $header_size (magic dependent, 0x600 in this example) &lt;br /&gt;
  0x600: Body, bodyLen bytes.&lt;br /&gt;
  ...&lt;br /&gt;
  0x600 + bodyLen: body signature (for X509 formats)&lt;br /&gt;
  0x680 + bodyLen (also 0x600+footerCertLen): certificate bundle (for X509 formats)&lt;br /&gt;
  0x680 + bodyLen + footerCertLen: end of file.&lt;br /&gt;
&lt;br /&gt;
The body signature is always 0x80 bytes long, and its length is not counted into bodyLen or footerCertLen.&lt;br /&gt;
&lt;br /&gt;
A few assertions should hold for non-Touch iPods:&lt;br /&gt;
&lt;br /&gt;
# File size == $header_size + bodyLen + footerCertLen + 0x80&lt;br /&gt;
# dataLen = bodyLen + 0x80 + footerCertLen&lt;br /&gt;
&lt;br /&gt;
It is worth noting that for early iOS devices, dataLen is actually the offset to the body signature. It is unknown why Apple has changed this to the data length.&lt;br /&gt;
&lt;br /&gt;
=== Encryption/Signature Formats ===&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Format (number) !! Header signed (SHA1+AES) !! Body encrypted !! Body signed (X509/RSA) !! AES Operation !! Notes&lt;br /&gt;
|-&lt;br /&gt;
| SIGNED_ENCRYPTED (1) || ✅ || ✅ || ❌ || Encryption, Global/GID Key || Not accepted in 2.0.&lt;br /&gt;
|-&lt;br /&gt;
| SIGNED (2) || ✅ || ❌ || ❌ || Encryption, Global/GID Key || Not accepted in 2.0.&lt;br /&gt;
|-&lt;br /&gt;
| X509_SIGNED_ENCRYPTED (3) || ✅ || ✅ || ✅|| Decryption, Global/GID Key || Most (all?) released images have this type&lt;br /&gt;
|-&lt;br /&gt;
| X509_SIGNED (4) || ✅ || ❌ || ✅ || Decryption, Global/GID Key ||&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
DFU mode in N3G, N4G, N5G seems only accepts X509_SIGNED_ENCRYPTED.&lt;br /&gt;
&lt;br /&gt;
Other boot modes (notably in N3G) seem to accept other formats, but that&#039;s to be verified. N4G+/2.0 do not accept any non-X509 formats.&lt;br /&gt;
&lt;br /&gt;
=== Differences between v1.0 and 2.0 ===&lt;br /&gt;
&lt;br /&gt;
Nano4G+ use 2.0. Everything else uses 1.0.&lt;br /&gt;
&lt;br /&gt;
1.0 bootroms supports encryption formats 1, 2, 3 and 4. 2.0 only supports encryption formats 3 and 4.&lt;br /&gt;
&lt;br /&gt;
When uploading IMG1 images via DFU, 1.0 images need to be suffixed with a CRC32 of their content. 2.0 images don&#039;t need the CRC32.&lt;br /&gt;
&lt;br /&gt;
=== Differences between iBoot/SecureROM and iPod images ===&lt;br /&gt;
&lt;br /&gt;
The iPod images do not use &#039;Key 0x837&#039;, and in fact use the Global/GID key for all AES operations.&lt;br /&gt;
&lt;br /&gt;
The iPod images are sometimes decrypted using the encrypt direction of the AES engine (formats 1 and 2) and sometimes with the decrypt direction of the AES engine (formats 3 and 4). iBoot/SecureROM images seem to all use the decrypt direction.&lt;br /&gt;
&lt;br /&gt;
=== Leftover SHA in header ===&lt;br /&gt;
&lt;br /&gt;
It seems like whatever generates IMG1 images does so in the following pseudocode:&lt;br /&gt;
&lt;br /&gt;
  sha1(src=data, srcLen=0x40, dst=data+0x40)&lt;br /&gt;
  aes(src=data+0x40, size=0x10)&lt;br /&gt;
  // data is ready, ship it!&lt;br /&gt;
&lt;br /&gt;
As after the 0x10 bytes of the AES-encrypted SHA1 signature, there are 4 bytes of unencrypted SHA1 (because a SHA1 digest is 0x14 bytes, while an AES128 block is 0x10 bytes). This means that you can check the header signature yourself (or, well, 32 bits of the signature) by performing the following:&lt;br /&gt;
&lt;br /&gt;
  sha1(data[0:0x40]).digest()[-4:] == data[0x50:0x54]&lt;br /&gt;
&lt;br /&gt;
This has likely zero security implications, but is nonetheless a fascinating curiosity.&lt;br /&gt;
&lt;br /&gt;
== Verification Routine ==&lt;br /&gt;
&lt;br /&gt;
There are 2 signatures that may be verified, those being the header signature and the body signature. &lt;br /&gt;
&lt;br /&gt;
The header signature in full may be verified by taking the SHA1 digest of data[0:0x40], encrypting it with the Global/GID key, and comparing it with the header signature.&lt;br /&gt;
&lt;br /&gt;
The body signature may be verified by first finding the leaf certificate, taking the public key from it, then verifying the body signature with the body data (defined as data[bodyPad:bodyPad + bodyLen]) and the public key.&lt;br /&gt;
&lt;br /&gt;
The body signature is then verified against the X.509 certificate chain provided after the signature. The leaf certificate in the chain must be emitted for the given signature and have a serial starting with &amp;lt;code&amp;gt;01:fb:01:fb&amp;lt;/code&amp;gt; (production devices, dev devices) or &amp;lt;code&amp;gt;01:fb:00:fb&amp;lt;/code&amp;gt; (dev devices). The root certificate in the chain must have a SHA singerprint that matches one hardcoded in the BootROM (&amp;lt;code&amp;gt;61:1e:5b:66:2c:59:3a:08:ff:58:d1:4a:e2:24:52:d1:98:df:6c:60&amp;lt;/code&amp;gt;, Apple Root CA). In additional, string comparisons are performed against the root and leaf subject CNs.&lt;br /&gt;
&lt;br /&gt;
== Parsing Decrypted IMG1 Files ==&lt;br /&gt;
&lt;br /&gt;
With the development of the [[wInd3x]] exploit and its [https://github.com/freemyipod/wInd3x implementation] it has become possible to decrypt IMG1 files on the [[Nano_4G|iPod Nano 4g]] and [[Nano_5G|iPod Nano 5g]]. The [[Nano_4G|iPod Nano 4g]] has two separate sets of firmware available, firmware intended to interface with the [[Nano_4G|iPod Nano 4g]] hardware through DFU mode to assist with the restoration of the iPod to factory settings and the general retail firmware that is intended to be used by the consumer. Both sets of firmware can be obtained by following the links available [https://itunes.apple.com/WebObjects/MZStore.woa/wa/com.apple.jingle.appserver.client.MZITunesClientCheck/version?touchUpdate=true here]. In particular the `x12250000_Recovery.ipsw` file contains the WTF firmware (WTF.x1225.release.dfu) that interacts with DFU mode and the `iPod_31.1.0.4.ipsw` contains the bootloader (N58s.bootloader.release.rb3) and the rest of the [[RetailOS]].&lt;br /&gt;
&lt;br /&gt;
To assist with development for the Nano 4G hardware, it is important to understand the drivers that are included in these IMG1 files.&lt;br /&gt;
&lt;br /&gt;
These drivers are included as part of the (U)EFI image that is contained within the IMG1 file.&lt;br /&gt;
&lt;br /&gt;
For the nano4g, the first 0x700 bytes of the IMG1 contains a header that is discussed above. The rest of the file contains a what seems to be a UEFI firmware partition. Some of the information about UEFI firmware from the [https://en.wikipedia.org/wiki/UEFI Wikipedia page] seems relevant to understand this partition as well as the [https://wiki.osdev.org/UEFI OS Dev wiki page on UEFI development], which discusses UEFI applications and seems to be the format for some of the files included within the IMG1 volume.&lt;br /&gt;
&lt;br /&gt;
Using The uefi-firmware-parser package [https://github.com/theopolis/uefi-firmware-parser available here], it is possible to extract the files in this EFI volume. The files in the partition can be extracted by removing the first 0x700 bytes (Nano 4g) of the decrypted IMG1 file. This can be done with a hex editor or other tools. Furthermore, this step can be skipped if the option `-b` is used below. It is also recommended to setup a separate Conda environment to use with this tool. The files can be extracted as follows:&lt;br /&gt;
&lt;br /&gt;
  uefi-firmware-parser -o out/ -e decrypted_efi_firmware_filename_here&lt;br /&gt;
&lt;br /&gt;
The benefit of this approach is this will extracted all drivers included in the EFI firmware volume and also decompress each driver. The next step in the process is to identify the function of each driver. For this Apple was helpful enough to not strip out the name of each driver inside each driver file. The mapping from the file GUIDs to their functions can be recovered in many ways, but here is a simple script to print out the mapping:&lt;br /&gt;
&lt;br /&gt;
  for ii in `find out/ | grep &amp;quot;\.pe&amp;quot;`;&lt;br /&gt;
    do echo $ii | cut -d &#039;/&#039; -f 3 | cut -d &#039;-&#039; -f 2-; &lt;br /&gt;
    strings $ii | tail -n 1 | rev | cut -d &#039;/&#039; -f 1 | rev| cut -d &#039;.&#039; -f 1;&lt;br /&gt;
    echo; &lt;br /&gt;
  done&lt;br /&gt;
&lt;br /&gt;
There is an addition .te file that contains the executable code that is jumped to from Secure Boot.&lt;br /&gt;
&lt;br /&gt;
The extracted firmware PE files will contain a valid PE file header and will begin with the &amp;quot;MZ&amp;quot; magic bytes. It may be helpful to use [https://github.com/blackberry/pe_tree PE Tree] to parse these headers and inspect these files. Manual inspection with a hex editor can be done as well. Some information about PE file headers is available [https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#section-table-section-headers here].&lt;br /&gt;
&lt;br /&gt;
The above instructions assume a Nano 4g IMG1 WTF file or Bootloader. See [https://github.com/freemyipod/defs/blob/main/efi.py here] for more information about the Nano 5g IMG1 structure.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22115</id>
		<title>920-0614-03</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22115"/>
		<updated>2025-05-05T01:20:48Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* CHIPID */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;The 920-0614-03 is seemingly a development/prototype iPod Nano 4G (or possibly iPod Touch 2G board?). It appeared on a bunch of eBay auctions around September 2023.&lt;br /&gt;
&lt;br /&gt;
== Specs ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;SoC&#039;&#039;&#039;: S5L8720&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Flash&#039;&#039;&#039;: Usually desoldered&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;DRAM&#039;&#039;&#039;: To be checked&lt;br /&gt;
&lt;br /&gt;
== UART ==&lt;br /&gt;
&lt;br /&gt;
The boards has at least two ways to access UART:&lt;br /&gt;
&lt;br /&gt;
# Over DE9 connector.&lt;br /&gt;
&lt;br /&gt;
# Over USB/Serial bridge.&lt;br /&gt;
&lt;br /&gt;
# Over 30-pin connector.&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;TODO&#039;&#039;&#039;: Figure out which serial is which, and document reanimating DE9/USB.&lt;br /&gt;
&lt;br /&gt;
== Power ==&lt;br /&gt;
&lt;br /&gt;
The board runs from either the 30-pin connector by itself (although it can sometimes be unstable) or from 5V over a DC power jack (which provides a 4v-ish supply which simulates the devices&#039; battery).&lt;br /&gt;
&lt;br /&gt;
== JTAG ==&lt;br /&gt;
&lt;br /&gt;
[[JTAG]] is available over the 30 pin connector, but is also seemingly locked out as on production devices.&lt;br /&gt;
&lt;br /&gt;
== Getting code to run ==&lt;br /&gt;
&lt;br /&gt;
[[wInd3x]] works on the device. On devices without Flash attempting to run the standard WTF causes a reset.&lt;br /&gt;
&lt;br /&gt;
== Differences from production device ==&lt;br /&gt;
&lt;br /&gt;
=== CHIPID ===&lt;br /&gt;
&lt;br /&gt;
Different CHIPIDL/H values are present in the CHIPID peripheral:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! SoC !! CHIPIDL (&amp;lt;code&amp;gt;0x3d100_0004&amp;lt;/code&amp;gt;) !! CHIPIDH (&amp;lt;code&amp;gt;0x3d100_0008&amp;lt;/code&amp;gt;)&lt;br /&gt;
|-&lt;br /&gt;
| Nano 4G || &amp;lt;code&amp;gt;19000011&amp;lt;/code&amp;gt; || &amp;lt;code&amp;gt;8720000f&amp;lt;/code&amp;gt;&lt;br /&gt;
|-&lt;br /&gt;
| 920-0614-03 || &amp;lt;code&amp;gt;11000001&amp;lt;/code&amp;gt; || &amp;lt;code&amp;gt;8720180f&amp;lt;/code&amp;gt;&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
Effects:&lt;br /&gt;
&lt;br /&gt;
# &amp;lt;code&amp;gt;CHIPIDL &amp;amp; 0x10 == 0&amp;lt;/code&amp;gt;: The BootROM accepts an additional leaf certificate serial: 0x01 0xFB &#039;&#039;&#039;0x00&#039;&#039;&#039; 0xFB in addition to the standard 0x01 0xFB &#039;&#039;&#039;0x01&#039;&#039;&#039; 0xFB&lt;br /&gt;
# &amp;lt;code&amp;gt;CHIPIDL &amp;amp; (1 &amp;lt;&amp;lt; 27) == 0&amp;lt;/code&amp;gt;: The WTF&#039;s ChipID[2] function returns 2 instead of 3 in second argument.&lt;br /&gt;
&lt;br /&gt;
== Pins ==&lt;br /&gt;
&lt;br /&gt;
As the board has clearly labeled and accessible GPIO pins / configuration straps, it&#039;s a good candidate to reverse engineer pin functionality as used in the production device.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! S5L8720 GPIO !! Function on board&lt;br /&gt;
|-&lt;br /&gt;
| 91 || &#039;DFU&#039; button&lt;br /&gt;
|-&lt;br /&gt;
| 5 || DB9 UART TX (J9204)&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
== Case ==&lt;br /&gt;
&lt;br /&gt;
Protective case design: https://www.printables.com/model/628404-920-0614-03-ipod-nano-4g-prototype-case&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=IMG1&amp;diff=22114</id>
		<title>IMG1</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=IMG1&amp;diff=22114"/>
		<updated>2025-05-05T01:20:34Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* Verification Routine */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Introduction ==&lt;br /&gt;
&lt;br /&gt;
IMG1 is a pseudonym for the image format used by early iOS devices and all S5L-based iPods.&lt;br /&gt;
&lt;br /&gt;
It is sometimes called the &#039;8900&#039; image, which is how it was called on the original iPhone / S5L8900. It is also sometimes called the &#039;DFU image&#039; format (because it&#039;s used in DFU mode to load WTF).&lt;br /&gt;
&lt;br /&gt;
The iPhone Wiki has some basic [https://www.theiphonewiki.com/wiki/S5L_File_Formats#8900 information about the format]. However, that only describes the &#039;1.0&#039; version of IMG1. The lineage of IMG1 has continued in iPods long after iOS-based devices stopped its use, with IMG2/IMG3 never making it to the newer non-Touch iPods. Here we describe the known usage of IMG1, including its 2.0 version, in clickwheel iPods and non-iBoot bootroms.&lt;br /&gt;
&lt;br /&gt;
== Header Format ==&lt;br /&gt;
&lt;br /&gt;
  struct IMG1 {&lt;br /&gt;
    u8 magic[4];            // 0x0, SoC digits, eg. `8720`.&lt;br /&gt;
    u8 version[3];          // 0x4, `1.0` or `2.0`&lt;br /&gt;
    u8 format;              // 0x7, Encryption/signature format. See below.&lt;br /&gt;
    u32 entrypoint;         // 0x8, Offset to jump to within body (after header).&lt;br /&gt;
    u32 bodyLen;            // 0xC, Size of the image body, ie. the data loaded into memory, before the&lt;br /&gt;
                            // signature/certificates start, after the header.&lt;br /&gt;
    u32 dataLen;            // 0x10, Size of everything that&#039;s not the header (body + signature + certificates).&lt;br /&gt;
    u32 footerCertOffset;   // 0x14, Offset of certificate start (after header).&lt;br /&gt;
    u32 footerCertLen;      // 0x18, Size of certificate bundle.&lt;br /&gt;
    u8 salt[32];            // 0x1C, Random data.&lt;br /&gt;
    u16 unk1;               // 0x3C&lt;br /&gt;
    u16 unk2;               // 0x3E, Security epoch?&lt;br /&gt;
    u8 headerSign[16];      // 0x40, AES-encrypted SHA1 signature of everything up to headerSign.&lt;br /&gt;
    u8 headerLeftover[4];   // 0x50, Last four bytes of unencrypted SHA1, usually leftover in images, but not&lt;br /&gt;
                            // checked by firmware. Curiosity.&lt;br /&gt;
  }&lt;br /&gt;
&lt;br /&gt;
The body is padded to either 0x800 (S5L8900 (iOS)/S5L8702), 0x600 (S5L8720/S5L8930) or 0x400 (S5L8723/S5L8740) bytes. The different sections are a bit tricky to reason about, here&#039;s an attempted overview:&lt;br /&gt;
&lt;br /&gt;
  0:     Header (0x40 + 0x14 bytes, first 0x40 signed into last 0x14 bytes)&lt;br /&gt;
  0x54:  Padding until $header_size (magic dependent, 0x600 in this example) &lt;br /&gt;
  0x600: Body, bodyLen bytes.&lt;br /&gt;
  ...&lt;br /&gt;
  0x600 + bodyLen: body signature (for X509 formats)&lt;br /&gt;
  0x680 + bodyLen (also 0x600+footerCertLen): certificate bundle (for X509 formats)&lt;br /&gt;
  0x680 + bodyLen + footerCertLen: end of file.&lt;br /&gt;
&lt;br /&gt;
The body signature is always 0x80 bytes long, and its length is not counted into bodyLen or footerCertLen.&lt;br /&gt;
&lt;br /&gt;
A few assertions should hold for non-Touch iPods:&lt;br /&gt;
&lt;br /&gt;
# File size == $header_size + bodyLen + footerCertLen + 0x80&lt;br /&gt;
# dataLen = bodyLen + 0x80 + footerCertLen&lt;br /&gt;
&lt;br /&gt;
It is worth noting that for early iOS devices, dataLen is actually the offset to the body signature. It is unknown why Apple has changed this to the data length.&lt;br /&gt;
&lt;br /&gt;
=== Encryption/Signature Formats ===&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Format (number) !! Header signed (SHA1+AES) !! Body encrypted !! Body signed (X509/RSA) !! AES Operation !! Notes&lt;br /&gt;
|-&lt;br /&gt;
| SIGNED_ENCRYPTED (1) || ✅ || ✅ || ❌ || Encryption, Global/GID Key || Not accepted in 2.0.&lt;br /&gt;
|-&lt;br /&gt;
| SIGNED (2) || ✅ || ❌ || ❌ || Encryption, Global/GID Key || Not accepted in 2.0.&lt;br /&gt;
|-&lt;br /&gt;
| X509_SIGNED_ENCRYPTED (3) || ✅ || ✅ || ✅|| Decryption, Global/GID Key || Most (all?) released images have this type&lt;br /&gt;
|-&lt;br /&gt;
| X509_SIGNED (4) || ✅ || ❌ || ✅ || Decryption, Global/GID Key ||&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
DFU mode in N3G, N4G, N5G seems only accepts X509_SIGNED_ENCRYPTED.&lt;br /&gt;
&lt;br /&gt;
Other boot modes (notably in N3G) seem to accept other formats, but that&#039;s to be verified. N4G+/2.0 do not accept any non-X509 formats.&lt;br /&gt;
&lt;br /&gt;
=== Differences between v1.0 and 2.0 ===&lt;br /&gt;
&lt;br /&gt;
Nano4G+ use 2.0. Everything else uses 1.0.&lt;br /&gt;
&lt;br /&gt;
1.0 bootroms supports encryption formats 1, 2, 3 and 4. 2.0 only supports encryption formats 3 and 4.&lt;br /&gt;
&lt;br /&gt;
When uploading IMG1 images via DFU, 1.0 images need to be suffixed with a CRC32 of their content. 2.0 images don&#039;t need the CRC32.&lt;br /&gt;
&lt;br /&gt;
=== Differences between iBoot/SecureROM and iPod images ===&lt;br /&gt;
&lt;br /&gt;
The iPod images do not use &#039;Key 0x837&#039;, and in fact use the Global/GID key for all AES operations.&lt;br /&gt;
&lt;br /&gt;
The iPod images are sometimes decrypted using the encrypt direction of the AES engine (formats 1 and 2) and sometimes with the decrypt direction of the AES engine (formats 3 and 4). iBoot/SecureROM images seem to all use the decrypt direction.&lt;br /&gt;
&lt;br /&gt;
=== Leftover SHA in header ===&lt;br /&gt;
&lt;br /&gt;
It seems like whatever generates IMG1 images does so in the following pseudocode:&lt;br /&gt;
&lt;br /&gt;
  sha1(src=data, srcLen=0x40, dst=data+0x40)&lt;br /&gt;
  aes(src=data+0x40, size=0x10)&lt;br /&gt;
  // data is ready, ship it!&lt;br /&gt;
&lt;br /&gt;
As after the 0x10 bytes of the AES-encrypted SHA1 signature, there are 4 bytes of unencrypted SHA1 (because a SHA1 digest is 0x14 bytes, while an AES128 block is 0x10 bytes). This means that you can check the header signature yourself (or, well, 32 bits of the signature) by performing the following:&lt;br /&gt;
&lt;br /&gt;
  sha1(data[0:0x40]).digest()[-4:] == data[0x50:0x54]&lt;br /&gt;
&lt;br /&gt;
This has likely zero security implications, but is nonetheless a fascinating curiosity.&lt;br /&gt;
&lt;br /&gt;
=== Verification Routine ===&lt;br /&gt;
&lt;br /&gt;
There are 2 signatures that may be verified, those being the header signature and the body signature. &lt;br /&gt;
&lt;br /&gt;
The header signature in full may be verified by taking the SHA1 digest of data[0:0x40], encrypting it with the Global/GID key, and comparing it with the header signature.&lt;br /&gt;
&lt;br /&gt;
The body signature may be verified by first finding the leaf certificate, taking the public key from it, then verifying the body signature with the body data (defined as data[bodyPad:bodyPad + bodyLen]) and the public key.&lt;br /&gt;
&lt;br /&gt;
The body signature is then verified against the X.509 certificate chain provided after the signature. The leaf certificate in the chain must be emitted for the given signature and have a serial starting with &amp;lt;code&amp;gt;01:fb:01:fb&amp;lt;/code&amp;gt; (production devices, dev devices) or &amp;lt;code&amp;gt;01:fb:00:fb&amp;lt;/code&amp;gt; (dev devices). The root certificate in the chain must have a SHA singerprint that matches one hardcoded in the BootROM (&amp;lt;code&amp;gt;61:1e:5b:66:2c:59:3a:08:ff:58:d1:4a:e2:24:52:d1:98:df:6c:60&amp;lt;/code&amp;gt;, Apple Root CA). In additional, string comparisons are performed against the root and leaf subject CNs.&lt;br /&gt;
&lt;br /&gt;
=== Parsing Decrypted IMG1 Files ===&lt;br /&gt;
&lt;br /&gt;
With the development of the [[wInd3x]] exploit and its [https://github.com/freemyipod/wInd3x implementation] it has become possible to decrypt IMG1 files on the [[Nano_4G|iPod Nano 4g]] and [[Nano_5G|iPod Nano 5g]]. The [[Nano_4G|iPod Nano 4g]] has two separate sets of firmware available, firmware intended to interface with the [[Nano_4G|iPod Nano 4g]] hardware through DFU mode to assist with the restoration of the iPod to factory settings and the general retail firmware that is intended to be used by the consumer. Both sets of firmware can be obtained by following the links available [https://itunes.apple.com/WebObjects/MZStore.woa/wa/com.apple.jingle.appserver.client.MZITunesClientCheck/version?touchUpdate=true here]. In particular the `x12250000_Recovery.ipsw` file contains the WTF firmware (WTF.x1225.release.dfu) that interacts with DFU mode and the `iPod_31.1.0.4.ipsw` contains the bootloader (N58s.bootloader.release.rb3) and the rest of the [[RetailOS]].&lt;br /&gt;
&lt;br /&gt;
To assist with development for the Nano 4G hardware, it is important to understand the drivers that are included in these IMG1 files.&lt;br /&gt;
&lt;br /&gt;
These drivers are included as part of the (U)EFI image that is contained within the IMG1 file.&lt;br /&gt;
&lt;br /&gt;
For the nano4g, the first 0x700 bytes of the IMG1 contains a header that is discussed above. The rest of the file contains a what seems to be a UEFI firmware partition. Some of the information about UEFI firmware from the [https://en.wikipedia.org/wiki/UEFI Wikipedia page] seems relevant to understand this partition as well as the [https://wiki.osdev.org/UEFI OS Dev wiki page on UEFI development], which discusses UEFI applications and seems to be the format for some of the files included within the IMG1 volume.&lt;br /&gt;
&lt;br /&gt;
Using The uefi-firmware-parser package [https://github.com/theopolis/uefi-firmware-parser available here], it is possible to extract the files in this EFI volume. The files in the partition can be extracted by removing the first 0x700 bytes (Nano 4g) of the decrypted IMG1 file. This can be done with a hex editor or other tools. Furthermore, this step can be skipped if the option `-b` is used below. It is also recommended to setup a separate Conda environment to use with this tool. The files can be extracted as follows:&lt;br /&gt;
&lt;br /&gt;
  uefi-firmware-parser -o out/ -e decrypted_efi_firmware_filename_here&lt;br /&gt;
&lt;br /&gt;
The benefit of this approach is this will extracted all drivers included in the EFI firmware volume and also decompress each driver. The next step in the process is to identify the function of each driver. For this Apple was helpful enough to not strip out the name of each driver inside each driver file. The mapping from the file GUIDs to their functions can be recovered in many ways, but here is a simple script to print out the mapping:&lt;br /&gt;
&lt;br /&gt;
  for ii in `find out/ | grep &amp;quot;\.pe&amp;quot;`;&lt;br /&gt;
    do echo $ii | cut -d &#039;/&#039; -f 3 | cut -d &#039;-&#039; -f 2-; &lt;br /&gt;
    strings $ii | tail -n 1 | rev | cut -d &#039;/&#039; -f 1 | rev| cut -d &#039;.&#039; -f 1;&lt;br /&gt;
    echo; &lt;br /&gt;
  done&lt;br /&gt;
&lt;br /&gt;
There is an addition .te file that contains the executable code that is jumped to from Secure Boot.&lt;br /&gt;
&lt;br /&gt;
The extracted firmware PE files will contain a valid PE file header and will begin with the &amp;quot;MZ&amp;quot; magic bytes. It may be helpful to use [https://github.com/blackberry/pe_tree PE Tree] to parse these headers and inspect these files. Manual inspection with a hex editor can be done as well. Some information about PE file headers is available [https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#section-table-section-headers here].&lt;br /&gt;
&lt;br /&gt;
The above instructions assume a Nano 4g IMG1 WTF file or Bootloader. See [https://github.com/freemyipod/defs/blob/main/efi.py here] for more information about the Nano 5g IMG1 structure.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Nano_7G&amp;diff=22113</id>
		<title>Nano 7G</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Nano_7G&amp;diff=22113"/>
		<updated>2025-01-04T22:20:19Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* Memory Map */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Image:Nano7g_front.jpg|500px]]&lt;br /&gt;
[[Image:Nano7g_back.jpg|500px]]&lt;br /&gt;
==Components==&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Label !! Component !! Part !! Markings !! Notes&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff0004&amp;quot;&amp;gt;Red&amp;lt;/span&amp;gt;&lt;br /&gt;
| PMIC&lt;br /&gt;
| &lt;br /&gt;
| Apple 338S1099&lt;br /&gt;
| Guessing based on connectivity to power components around.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff9024&amp;quot;&amp;gt;Orange&amp;lt;/span&amp;gt;&lt;br /&gt;
| Bluetooth + FM radio&lt;br /&gt;
| Broadcom BCM2078KUBG&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#f3e00e&amp;quot;&amp;gt;Yellow&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
| NXP Semiconductors 1609A1&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#16dc81&amp;quot;&amp;gt;Green&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 75203 23017&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#2343e8&amp;quot;&amp;gt;Blue&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 75292 98820&lt;br /&gt;
|&lt;br /&gt;
|}&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Label !! Component !! Part !! Markings !! Notes&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff0000&amp;quot;&amp;gt;Red&amp;lt;/span&amp;gt;&lt;br /&gt;
| NAND flash&lt;br /&gt;
| Toshiba THGBX2G7D2JLA01 128 Gb (16 GB)&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff9024&amp;quot;&amp;gt;Orange&amp;lt;/span&amp;gt;&lt;br /&gt;
| Touchscreen controller&lt;br /&gt;
| Texas Instruments 343S0538&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#f3e00e&amp;quot;&amp;gt;Yellow&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
| Apple 338S1146&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#16dc81&amp;quot;&amp;gt;Green&amp;lt;/span&amp;gt;&lt;br /&gt;
| SoC/CPU&lt;br /&gt;
| S5L8740&lt;br /&gt;
| 339S0193&lt;br /&gt;
| 8740 per IMG1. Guessing based on similar package to N6G SoC/CPU. Also has the most diffpairs running to/from it (from delayered PCB).&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Teardowns:&lt;br /&gt;
* https://www.ifixit.com/Teardown/iPod+Nano+7th+Generation+Teardown/10826&lt;br /&gt;
&amp;lt;!--&lt;br /&gt;
Reviews:&lt;br /&gt;
* TODO&lt;br /&gt;
--&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Core ==&lt;br /&gt;
&lt;br /&gt;
Cortex A5 according to CP15:&lt;br /&gt;
&lt;br /&gt;
&amp;lt;pre&amp;gt;&lt;br /&gt;
ID code: 0x410fc050&lt;br /&gt;
  Implementer: ARM&lt;br /&gt;
  Variant: 0x0&lt;br /&gt;
  Architecture: See CPUID&lt;br /&gt;
  Part number: c05, Revision: 0&lt;br /&gt;
&amp;lt;/pre&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Memory Map ==&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Address !! Name&lt;br /&gt;
|-&lt;br /&gt;
| 0x38C00000&lt;br /&gt;
| AES&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C500000&lt;br /&gt;
| CLKCON&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C700000&lt;br /&gt;
| TIMER&lt;br /&gt;
|-&lt;br /&gt;
| 0x3CC00000&lt;br /&gt;
| UART0&lt;br /&gt;
|-&lt;br /&gt;
| 0x3CF00000&lt;br /&gt;
| GPIO&lt;br /&gt;
|-&lt;br /&gt;
| 0x3D100000&lt;br /&gt;
| CHIPID&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
== Clock Gates ==&lt;br /&gt;
&lt;br /&gt;
There is no big debug table with all clock gates in N7G RetailOS, so the following has been written out by hand:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Address !! Bits (clear to power on) !! Meaning !! Source&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C50006C&lt;br /&gt;
| 0x2000&lt;br /&gt;
| &#039;SPI power&#039;&lt;br /&gt;
| WTF DevicePowerManagement.dll&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C50004C&lt;br /&gt;
| 0x4&lt;br /&gt;
| &#039;SPI power&#039;&lt;br /&gt;
| WTF DevicePowerManagement.dll&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C50004c&lt;br /&gt;
| 0x1f800020&lt;br /&gt;
| Timer&lt;br /&gt;
| WTF IpodSec.dll&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C500058&lt;br /&gt;
| 0x60&lt;br /&gt;
| Timer&lt;br /&gt;
| WTF IpodSec.dll&lt;br /&gt;
|-&lt;br /&gt;
| 0x3c50006c&lt;br /&gt;
| 0xc0007f&lt;br /&gt;
| Timer&lt;br /&gt;
| WTF IpodSec.dll&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Nano_7G&amp;diff=22112</id>
		<title>Nano 7G</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Nano_7G&amp;diff=22112"/>
		<updated>2025-01-04T22:16:57Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* Clock Gates */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Image:Nano7g_front.jpg|500px]]&lt;br /&gt;
[[Image:Nano7g_back.jpg|500px]]&lt;br /&gt;
==Components==&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Label !! Component !! Part !! Markings !! Notes&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff0004&amp;quot;&amp;gt;Red&amp;lt;/span&amp;gt;&lt;br /&gt;
| PMIC&lt;br /&gt;
| &lt;br /&gt;
| Apple 338S1099&lt;br /&gt;
| Guessing based on connectivity to power components around.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff9024&amp;quot;&amp;gt;Orange&amp;lt;/span&amp;gt;&lt;br /&gt;
| Bluetooth + FM radio&lt;br /&gt;
| Broadcom BCM2078KUBG&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#f3e00e&amp;quot;&amp;gt;Yellow&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
| NXP Semiconductors 1609A1&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#16dc81&amp;quot;&amp;gt;Green&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 75203 23017&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#2343e8&amp;quot;&amp;gt;Blue&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 75292 98820&lt;br /&gt;
|&lt;br /&gt;
|}&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Label !! Component !! Part !! Markings !! Notes&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff0000&amp;quot;&amp;gt;Red&amp;lt;/span&amp;gt;&lt;br /&gt;
| NAND flash&lt;br /&gt;
| Toshiba THGBX2G7D2JLA01 128 Gb (16 GB)&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff9024&amp;quot;&amp;gt;Orange&amp;lt;/span&amp;gt;&lt;br /&gt;
| Touchscreen controller&lt;br /&gt;
| Texas Instruments 343S0538&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#f3e00e&amp;quot;&amp;gt;Yellow&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
| Apple 338S1146&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#16dc81&amp;quot;&amp;gt;Green&amp;lt;/span&amp;gt;&lt;br /&gt;
| SoC/CPU&lt;br /&gt;
| S5L8740&lt;br /&gt;
| 339S0193&lt;br /&gt;
| 8740 per IMG1. Guessing based on similar package to N6G SoC/CPU. Also has the most diffpairs running to/from it (from delayered PCB).&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Teardowns:&lt;br /&gt;
* https://www.ifixit.com/Teardown/iPod+Nano+7th+Generation+Teardown/10826&lt;br /&gt;
&amp;lt;!--&lt;br /&gt;
Reviews:&lt;br /&gt;
* TODO&lt;br /&gt;
--&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Core ==&lt;br /&gt;
&lt;br /&gt;
Cortex A5 according to CP15:&lt;br /&gt;
&lt;br /&gt;
&amp;lt;pre&amp;gt;&lt;br /&gt;
ID code: 0x410fc050&lt;br /&gt;
  Implementer: ARM&lt;br /&gt;
  Variant: 0x0&lt;br /&gt;
  Architecture: See CPUID&lt;br /&gt;
  Part number: c05, Revision: 0&lt;br /&gt;
&amp;lt;/pre&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Memory Map ==&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Address !! Name&lt;br /&gt;
|-&lt;br /&gt;
| 0x38C00000&lt;br /&gt;
| AES&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C500000&lt;br /&gt;
| CLKCON&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C700000&lt;br /&gt;
| TIMER&lt;br /&gt;
|-&lt;br /&gt;
| 0x3CC00000&lt;br /&gt;
| UART0&lt;br /&gt;
|-&lt;br /&gt;
| 0x3D100000&lt;br /&gt;
| CHIPID&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
== Clock Gates ==&lt;br /&gt;
&lt;br /&gt;
There is no big debug table with all clock gates in N7G RetailOS, so the following has been written out by hand:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Address !! Bits (clear to power on) !! Meaning !! Source&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C50006C&lt;br /&gt;
| 0x2000&lt;br /&gt;
| &#039;SPI power&#039;&lt;br /&gt;
| WTF DevicePowerManagement.dll&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C50004C&lt;br /&gt;
| 0x4&lt;br /&gt;
| &#039;SPI power&#039;&lt;br /&gt;
| WTF DevicePowerManagement.dll&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C50004c&lt;br /&gt;
| 0x1f800020&lt;br /&gt;
| Timer&lt;br /&gt;
| WTF IpodSec.dll&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C500058&lt;br /&gt;
| 0x60&lt;br /&gt;
| Timer&lt;br /&gt;
| WTF IpodSec.dll&lt;br /&gt;
|-&lt;br /&gt;
| 0x3c50006c&lt;br /&gt;
| 0xc0007f&lt;br /&gt;
| Timer&lt;br /&gt;
| WTF IpodSec.dll&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Nano_7G&amp;diff=22111</id>
		<title>Nano 7G</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Nano_7G&amp;diff=22111"/>
		<updated>2025-01-04T22:14:36Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* Memory Map */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Image:Nano7g_front.jpg|500px]]&lt;br /&gt;
[[Image:Nano7g_back.jpg|500px]]&lt;br /&gt;
==Components==&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Label !! Component !! Part !! Markings !! Notes&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff0004&amp;quot;&amp;gt;Red&amp;lt;/span&amp;gt;&lt;br /&gt;
| PMIC&lt;br /&gt;
| &lt;br /&gt;
| Apple 338S1099&lt;br /&gt;
| Guessing based on connectivity to power components around.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff9024&amp;quot;&amp;gt;Orange&amp;lt;/span&amp;gt;&lt;br /&gt;
| Bluetooth + FM radio&lt;br /&gt;
| Broadcom BCM2078KUBG&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#f3e00e&amp;quot;&amp;gt;Yellow&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
| NXP Semiconductors 1609A1&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#16dc81&amp;quot;&amp;gt;Green&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 75203 23017&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#2343e8&amp;quot;&amp;gt;Blue&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 75292 98820&lt;br /&gt;
|&lt;br /&gt;
|}&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Label !! Component !! Part !! Markings !! Notes&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff0000&amp;quot;&amp;gt;Red&amp;lt;/span&amp;gt;&lt;br /&gt;
| NAND flash&lt;br /&gt;
| Toshiba THGBX2G7D2JLA01 128 Gb (16 GB)&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff9024&amp;quot;&amp;gt;Orange&amp;lt;/span&amp;gt;&lt;br /&gt;
| Touchscreen controller&lt;br /&gt;
| Texas Instruments 343S0538&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#f3e00e&amp;quot;&amp;gt;Yellow&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
| Apple 338S1146&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#16dc81&amp;quot;&amp;gt;Green&amp;lt;/span&amp;gt;&lt;br /&gt;
| SoC/CPU&lt;br /&gt;
| S5L8740&lt;br /&gt;
| 339S0193&lt;br /&gt;
| 8740 per IMG1. Guessing based on similar package to N6G SoC/CPU. Also has the most diffpairs running to/from it (from delayered PCB).&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Teardowns:&lt;br /&gt;
* https://www.ifixit.com/Teardown/iPod+Nano+7th+Generation+Teardown/10826&lt;br /&gt;
&amp;lt;!--&lt;br /&gt;
Reviews:&lt;br /&gt;
* TODO&lt;br /&gt;
--&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Core ==&lt;br /&gt;
&lt;br /&gt;
Cortex A5 according to CP15:&lt;br /&gt;
&lt;br /&gt;
&amp;lt;pre&amp;gt;&lt;br /&gt;
ID code: 0x410fc050&lt;br /&gt;
  Implementer: ARM&lt;br /&gt;
  Variant: 0x0&lt;br /&gt;
  Architecture: See CPUID&lt;br /&gt;
  Part number: c05, Revision: 0&lt;br /&gt;
&amp;lt;/pre&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Memory Map ==&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Address !! Name&lt;br /&gt;
|-&lt;br /&gt;
| 0x38C00000&lt;br /&gt;
| AES&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C500000&lt;br /&gt;
| CLKCON&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C700000&lt;br /&gt;
| TIMER&lt;br /&gt;
|-&lt;br /&gt;
| 0x3CC00000&lt;br /&gt;
| UART0&lt;br /&gt;
|-&lt;br /&gt;
| 0x3D100000&lt;br /&gt;
| CHIPID&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
== Clock Gates ==&lt;br /&gt;
&lt;br /&gt;
There is no big debug table with all clock gates in N7G RetailOS, so the following has been written out by hand:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Address !! Bits (clear to power on) !! Meaning !! Source&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C50006C&lt;br /&gt;
| 0x2000&lt;br /&gt;
| &#039;SPI power&#039;&lt;br /&gt;
| WTF DevicePowerManagement.dll&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C50004C&lt;br /&gt;
| 0x4&lt;br /&gt;
| &#039;SPI power&#039;&lt;br /&gt;
| WTF DevicePowerManagement.dll&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Nano_7G&amp;diff=22110</id>
		<title>Nano 7G</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Nano_7G&amp;diff=22110"/>
		<updated>2025-01-04T21:46:22Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Image:Nano7g_front.jpg|500px]]&lt;br /&gt;
[[Image:Nano7g_back.jpg|500px]]&lt;br /&gt;
==Components==&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Label !! Component !! Part !! Markings !! Notes&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff0004&amp;quot;&amp;gt;Red&amp;lt;/span&amp;gt;&lt;br /&gt;
| PMIC&lt;br /&gt;
| &lt;br /&gt;
| Apple 338S1099&lt;br /&gt;
| Guessing based on connectivity to power components around.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff9024&amp;quot;&amp;gt;Orange&amp;lt;/span&amp;gt;&lt;br /&gt;
| Bluetooth + FM radio&lt;br /&gt;
| Broadcom BCM2078KUBG&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#f3e00e&amp;quot;&amp;gt;Yellow&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
| NXP Semiconductors 1609A1&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#16dc81&amp;quot;&amp;gt;Green&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 75203 23017&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#2343e8&amp;quot;&amp;gt;Blue&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 75292 98820&lt;br /&gt;
|&lt;br /&gt;
|}&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Label !! Component !! Part !! Markings !! Notes&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff0000&amp;quot;&amp;gt;Red&amp;lt;/span&amp;gt;&lt;br /&gt;
| NAND flash&lt;br /&gt;
| Toshiba THGBX2G7D2JLA01 128 Gb (16 GB)&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff9024&amp;quot;&amp;gt;Orange&amp;lt;/span&amp;gt;&lt;br /&gt;
| Touchscreen controller&lt;br /&gt;
| Texas Instruments 343S0538&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#f3e00e&amp;quot;&amp;gt;Yellow&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
| Apple 338S1146&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#16dc81&amp;quot;&amp;gt;Green&amp;lt;/span&amp;gt;&lt;br /&gt;
| SoC/CPU&lt;br /&gt;
| S5L8740&lt;br /&gt;
| 339S0193&lt;br /&gt;
| 8740 per IMG1. Guessing based on similar package to N6G SoC/CPU. Also has the most diffpairs running to/from it (from delayered PCB).&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Teardowns:&lt;br /&gt;
* https://www.ifixit.com/Teardown/iPod+Nano+7th+Generation+Teardown/10826&lt;br /&gt;
&amp;lt;!--&lt;br /&gt;
Reviews:&lt;br /&gt;
* TODO&lt;br /&gt;
--&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Core ==&lt;br /&gt;
&lt;br /&gt;
Cortex A5 according to CP15:&lt;br /&gt;
&lt;br /&gt;
&amp;lt;pre&amp;gt;&lt;br /&gt;
ID code: 0x410fc050&lt;br /&gt;
  Implementer: ARM&lt;br /&gt;
  Variant: 0x0&lt;br /&gt;
  Architecture: See CPUID&lt;br /&gt;
  Part number: c05, Revision: 0&lt;br /&gt;
&amp;lt;/pre&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Memory Map ==&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Address !! Name&lt;br /&gt;
|-&lt;br /&gt;
| 0x38C00000&lt;br /&gt;
| AES&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C500000&lt;br /&gt;
| CLKCON&lt;br /&gt;
|-&lt;br /&gt;
| 0x3CC00000&lt;br /&gt;
| UART0&lt;br /&gt;
|-&lt;br /&gt;
| 0x3D100000&lt;br /&gt;
| CHIPID&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
== Clock Gates ==&lt;br /&gt;
&lt;br /&gt;
There is no big debug table with all clock gates in N7G RetailOS, so the following has been written out by hand:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Address !! Bits (clear to power on) !! Meaning !! Source&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C50006C&lt;br /&gt;
| 0x2000&lt;br /&gt;
| &#039;SPI power&#039;&lt;br /&gt;
| WTF DevicePowerManagement.dll&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C50004C&lt;br /&gt;
| 0x4&lt;br /&gt;
| &#039;SPI power&#039;&lt;br /&gt;
| WTF DevicePowerManagement.dll&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Nano_7G&amp;diff=22109</id>
		<title>Nano 7G</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Nano_7G&amp;diff=22109"/>
		<updated>2025-01-04T21:44:25Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Image:Nano7g_front.jpg|500px]]&lt;br /&gt;
[[Image:Nano7g_back.jpg|500px]]&lt;br /&gt;
==Components==&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Label !! Component !! Part !! Markings !! Notes&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff0004&amp;quot;&amp;gt;Red&amp;lt;/span&amp;gt;&lt;br /&gt;
| PMIC&lt;br /&gt;
| &lt;br /&gt;
| Apple 338S1099&lt;br /&gt;
| Guessing based on connectivity to power components around.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff9024&amp;quot;&amp;gt;Orange&amp;lt;/span&amp;gt;&lt;br /&gt;
| Bluetooth + FM radio&lt;br /&gt;
| Broadcom BCM2078KUBG&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#f3e00e&amp;quot;&amp;gt;Yellow&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
| NXP Semiconductors 1609A1&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#16dc81&amp;quot;&amp;gt;Green&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 75203 23017&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#2343e8&amp;quot;&amp;gt;Blue&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
| 75292 98820&lt;br /&gt;
|&lt;br /&gt;
|}&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Label !! Component !! Part !! Markings !! Notes&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff0000&amp;quot;&amp;gt;Red&amp;lt;/span&amp;gt;&lt;br /&gt;
| NAND flash&lt;br /&gt;
| Toshiba THGBX2G7D2JLA01 128 Gb (16 GB)&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#ff9024&amp;quot;&amp;gt;Orange&amp;lt;/span&amp;gt;&lt;br /&gt;
| Touchscreen controller&lt;br /&gt;
| Texas Instruments 343S0538&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#f3e00e&amp;quot;&amp;gt;Yellow&amp;lt;/span&amp;gt;&lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
| Apple 338S1146&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;span style=&amp;quot;color:#16dc81&amp;quot;&amp;gt;Green&amp;lt;/span&amp;gt;&lt;br /&gt;
| SoC/CPU&lt;br /&gt;
| S5L8740&lt;br /&gt;
| 339S0193&lt;br /&gt;
| 8740 per IMG1. Guessing based on similar package to N6G SoC/CPU. Also has the most diffpairs running to/from it (from delayered PCB).&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Teardowns:&lt;br /&gt;
* https://www.ifixit.com/Teardown/iPod+Nano+7th+Generation+Teardown/10826&lt;br /&gt;
&amp;lt;!--&lt;br /&gt;
Reviews:&lt;br /&gt;
* TODO&lt;br /&gt;
--&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Core ==&lt;br /&gt;
&lt;br /&gt;
Cortex A5 according to CP15:&lt;br /&gt;
&lt;br /&gt;
&amp;lt;pre&amp;gt;&lt;br /&gt;
ID code: 0x410fc050&lt;br /&gt;
  Implementer: ARM&lt;br /&gt;
  Variant: 0x0&lt;br /&gt;
  Architecture: See CPUID&lt;br /&gt;
  Part number: c05, Revision: 0&lt;br /&gt;
&amp;lt;/pre&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Clock Gates ==&lt;br /&gt;
&lt;br /&gt;
There is no big debug table with all clock gates in N7G RetailOS, so the following has been written out by hand:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Address !! Bits (clear to power on) !! Meaning !! Source&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C50006C&lt;br /&gt;
| 0x2000&lt;br /&gt;
| &#039;SPI power&#039;&lt;br /&gt;
| WTF DevicePowerManagement.dll&lt;br /&gt;
|-&lt;br /&gt;
| 0x3C50004C&lt;br /&gt;
| 0x4&lt;br /&gt;
| &#039;SPI power&#039;&lt;br /&gt;
| WTF DevicePowerManagement.dll&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Main_Page&amp;diff=22108</id>
		<title>Main Page</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Main_Page&amp;diff=22108"/>
		<updated>2024-12-25T22:35:43Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* Updates */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;__NOTOC__&lt;br /&gt;
[[File:EmCORE_Nano2G_Nano4G_Classic.jpg|280px|thumb|right|[[emCORE]] r779 on [[Nano 2G]], [[Nano 4G]] and [[Classic 2G]]]]&lt;br /&gt;
This is the wiki for the freemyipod project. Freemyipod is a project aimed at reverse-engineering non-iOS iPods (all models other than the Touch) and creating tools and documentation so that other people can port alternative firmwares to them such as [http://www.rockbox.org rockbox] or Linux. Freemyipod is a relaunch of [[Linux4nano]].&lt;br /&gt;
&lt;br /&gt;
== FAQ ==&lt;br /&gt;
&lt;br /&gt;
=== What can I do with my iPod nano (2nd generation), iPod classic or older iPods? ===&lt;br /&gt;
&lt;br /&gt;
There&#039;s an upstream Rockbox port for these devices. Go use that.&lt;br /&gt;
&lt;br /&gt;
=== What can I do with my iPod nano (3rd generation) or newer? ===&lt;br /&gt;
&lt;br /&gt;
Not much (yet) unless you&#039;re an embedded developer :).&lt;br /&gt;
&lt;br /&gt;
On the 3rd, 4th and 5th generation, we have a stable tethered exploit ([[wInd3x]]) which allows early, untethered and safe (no permanent modification) code execution. This in turn allows you to run [[U-Boot]] and an early [[Linux|Linux port]] or experiment with reverse-engineering/modifying the original firmware, [[retailOS]].&lt;br /&gt;
&lt;br /&gt;
On the 6th and 7th generation, a font parsing vulnerability (CVE-2010-1797) can be exploited with [[ipod_sun]].&lt;br /&gt;
&lt;br /&gt;
On the 7th generation (and possibly 6th generation), a vulnerability in DFU_DNLOAD packet parsing code can be exploited with [[S5Late]].&lt;br /&gt;
&lt;br /&gt;
There&#039;s a set of earlier tooling ([[emCORE]]/[[emBIOS]]/[[iBugger]]) which was exploiting other vulnerabilities and was a lead-up to a port of Rockbox, but it&#039;s mostly abandoned.&lt;br /&gt;
&lt;br /&gt;
== Getting an account ==&lt;br /&gt;
Due to spambots, registration is closed. For an account contact [[User:User890104|User890104]] or [[User:Q3k|q3k]].&lt;br /&gt;
&lt;br /&gt;
==Updates==&lt;br /&gt;
* {{#dateformat:2024-12-25}} - Some of us will be at 38C3 in Hamburg! [https://events.ccc.de/congress/2024/hub/en/project/ipod-nano-hacking-freemyipod/ Come say hi!]&lt;br /&gt;
* {{#dateformat:2024-12-16}} - [[S5Late]], a tethered iPod bootrom/DFU exploit for Nano 7G (and possibly Nano 6G), is released.&lt;br /&gt;
* {{#dateformat:2023-12-28}} - [[ipod_sun]], a tool that enables code execution on the iPod nano 6th and 7th generation, is released.&lt;br /&gt;
* {{#dateformat:2023-01-07}} - [https://social.hackerspace.pl/@q3k/109655916469636189 A preliminary U-Boot port to the Nano 5G has been developed.]&lt;br /&gt;
* {{#dateformat:2022-01-04}} - The bootrom of iPod Nano 5G was successfully dumped, and is in the process of being reverse-engineered!&lt;br /&gt;
* {{#dateformat:2021-12-31}} - An exploit named wInd3x, which exploits the latest vulnerability, is being prepared for Nano 4G and Nano 5G.&lt;br /&gt;
* {{#dateformat:2021-12-27}} - A new vulnerability was discovered in iPod Nano 4G and Nano 5G bootrom, which allows arbitrary code execution!&lt;br /&gt;
* {{#dateformat:2018-08-25}} - The website software has been updated to MediaWiki 1.31 after about 2 months of downtime.&lt;br /&gt;
&amp;lt;!--&lt;br /&gt;
* {{#dateformat:2016-06-17}} - The freemyipod project is becoming deprecated, as parts of the code is slowly being integrated in Rockbox. It is likely that no future development on the freemyipod project will take place. Essential parts of emCORE helped building a Rockbox bootloader for iPod Classic, and any future development will take place in the Rockbox project.&lt;br /&gt;
* {{#dateformat:2014-03-26}} - A bug that prevented [[emCORE]] installations on certain Windows configurations (getting stuck on &amp;quot;Booting UBI file...&amp;quot;), has been finally fixed! If the installation has failed for you before, you can retry it using the updated version of our tool (use the iTunes method for now).&lt;br /&gt;
* {{#dateformat:2012-01-02}} - There have been some problems with the latest release. A hotfix release ([[EmCORE_Releases/r859|r859]]) has been published to fix some of these problems. iPod nano 2g users are advised to upgrade.  See the [[EmCORE_Releases/r859|release details page]] for more information.&lt;br /&gt;
* {{#dateformat:2012-01-01}} - A new release &amp;lt;s&amp;gt;([[EmCORE_Releases/r855|r855]])&amp;lt;/s&amp;gt; is out! It includes a couple of new features, several bugfixes and a new bootmenu theme! More information on the &amp;lt;s&amp;gt;[[EmCORE_Releases/r855|release details page]]&amp;lt;/s&amp;gt;.&lt;br /&gt;
* {{#dateformat:2011-04-25}} - The [[emCORE]] kernel now runs on the iPod Touch 2G as well, thanks to the help of kleemajo. This is of course not a fully functional port yet, but we&#039;ll see how it continues. It&#039;s about the same state as the iPod Nano 4G now. /7&lt;br /&gt;
* {{#dateformat:2011-03-25}} - [[emCORE]] is replacing [[emBIOS]] completely now. Therefore [[emBIOS]] will be deprecated software as of now! All emBIOS users are advised to upgrade to emCORE including people using iLoader 0.2.2 or less. More detailed update instructions will follow!&lt;br /&gt;
* {{#dateformat:2011-01-08}} - The Rockbox port for the iPod Classic is slowly getting usable. Most of the blocking issues have been fixed. The  first-generation 160GB model still doesn&#039;t work, and some people are experiencing slightly garbled display contents.&lt;br /&gt;
* {{#dateformat:2011-01-04}} - There is an early Rockbox port for the iPod Classic! It still isn&#039;t quite usable, playback stutters etc., but if you want to play around with it, here are some quick&#039;n&#039;dirty notes on the installation procedure: [[IPod Classic iLoader Installation]]&lt;br /&gt;
* {{#dateformat:2010-11-22}} - We now have emBIOS support for the iPod classic 1g, the others might follow soon&lt;br /&gt;
* {{#dateformat:2010-08-29}} - We&#039;re proud to announce the release of [[emBIOS]] v0.1.0 and [[iLoader]] v0.2.0!&lt;br /&gt;
* {{#dateformat:2010-08-26}} - [[iLoader]], its installer and uninstaller all have been fully ported to [[emBIOS]] now. A beta release will be coming soon!&lt;br /&gt;
* {{#dateformat:2010-08-13}} - [[emBIOS]] is continually being improved and the next step is porting tools like [[iLoader]] to use it.&lt;br /&gt;
* {{#dateformat:2010-08-06}} - The wiki has now been moved to www.freemyipod.org&lt;br /&gt;
* {{#dateformat:2010-08-05}} - Recently we&#039;ve been working on a hardware abstraction project called [[emBIOS]]. Follow development [http://websvn.freemyipod.org/listing.php?repname=freemyipod&amp;amp;path=/embios/ here]&lt;br /&gt;
* {{#dateformat:2010-08-03}} - We can now access the Nano 4G accelerometer.&lt;br /&gt;
* {{#dateformat:2010-08-02}} - serpilliere managed to decrypt the NOR flash on the [[Nano 3G]].&lt;br /&gt;
* {{#dateformat:2010-08-01}} - serpilliere managed to access and dump the NOR flash on the [[Nano 3G]]. This code could possibly work on the Classics.&lt;br /&gt;
* {{#dateformat:2010-07-27}} - The server got zapped by lightning but a new one was up and running within a day.&lt;br /&gt;
* {{#dateformat:2010-02-23}} - We can now execute code on everything besides the [[Nano 5G]]! Minimalistic iBugger working on [[Nano 3G]]!&lt;br /&gt;
* {{#dateformat:2009-11-01}} - iBugger core v0.1 successfully running on [[Nano 4G]]! [http://img217.imageshack.us/img217/4122/img0969.jpg]&lt;br /&gt;
--&amp;gt;&lt;br /&gt;
Follow [http://twitter.com/freemyipod our Twitter feed] to get status updates automatically. See the [[Status]] page for more detailed information. Check our [[ Special:Code/freemyipod|SVN activity ]] page for the latest changes to our source code.&lt;br /&gt;
&lt;br /&gt;
{| cellspacing=&amp;quot;3&amp;quot; width=&amp;quot;100%&amp;quot;&lt;br /&gt;
|- valign=&amp;quot;top&amp;quot;&lt;br /&gt;
|style=&amp;quot;border: 1px dashed #c6c9ff; background-color: #f0f0ff&amp;quot;|&lt;br /&gt;
===Project info===&lt;br /&gt;
* [[ Status ]]&lt;br /&gt;
* [[ Contact ]]&lt;br /&gt;
* [[ Contributing ]]&lt;br /&gt;
&lt;br /&gt;
===Released Software===&lt;br /&gt;
* [[wInd3x]]&lt;br /&gt;
* [[ipod_sun]]&lt;br /&gt;
* [[U-Boot|U-Boot port]]&lt;br /&gt;
* [[Linux|Linux port]]&lt;br /&gt;
* Legacy:&lt;br /&gt;
** [[iBugger]]&lt;br /&gt;
** [[iLoader]]&lt;br /&gt;
** [[emCORE]]&lt;br /&gt;
&lt;br /&gt;
|style=&amp;quot;border: 1px dashed #c6c9ff; background-color: #f0f0ff&amp;quot;|&lt;br /&gt;
&lt;br /&gt;
===Basic skills===&lt;br /&gt;
* [[Working with binaries]]&lt;br /&gt;
* [[Dumping firmware]]&lt;br /&gt;
* [[Extracting firmware]]&lt;br /&gt;
* [[Firmware downgrading]]&lt;br /&gt;
* [[Troubleshooting]]&lt;br /&gt;
&lt;br /&gt;
===Reverse engineering results===&lt;br /&gt;
* [[Firmware]]&lt;br /&gt;
** [[Bootrom]]&lt;br /&gt;
** [[Boot Process]]&lt;br /&gt;
** [[Firmware decryption]]&lt;br /&gt;
** [[FTL|Flash Translation Layer]]&lt;br /&gt;
** [[RetailOS]]&lt;br /&gt;
*** [[RetailOS Options]]&lt;br /&gt;
* [[GUID table]]&lt;br /&gt;
* [[JTAG]]&lt;br /&gt;
* Nano 2G&lt;br /&gt;
** [[Nano2G clock gates‎]]&lt;br /&gt;
** [[Nano2G LCD init]]&lt;br /&gt;
** [[Nano2G HW analysis]]&lt;br /&gt;
** [[S5L8701 analysis]]&lt;br /&gt;
* Nano 4G&lt;br /&gt;
** [[Nano4G firmware upgrade process]]&lt;br /&gt;
* Nano 5G&lt;br /&gt;
** [[Nano 5G|General]]&lt;br /&gt;
&lt;br /&gt;
===Other guides===&lt;br /&gt;
* [[Modes]]&lt;br /&gt;
|style=&amp;quot;border: 1px dashed #c6c9ff; background-color: #f0f0ff&amp;quot;|&lt;br /&gt;
===Hardware===&lt;br /&gt;
* [[Hardware]]&lt;br /&gt;
** [[Nano 1G]]&lt;br /&gt;
** [[Nano 2G]]&lt;br /&gt;
** [[Nano 3G]]&lt;br /&gt;
** [[Nano 4G]]&lt;br /&gt;
*** [[920-0614-03]]&lt;br /&gt;
** [[Nano 5G]]&lt;br /&gt;
** [[Nano 6G]]&lt;br /&gt;
** [[Nano 7G]]&lt;br /&gt;
** [[Classic 1G]]&lt;br /&gt;
** [[Classic 2G]]&lt;br /&gt;
** [[Classic 3G]]&lt;br /&gt;
* [[Chronology]]&lt;br /&gt;
* [[S5L8700 datasheet]]&lt;br /&gt;
&lt;br /&gt;
===Exploiting===&lt;br /&gt;
* [[wInd3x]]&lt;br /&gt;
* [[Pwnage 2.0]]&lt;br /&gt;
* [[Notes vulnerability]]&lt;br /&gt;
** [[Address bruteforcing]]&lt;br /&gt;
** [[Nanotron 3000]]&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Main_Page&amp;diff=22107</id>
		<title>Main Page</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Main_Page&amp;diff=22107"/>
		<updated>2024-12-25T22:35:03Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* Updates */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;__NOTOC__&lt;br /&gt;
[[File:EmCORE_Nano2G_Nano4G_Classic.jpg|280px|thumb|right|[[emCORE]] r779 on [[Nano 2G]], [[Nano 4G]] and [[Classic 2G]]]]&lt;br /&gt;
This is the wiki for the freemyipod project. Freemyipod is a project aimed at reverse-engineering non-iOS iPods (all models other than the Touch) and creating tools and documentation so that other people can port alternative firmwares to them such as [http://www.rockbox.org rockbox] or Linux. Freemyipod is a relaunch of [[Linux4nano]].&lt;br /&gt;
&lt;br /&gt;
== FAQ ==&lt;br /&gt;
&lt;br /&gt;
=== What can I do with my iPod nano (2nd generation), iPod classic or older iPods? ===&lt;br /&gt;
&lt;br /&gt;
There&#039;s an upstream Rockbox port for these devices. Go use that.&lt;br /&gt;
&lt;br /&gt;
=== What can I do with my iPod nano (3rd generation) or newer? ===&lt;br /&gt;
&lt;br /&gt;
Not much (yet) unless you&#039;re an embedded developer :).&lt;br /&gt;
&lt;br /&gt;
On the 3rd, 4th and 5th generation, we have a stable tethered exploit ([[wInd3x]]) which allows early, untethered and safe (no permanent modification) code execution. This in turn allows you to run [[U-Boot]] and an early [[Linux|Linux port]] or experiment with reverse-engineering/modifying the original firmware, [[retailOS]].&lt;br /&gt;
&lt;br /&gt;
On the 6th and 7th generation, a font parsing vulnerability (CVE-2010-1797) can be exploited with [[ipod_sun]].&lt;br /&gt;
&lt;br /&gt;
On the 7th generation (and possibly 6th generation), a vulnerability in DFU_DNLOAD packet parsing code can be exploited with [[S5Late]].&lt;br /&gt;
&lt;br /&gt;
There&#039;s a set of earlier tooling ([[emCORE]]/[[emBIOS]]/[[iBugger]]) which was exploiting other vulnerabilities and was a lead-up to a port of Rockbox, but it&#039;s mostly abandoned.&lt;br /&gt;
&lt;br /&gt;
== Getting an account ==&lt;br /&gt;
Due to spambots, registration is closed. For an account contact [[User:User890104|User890104]] or [[User:Q3k|q3k]].&lt;br /&gt;
&lt;br /&gt;
==Updates==&lt;br /&gt;
* {{#dateformat:2024-12-25}} - Some of us will be at 38C3 in Hamburg! [https://events.ccc.de/congress/2024/hub/de/project/ipod-nano-hacking-freemyipod/ Come say hi!]&lt;br /&gt;
* {{#dateformat:2024-12-16}} - [[S5Late]], a tethered iPod bootrom/DFU exploit for Nano 7G (and possibly Nano 6G), is released.&lt;br /&gt;
* {{#dateformat:2023-12-28}} - [[ipod_sun]], a tool that enables code execution on the iPod nano 6th and 7th generation, is released.&lt;br /&gt;
* {{#dateformat:2023-01-07}} - [https://social.hackerspace.pl/@q3k/109655916469636189 A preliminary U-Boot port to the Nano 5G has been developed.]&lt;br /&gt;
* {{#dateformat:2022-01-04}} - The bootrom of iPod Nano 5G was successfully dumped, and is in the process of being reverse-engineered!&lt;br /&gt;
* {{#dateformat:2021-12-31}} - An exploit named wInd3x, which exploits the latest vulnerability, is being prepared for Nano 4G and Nano 5G.&lt;br /&gt;
* {{#dateformat:2021-12-27}} - A new vulnerability was discovered in iPod Nano 4G and Nano 5G bootrom, which allows arbitrary code execution!&lt;br /&gt;
* {{#dateformat:2018-08-25}} - The website software has been updated to MediaWiki 1.31 after about 2 months of downtime.&lt;br /&gt;
&amp;lt;!--&lt;br /&gt;
* {{#dateformat:2016-06-17}} - The freemyipod project is becoming deprecated, as parts of the code is slowly being integrated in Rockbox. It is likely that no future development on the freemyipod project will take place. Essential parts of emCORE helped building a Rockbox bootloader for iPod Classic, and any future development will take place in the Rockbox project.&lt;br /&gt;
* {{#dateformat:2014-03-26}} - A bug that prevented [[emCORE]] installations on certain Windows configurations (getting stuck on &amp;quot;Booting UBI file...&amp;quot;), has been finally fixed! If the installation has failed for you before, you can retry it using the updated version of our tool (use the iTunes method for now).&lt;br /&gt;
* {{#dateformat:2012-01-02}} - There have been some problems with the latest release. A hotfix release ([[EmCORE_Releases/r859|r859]]) has been published to fix some of these problems. iPod nano 2g users are advised to upgrade.  See the [[EmCORE_Releases/r859|release details page]] for more information.&lt;br /&gt;
* {{#dateformat:2012-01-01}} - A new release &amp;lt;s&amp;gt;([[EmCORE_Releases/r855|r855]])&amp;lt;/s&amp;gt; is out! It includes a couple of new features, several bugfixes and a new bootmenu theme! More information on the &amp;lt;s&amp;gt;[[EmCORE_Releases/r855|release details page]]&amp;lt;/s&amp;gt;.&lt;br /&gt;
* {{#dateformat:2011-04-25}} - The [[emCORE]] kernel now runs on the iPod Touch 2G as well, thanks to the help of kleemajo. This is of course not a fully functional port yet, but we&#039;ll see how it continues. It&#039;s about the same state as the iPod Nano 4G now. /7&lt;br /&gt;
* {{#dateformat:2011-03-25}} - [[emCORE]] is replacing [[emBIOS]] completely now. Therefore [[emBIOS]] will be deprecated software as of now! All emBIOS users are advised to upgrade to emCORE including people using iLoader 0.2.2 or less. More detailed update instructions will follow!&lt;br /&gt;
* {{#dateformat:2011-01-08}} - The Rockbox port for the iPod Classic is slowly getting usable. Most of the blocking issues have been fixed. The  first-generation 160GB model still doesn&#039;t work, and some people are experiencing slightly garbled display contents.&lt;br /&gt;
* {{#dateformat:2011-01-04}} - There is an early Rockbox port for the iPod Classic! It still isn&#039;t quite usable, playback stutters etc., but if you want to play around with it, here are some quick&#039;n&#039;dirty notes on the installation procedure: [[IPod Classic iLoader Installation]]&lt;br /&gt;
* {{#dateformat:2010-11-22}} - We now have emBIOS support for the iPod classic 1g, the others might follow soon&lt;br /&gt;
* {{#dateformat:2010-08-29}} - We&#039;re proud to announce the release of [[emBIOS]] v0.1.0 and [[iLoader]] v0.2.0!&lt;br /&gt;
* {{#dateformat:2010-08-26}} - [[iLoader]], its installer and uninstaller all have been fully ported to [[emBIOS]] now. A beta release will be coming soon!&lt;br /&gt;
* {{#dateformat:2010-08-13}} - [[emBIOS]] is continually being improved and the next step is porting tools like [[iLoader]] to use it.&lt;br /&gt;
* {{#dateformat:2010-08-06}} - The wiki has now been moved to www.freemyipod.org&lt;br /&gt;
* {{#dateformat:2010-08-05}} - Recently we&#039;ve been working on a hardware abstraction project called [[emBIOS]]. Follow development [http://websvn.freemyipod.org/listing.php?repname=freemyipod&amp;amp;path=/embios/ here]&lt;br /&gt;
* {{#dateformat:2010-08-03}} - We can now access the Nano 4G accelerometer.&lt;br /&gt;
* {{#dateformat:2010-08-02}} - serpilliere managed to decrypt the NOR flash on the [[Nano 3G]].&lt;br /&gt;
* {{#dateformat:2010-08-01}} - serpilliere managed to access and dump the NOR flash on the [[Nano 3G]]. This code could possibly work on the Classics.&lt;br /&gt;
* {{#dateformat:2010-07-27}} - The server got zapped by lightning but a new one was up and running within a day.&lt;br /&gt;
* {{#dateformat:2010-02-23}} - We can now execute code on everything besides the [[Nano 5G]]! Minimalistic iBugger working on [[Nano 3G]]!&lt;br /&gt;
* {{#dateformat:2009-11-01}} - iBugger core v0.1 successfully running on [[Nano 4G]]! [http://img217.imageshack.us/img217/4122/img0969.jpg]&lt;br /&gt;
--&amp;gt;&lt;br /&gt;
Follow [http://twitter.com/freemyipod our Twitter feed] to get status updates automatically. See the [[Status]] page for more detailed information. Check our [[ Special:Code/freemyipod|SVN activity ]] page for the latest changes to our source code.&lt;br /&gt;
&lt;br /&gt;
{| cellspacing=&amp;quot;3&amp;quot; width=&amp;quot;100%&amp;quot;&lt;br /&gt;
|- valign=&amp;quot;top&amp;quot;&lt;br /&gt;
|style=&amp;quot;border: 1px dashed #c6c9ff; background-color: #f0f0ff&amp;quot;|&lt;br /&gt;
===Project info===&lt;br /&gt;
* [[ Status ]]&lt;br /&gt;
* [[ Contact ]]&lt;br /&gt;
* [[ Contributing ]]&lt;br /&gt;
&lt;br /&gt;
===Released Software===&lt;br /&gt;
* [[wInd3x]]&lt;br /&gt;
* [[ipod_sun]]&lt;br /&gt;
* [[U-Boot|U-Boot port]]&lt;br /&gt;
* [[Linux|Linux port]]&lt;br /&gt;
* Legacy:&lt;br /&gt;
** [[iBugger]]&lt;br /&gt;
** [[iLoader]]&lt;br /&gt;
** [[emCORE]]&lt;br /&gt;
&lt;br /&gt;
|style=&amp;quot;border: 1px dashed #c6c9ff; background-color: #f0f0ff&amp;quot;|&lt;br /&gt;
&lt;br /&gt;
===Basic skills===&lt;br /&gt;
* [[Working with binaries]]&lt;br /&gt;
* [[Dumping firmware]]&lt;br /&gt;
* [[Extracting firmware]]&lt;br /&gt;
* [[Firmware downgrading]]&lt;br /&gt;
* [[Troubleshooting]]&lt;br /&gt;
&lt;br /&gt;
===Reverse engineering results===&lt;br /&gt;
* [[Firmware]]&lt;br /&gt;
** [[Bootrom]]&lt;br /&gt;
** [[Boot Process]]&lt;br /&gt;
** [[Firmware decryption]]&lt;br /&gt;
** [[FTL|Flash Translation Layer]]&lt;br /&gt;
** [[RetailOS]]&lt;br /&gt;
*** [[RetailOS Options]]&lt;br /&gt;
* [[GUID table]]&lt;br /&gt;
* [[JTAG]]&lt;br /&gt;
* Nano 2G&lt;br /&gt;
** [[Nano2G clock gates‎]]&lt;br /&gt;
** [[Nano2G LCD init]]&lt;br /&gt;
** [[Nano2G HW analysis]]&lt;br /&gt;
** [[S5L8701 analysis]]&lt;br /&gt;
* Nano 4G&lt;br /&gt;
** [[Nano4G firmware upgrade process]]&lt;br /&gt;
* Nano 5G&lt;br /&gt;
** [[Nano 5G|General]]&lt;br /&gt;
&lt;br /&gt;
===Other guides===&lt;br /&gt;
* [[Modes]]&lt;br /&gt;
|style=&amp;quot;border: 1px dashed #c6c9ff; background-color: #f0f0ff&amp;quot;|&lt;br /&gt;
===Hardware===&lt;br /&gt;
* [[Hardware]]&lt;br /&gt;
** [[Nano 1G]]&lt;br /&gt;
** [[Nano 2G]]&lt;br /&gt;
** [[Nano 3G]]&lt;br /&gt;
** [[Nano 4G]]&lt;br /&gt;
*** [[920-0614-03]]&lt;br /&gt;
** [[Nano 5G]]&lt;br /&gt;
** [[Nano 6G]]&lt;br /&gt;
** [[Nano 7G]]&lt;br /&gt;
** [[Classic 1G]]&lt;br /&gt;
** [[Classic 2G]]&lt;br /&gt;
** [[Classic 3G]]&lt;br /&gt;
* [[Chronology]]&lt;br /&gt;
* [[S5L8700 datasheet]]&lt;br /&gt;
&lt;br /&gt;
===Exploiting===&lt;br /&gt;
* [[wInd3x]]&lt;br /&gt;
* [[Pwnage 2.0]]&lt;br /&gt;
* [[Notes vulnerability]]&lt;br /&gt;
** [[Address bruteforcing]]&lt;br /&gt;
** [[Nanotron 3000]]&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22106</id>
		<title>920-0614-03</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22106"/>
		<updated>2024-12-23T01:10:32Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;The 920-0614-03 is seemingly a development/prototype iPod Nano 4G (or possibly iPod Touch 2G board?). It appeared on a bunch of eBay auctions around September 2023.&lt;br /&gt;
&lt;br /&gt;
== Specs ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;SoC&#039;&#039;&#039;: S5L8720&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Flash&#039;&#039;&#039;: Usually desoldered&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;DRAM&#039;&#039;&#039;: To be checked&lt;br /&gt;
&lt;br /&gt;
== UART ==&lt;br /&gt;
&lt;br /&gt;
The boards has at least two ways to access UART:&lt;br /&gt;
&lt;br /&gt;
# Over DE9 connector.&lt;br /&gt;
&lt;br /&gt;
# Over USB/Serial bridge.&lt;br /&gt;
&lt;br /&gt;
# Over 30-pin connector.&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;TODO&#039;&#039;&#039;: Figure out which serial is which, and document reanimating DE9/USB.&lt;br /&gt;
&lt;br /&gt;
== Power ==&lt;br /&gt;
&lt;br /&gt;
The board runs from either the 30-pin connector by itself (although it can sometimes be unstable) or from 5V over a DC power jack (which provides a 4v-ish supply which simulates the devices&#039; battery).&lt;br /&gt;
&lt;br /&gt;
== JTAG ==&lt;br /&gt;
&lt;br /&gt;
[[JTAG]] is available over the 30 pin connector, but is also seemingly locked out as on production devices.&lt;br /&gt;
&lt;br /&gt;
== Getting code to run ==&lt;br /&gt;
&lt;br /&gt;
[[wInd3x]] works on the device. On devices without Flash attempting to run the standard WTF causes a reset.&lt;br /&gt;
&lt;br /&gt;
== Differences from production device ==&lt;br /&gt;
&lt;br /&gt;
=== CHIPID ===&lt;br /&gt;
&lt;br /&gt;
Different CHIPIDL/H values are present in the CHIPID peripheral:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! SoC !! CHIPIDL (&amp;lt;code&amp;gt;0x3d100_0004&amp;lt;/code&amp;gt;) !! CHIPIDH (&amp;lt;code&amp;gt;0x3d100_0008&amp;lt;/code&amp;gt;)&lt;br /&gt;
|-&lt;br /&gt;
| Nano 4G || &amp;lt;code&amp;gt;19000011&amp;lt;/code&amp;gt; || &amp;lt;code&amp;gt;8720000f&amp;lt;/code&amp;gt;&lt;br /&gt;
|-&lt;br /&gt;
| 920-0614-03 || &amp;lt;code&amp;gt;11000001&amp;lt;/code&amp;gt; || &amp;lt;code&amp;gt;8720180f&amp;lt;/code&amp;gt;&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
Effects:&lt;br /&gt;
&lt;br /&gt;
# &amp;lt;code&amp;gt;CHIPIDL &amp;amp; 0x10 == 0&amp;lt;/code&amp;gt;: The BootROM accepts an additional top-level serial: 0x01 0xFB &#039;&#039;&#039;0x00&#039;&#039;&#039; 0xFB in addition to the standard 0x01 0xFB &#039;&#039;&#039;0x01&#039;&#039;&#039; 0xFB&lt;br /&gt;
# &amp;lt;code&amp;gt;CHIPIDL &amp;amp; (1 &amp;lt;&amp;lt; 27) == 0&amp;lt;/code&amp;gt;: The WTF&#039;s ChipID[2] function returns 2 instead of 3 in second argument.&lt;br /&gt;
&lt;br /&gt;
== Pins ==&lt;br /&gt;
&lt;br /&gt;
As the board has clearly labeled and accessible GPIO pins / configuration straps, it&#039;s a good candidate to reverse engineer pin functionality as used in the production device.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! S5L8720 GPIO !! Function on board&lt;br /&gt;
|-&lt;br /&gt;
| 91 || &#039;DFU&#039; button&lt;br /&gt;
|-&lt;br /&gt;
| 5 || DB9 UART TX (J9204)&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
== Case ==&lt;br /&gt;
&lt;br /&gt;
Protective case design: https://www.printables.com/model/628404-920-0614-03-ipod-nano-4g-prototype-case&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Main_Page&amp;diff=22080</id>
		<title>Main Page</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Main_Page&amp;diff=22080"/>
		<updated>2024-08-04T02:13:41Z</updated>

		<summary type="html">&lt;p&gt;Q3k: Removed protection from &amp;quot;Main Page&amp;quot;&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;__NOTOC__&lt;br /&gt;
[[File:EmCORE_Nano2G_Nano4G_Classic.jpg|280px|thumb|right|[[emCORE]] r779 on [[Nano 2G]], [[Nano 4G]] and [[Classic 2G]]]]&lt;br /&gt;
This is the wiki for the freemyipod project. Freemyipod is a project for reverse-engineering iPods with clickwheel (&#039;&#039;&#039;no&#039;&#039;&#039; iOS devices) and creating tools and documentation so that other people can port alternative firmwares to them such as [http://www.rockbox.org rockbox] or Linux. Freemyipod is a relaunch of [[Linux4nano]].&lt;br /&gt;
&lt;br /&gt;
== FAQ ==&lt;br /&gt;
&lt;br /&gt;
=== What can I do with my iPod Nano 2, iPod Classic or older iPods? ===&lt;br /&gt;
&lt;br /&gt;
There&#039;s an upstream Rockbox port for these devices. Go use that.&lt;br /&gt;
&lt;br /&gt;
=== What can I do with my iPod Nano 3/4/5? ===&lt;br /&gt;
&lt;br /&gt;
Not much (yet) unless you&#039;re an embedded developer :).&lt;br /&gt;
&lt;br /&gt;
We have a stable tethered exploit ([[wInd3x]]) which allows early, untethered and safe (no permanent modification) code execution on Nano 3G-5G. This in turn allows you to run [[U-Boot]] and an early [[Linux|Linux port]] or experiment with reverse-engineering/modifying the original firmware, [[OSOS]].&lt;br /&gt;
&lt;br /&gt;
There&#039;s a set of earlier tooling ([[emCORE]]/[[emBIOS]]/[[iBugger]]) which was exploiting other vulnerabilities and was a lead-up to a port of Rockbox, but it&#039;s mostly abandoned.&lt;br /&gt;
&lt;br /&gt;
=== What can I do with my iPod Nano 6/7? ===&lt;br /&gt;
&lt;br /&gt;
Nothing, other than helping us find vulnerabilities to get code execution on them.&lt;br /&gt;
&lt;br /&gt;
== Getting an account ==&lt;br /&gt;
&lt;br /&gt;
Due to spambots, registration is closed. For an account contact [[User:User890104|User890104]] or [[User:Q3k|q3k]].&lt;br /&gt;
&lt;br /&gt;
==Updates==&lt;br /&gt;
* {{#dateformat:2023-01-07}} - [https://social.hackerspace.pl/@q3k/109655916469636189 A preliminary U-Boot port to the Nano 5G has been developed.]&lt;br /&gt;
* {{#dateformat:2022-01-04}} - The bootrom of iPod Nano 5G was successfully dumped, and is in the process of being reverse-engineered!&lt;br /&gt;
* {{#dateformat:2021-12-31}} - An exploit named wInd3x, which exploits the latest vulnerability, is being prepared for Nano 4G and Nano 5G.&lt;br /&gt;
* {{#dateformat:2021-12-27}} - A new vulnerability was discovered in iPod Nano 4G and Nano 5G bootrom, which allows arbitrary code execution!&lt;br /&gt;
* {{#dateformat:2018-08-25}} - The website software has been updated to MediaWiki 1.31 after about 2 months of downtime.&lt;br /&gt;
&amp;lt;!--&lt;br /&gt;
* {{#dateformat:2016-06-17}} - The freemyipod project is becoming deprecated, as parts of the code is slowly being integrated in Rockbox. It is likely that no future development on the freemyipod project will take place. Essential parts of emCORE helped building a Rockbox bootloader for iPod Classic, and any future development will take place in the Rockbox project.&lt;br /&gt;
* {{#dateformat:2014-03-26}} - A bug that prevented [[emCORE]] installations on certain Windows configurations (getting stuck on &amp;quot;Booting UBI file...&amp;quot;), has been finally fixed! If the installation has failed for you before, you can retry it using the updated version of our tool (use the iTunes method for now).&lt;br /&gt;
* {{#dateformat:2012-01-02}} - There have been some problems with the latest release. A hotfix release ([[EmCORE_Releases/r859|r859]]) has been published to fix some of these problems. iPod nano 2g users are advised to upgrade.  See the [[EmCORE_Releases/r859|release details page]] for more information.&lt;br /&gt;
* {{#dateformat:2012-01-01}} - A new release &amp;lt;s&amp;gt;([[EmCORE_Releases/r855|r855]])&amp;lt;/s&amp;gt; is out! It includes a couple of new features, several bugfixes and a new bootmenu theme! More information on the &amp;lt;s&amp;gt;[[EmCORE_Releases/r855|release details page]]&amp;lt;/s&amp;gt;.&lt;br /&gt;
* {{#dateformat:2011-04-25}} - The [[emCORE]] kernel now runs on the iPod Touch 2G as well, thanks to the help of kleemajo. This is of course not a fully functional port yet, but we&#039;ll see how it continues. It&#039;s about the same state as the iPod Nano 4G now. /7&lt;br /&gt;
* {{#dateformat:2011-03-25}} - [[emCORE]] is replacing [[emBIOS]] completely now. Therefore [[emBIOS]] will be deprecated software as of now! All emBIOS users are advised to upgrade to emCORE including people using iLoader 0.2.2 or less. More detailed update instructions will follow!&lt;br /&gt;
* {{#dateformat:2011-01-08}} - The Rockbox port for the iPod Classic is slowly getting usable. Most of the blocking issues have been fixed. The  first-generation 160GB model still doesn&#039;t work, and some people are experiencing slightly garbled display contents.&lt;br /&gt;
* {{#dateformat:2011-01-04}} - There is an early Rockbox port for the iPod Classic! It still isn&#039;t quite usable, playback stutters etc., but if you want to play around with it, here are some quick&#039;n&#039;dirty notes on the installation procedure: [[IPod Classic iLoader Installation]]&lt;br /&gt;
* {{#dateformat:2010-11-22}} - We now have emBIOS support for the iPod classic 1g, the others might follow soon&lt;br /&gt;
* {{#dateformat:2010-08-29}} - We&#039;re proud to announce the release of [[emBIOS]] v0.1.0 and [[iLoader]] v0.2.0!&lt;br /&gt;
* {{#dateformat:2010-08-26}} - [[iLoader]], its installer and uninstaller all have been fully ported to [[emBIOS]] now. A beta release will be coming soon!&lt;br /&gt;
* {{#dateformat:2010-08-13}} - [[emBIOS]] is continually being improved and the next step is porting tools like [[iLoader]] to use it.&lt;br /&gt;
* {{#dateformat:2010-08-06}} - The wiki has now been moved to www.freemyipod.org&lt;br /&gt;
* {{#dateformat:2010-08-05}} - Recently we&#039;ve been working on a hardware abstraction project called [[emBIOS]]. Follow development [http://websvn.freemyipod.org/listing.php?repname=freemyipod&amp;amp;path=/embios/ here]&lt;br /&gt;
* {{#dateformat:2010-08-03}} - We can now access the Nano 4G accelerometer.&lt;br /&gt;
* {{#dateformat:2010-08-02}} - serpilliere managed to decrypt the NOR flash on the [[Nano 3G]].&lt;br /&gt;
* {{#dateformat:2010-08-01}} - serpilliere managed to access and dump the NOR flash on the [[Nano 3G]]. This code could possibly work on the Classics.&lt;br /&gt;
* {{#dateformat:2010-07-27}} - The server got zapped by lightning but a new one was up and running within a day.&lt;br /&gt;
* {{#dateformat:2010-02-23}} - We can now execute code on everything besides the [[Nano 5G]]! Minimalistic iBugger working on [[Nano 3G]]!&lt;br /&gt;
* {{#dateformat:2009-11-01}} - iBugger core v0.1 successfully running on [[Nano 4G]]! [http://img217.imageshack.us/img217/4122/img0969.jpg]&lt;br /&gt;
--&amp;gt;&lt;br /&gt;
Follow [http://twitter.com/freemyipod our Twitter feed] to get status updates automatically. See the [[Status]] page for more detailed information. Check our [[ Special:Code/freemyipod|SVN activity ]] page for the latest changes to our source code.&lt;br /&gt;
&lt;br /&gt;
{| cellspacing=&amp;quot;3&amp;quot; width=&amp;quot;100%&amp;quot;&lt;br /&gt;
|- valign=&amp;quot;top&amp;quot;&lt;br /&gt;
|style=&amp;quot;border: 1px dashed #c6c9ff; background-color: #f0f0ff&amp;quot;|&lt;br /&gt;
===Project info===&lt;br /&gt;
* [[ Status ]]&lt;br /&gt;
* [[ Contact ]]&lt;br /&gt;
* [[ Contributing ]]&lt;br /&gt;
&lt;br /&gt;
===Released Software===&lt;br /&gt;
* [[wInd3x]]&lt;br /&gt;
* [[U-Boot|U-Boot port]]&lt;br /&gt;
* [[Linux|Linux port]]&lt;br /&gt;
* Legacy:&lt;br /&gt;
** [[iBugger]]&lt;br /&gt;
** [[iLoader]]&lt;br /&gt;
** [[emCORE]]&lt;br /&gt;
&lt;br /&gt;
|style=&amp;quot;border: 1px dashed #c6c9ff; background-color: #f0f0ff&amp;quot;|&lt;br /&gt;
&lt;br /&gt;
===Basic skills===&lt;br /&gt;
* [[Working with binaries]]&lt;br /&gt;
* [[Dumping firmware]]&lt;br /&gt;
* [[Extracting firmware]]&lt;br /&gt;
* [[Firmware downgrading]]&lt;br /&gt;
* [[Troubleshooting]]&lt;br /&gt;
&lt;br /&gt;
===Reverse engineering results===&lt;br /&gt;
* [[Firmware]]&lt;br /&gt;
** [[Bootrom]]&lt;br /&gt;
** [[Boot Process]]&lt;br /&gt;
** [[Firmware decryption]]&lt;br /&gt;
** [[FTL|Flash Translation Layer]]&lt;br /&gt;
** [[RetailOS]]&lt;br /&gt;
*** [[RetailOS Options]]&lt;br /&gt;
* [[GUID table]]&lt;br /&gt;
* [[JTAG]]&lt;br /&gt;
* Nano 2G&lt;br /&gt;
** [[Nano2G clock gates‎]]&lt;br /&gt;
** [[Nano2G LCD init]]&lt;br /&gt;
** [[Nano2G HW analysis]]&lt;br /&gt;
** [[S5L8701 analysis]]&lt;br /&gt;
* Nano 4G&lt;br /&gt;
** [[Nano4G firmware upgrade process]]&lt;br /&gt;
* Nano 5G&lt;br /&gt;
** [[Nano 5G|General]]&lt;br /&gt;
&lt;br /&gt;
===Other guides===&lt;br /&gt;
* [[Modes]]&lt;br /&gt;
|style=&amp;quot;border: 1px dashed #c6c9ff; background-color: #f0f0ff&amp;quot;|&lt;br /&gt;
===Hardware===&lt;br /&gt;
* [[Hardware]]&lt;br /&gt;
** [[Nano 1G]]&lt;br /&gt;
** [[Nano 2G]]&lt;br /&gt;
** [[Nano 3G]]&lt;br /&gt;
** [[Nano 4G]]&lt;br /&gt;
*** [[920-0614-03]]&lt;br /&gt;
** [[Nano 5G]]&lt;br /&gt;
** [[Nano 6G]]&lt;br /&gt;
** [[Classic 1G]]&lt;br /&gt;
** [[Classic 2G]]&lt;br /&gt;
** [[Classic 3G]]&lt;br /&gt;
* [[Chronology]]&lt;br /&gt;
* [[S5L8700 datasheet]]&lt;br /&gt;
&lt;br /&gt;
===Exploiting===&lt;br /&gt;
* [[wInd3x]]&lt;br /&gt;
* [[Pwnage 2.0]]&lt;br /&gt;
* [[Notes vulnerability]]&lt;br /&gt;
** [[Address bruteforcing]]&lt;br /&gt;
** [[Nanotron 3000]]&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22074</id>
		<title>920-0614-03</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22074"/>
		<updated>2024-05-05T10:21:26Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* Pins */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;The 920-0614-03 is seemingly a development/prototype iPod Nano 4G (or possibly iPod Touch 2G board?). It appeared on a bunch of eBay auctions around September 2023.&lt;br /&gt;
&lt;br /&gt;
== Specs ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;SoC&#039;&#039;&#039;: S5L8729&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Flash&#039;&#039;&#039;: Usually desoldered&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;DRAM&#039;&#039;&#039;: To be checked&lt;br /&gt;
&lt;br /&gt;
== UART ==&lt;br /&gt;
&lt;br /&gt;
The boards has at least two ways to access UART:&lt;br /&gt;
&lt;br /&gt;
# Over DE9 connector.&lt;br /&gt;
&lt;br /&gt;
# Over USB/Serial bridge.&lt;br /&gt;
&lt;br /&gt;
# Over 30-pin connector.&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;TODO&#039;&#039;&#039;: Figure out which serial is which, and document reanimating DE9/USB.&lt;br /&gt;
&lt;br /&gt;
== Power ==&lt;br /&gt;
&lt;br /&gt;
The board runs from either the 30-pin connector by itself (although it can sometimes be unstable) or from 5V over a DC power jack (which provides a 4v-ish supply which simulates the devices&#039; battery).&lt;br /&gt;
&lt;br /&gt;
== JTAG ==&lt;br /&gt;
&lt;br /&gt;
[[JTAG]] is available over the 30 pin connector, but is also seemingly locked out as on production devices.&lt;br /&gt;
&lt;br /&gt;
== Getting code to run ==&lt;br /&gt;
&lt;br /&gt;
[[wInd3x]] works on the device. On devices without Flash attempting to run the standard WTF causes a reset.&lt;br /&gt;
&lt;br /&gt;
== Differences from production device ==&lt;br /&gt;
&lt;br /&gt;
=== CHIPID ===&lt;br /&gt;
&lt;br /&gt;
Different CHIPIDL/H values are present in the CHIPID peripheral:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! SoC !! CHIPIDL (&amp;lt;code&amp;gt;0x3d100_0004&amp;lt;/code&amp;gt;) !! CHIPIDH (&amp;lt;code&amp;gt;0x3d100_0008&amp;lt;/code&amp;gt;)&lt;br /&gt;
|-&lt;br /&gt;
| Nano 4G || &amp;lt;code&amp;gt;19000011&amp;lt;/code&amp;gt; || &amp;lt;code&amp;gt;8720000f&amp;lt;/code&amp;gt;&lt;br /&gt;
|-&lt;br /&gt;
| 920-0614-03 || &amp;lt;code&amp;gt;11000001&amp;lt;/code&amp;gt; || &amp;lt;code&amp;gt;8720180f&amp;lt;/code&amp;gt;&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
Effects:&lt;br /&gt;
&lt;br /&gt;
# &amp;lt;code&amp;gt;CHIPIDL &amp;amp; 0x10 == 0&amp;lt;/code&amp;gt;: The BootROM accepts an additional top-level serial: 0x01 0xFB &#039;&#039;&#039;0x00&#039;&#039;&#039; 0xFB in addition to the standard 0x01 0xFB &#039;&#039;&#039;0x01&#039;&#039;&#039; 0xFB&lt;br /&gt;
# &amp;lt;code&amp;gt;CHIPIDL &amp;amp; (1 &amp;lt;&amp;lt; 27) == 0&amp;lt;/code&amp;gt;: The WTF&#039;s ChipID[2] function returns 2 instead of 3 in *second argument.&lt;br /&gt;
&lt;br /&gt;
== Pins ==&lt;br /&gt;
&lt;br /&gt;
As the board has clearly labeled and accessible GPIO pins / configuration straps, it&#039;s a good candidate to reverse engineer pin functionality as used in the production device.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! S5L8720 GPIO !! Function on board&lt;br /&gt;
|-&lt;br /&gt;
| 91 || &#039;DFU&#039; button&lt;br /&gt;
|-&lt;br /&gt;
| 5 || DB9 UART TX (J9204)&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
== Case ==&lt;br /&gt;
&lt;br /&gt;
Protective case design: https://www.printables.com/model/628404-920-0614-03-ipod-nano-4g-prototype-case&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22073</id>
		<title>920-0614-03</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22073"/>
		<updated>2024-05-04T14:42:08Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* Pins */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;The 920-0614-03 is seemingly a development/prototype iPod Nano 4G (or possibly iPod Touch 2G board?). It appeared on a bunch of eBay auctions around September 2023.&lt;br /&gt;
&lt;br /&gt;
== Specs ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;SoC&#039;&#039;&#039;: S5L8729&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Flash&#039;&#039;&#039;: Usually desoldered&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;DRAM&#039;&#039;&#039;: To be checked&lt;br /&gt;
&lt;br /&gt;
== UART ==&lt;br /&gt;
&lt;br /&gt;
The boards has at least two ways to access UART:&lt;br /&gt;
&lt;br /&gt;
# Over DE9 connector.&lt;br /&gt;
&lt;br /&gt;
# Over USB/Serial bridge.&lt;br /&gt;
&lt;br /&gt;
# Over 30-pin connector.&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;TODO&#039;&#039;&#039;: Figure out which serial is which, and document reanimating DE9/USB.&lt;br /&gt;
&lt;br /&gt;
== Power ==&lt;br /&gt;
&lt;br /&gt;
The board runs from either the 30-pin connector by itself (although it can sometimes be unstable) or from 5V over a DC power jack (which provides a 4v-ish supply which simulates the devices&#039; battery).&lt;br /&gt;
&lt;br /&gt;
== JTAG ==&lt;br /&gt;
&lt;br /&gt;
[[JTAG]] is available over the 30 pin connector, but is also seemingly locked out as on production devices.&lt;br /&gt;
&lt;br /&gt;
== Getting code to run ==&lt;br /&gt;
&lt;br /&gt;
[[wInd3x]] works on the device. On devices without Flash attempting to run the standard WTF causes a reset.&lt;br /&gt;
&lt;br /&gt;
== Differences from production device ==&lt;br /&gt;
&lt;br /&gt;
=== CHIPID ===&lt;br /&gt;
&lt;br /&gt;
Different CHIPIDL/H values are present in the CHIPID peripheral:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! SoC !! CHIPIDL (&amp;lt;code&amp;gt;0x3d100_0004&amp;lt;/code&amp;gt;) !! CHIPIDH (&amp;lt;code&amp;gt;0x3d100_0008&amp;lt;/code&amp;gt;)&lt;br /&gt;
|-&lt;br /&gt;
| Nano 4G || &amp;lt;code&amp;gt;19000011&amp;lt;/code&amp;gt; || &amp;lt;code&amp;gt;8720000f&amp;lt;/code&amp;gt;&lt;br /&gt;
|-&lt;br /&gt;
| 920-0614-03 || &amp;lt;code&amp;gt;11000001&amp;lt;/code&amp;gt; || &amp;lt;code&amp;gt;8720180f&amp;lt;/code&amp;gt;&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
Effects:&lt;br /&gt;
&lt;br /&gt;
# &amp;lt;code&amp;gt;CHIPIDL &amp;amp; 0x10 == 0&amp;lt;/code&amp;gt;: The BootROM accepts an additional top-level serial: 0x01 0xFB &#039;&#039;&#039;0x00&#039;&#039;&#039; 0xFB in addition to the standard 0x01 0xFB &#039;&#039;&#039;0x01&#039;&#039;&#039; 0xFB&lt;br /&gt;
# &amp;lt;code&amp;gt;CHIPIDL &amp;amp; (1 &amp;lt;&amp;lt; 27) == 0&amp;lt;/code&amp;gt;: The WTF&#039;s ChipID[2] function returns 2 instead of 3 in *second argument.&lt;br /&gt;
&lt;br /&gt;
== Pins ==&lt;br /&gt;
&lt;br /&gt;
As the board has clearly labeled and accessible GPIO pins / configuration straps, it&#039;s a good candidate to reverse engineer pin functionality as used in the production device.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! S5L8720 GPIO !! Function on board&lt;br /&gt;
|-&lt;br /&gt;
| 91 || &#039;DFU&#039; button&lt;br /&gt;
|-&lt;br /&gt;
| 2 || DB9 UART TX (J9205)&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
== Case ==&lt;br /&gt;
&lt;br /&gt;
Protective case design: https://www.printables.com/model/628404-920-0614-03-ipod-nano-4g-prototype-case&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Main_Page&amp;diff=22072</id>
		<title>Main Page</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Main_Page&amp;diff=22072"/>
		<updated>2024-05-04T14:41:40Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;__NOTOC__&lt;br /&gt;
[[File:EmCORE_Nano2G_Nano4G_Classic.jpg|280px|thumb|right|[[emCORE]] r779 on [[Nano 2G]], [[Nano 4G]] and [[Classic 2G]]]]&lt;br /&gt;
This is the wiki for the freemyipod project. Freemyipod is a project for reverse-engineering iPods with clickwheel (&#039;&#039;&#039;no&#039;&#039;&#039; iOS devices) and creating tools and documentation so that other people can port alternative firmwares to them such as [http://www.rockbox.org rockbox] or Linux. Freemyipod is a relaunch of [[Linux4nano]].&lt;br /&gt;
&lt;br /&gt;
== FAQ ==&lt;br /&gt;
&lt;br /&gt;
=== What can I do with my iPod Nano 2, iPod Classic or older iPods? ===&lt;br /&gt;
&lt;br /&gt;
There&#039;s an upstream Rockbox port for these devices. Go use that.&lt;br /&gt;
&lt;br /&gt;
=== What can I do with my iPod Nano 3/4/5? ===&lt;br /&gt;
&lt;br /&gt;
Not much (yet) unless you&#039;re an embedded developer :).&lt;br /&gt;
&lt;br /&gt;
We have a stable tethered exploit ([[wInd3x]]) which allows early, untethered and safe (no permanent modification) code execution on Nano 3G-5G. This in turn allows you to run [[U-Boot]] and an early [[Linux|Linux port]] or experiment with reverse-engineering/modifying the original firmware, [[OSOS]].&lt;br /&gt;
&lt;br /&gt;
There&#039;s a set of earlier tooling ([[emCORE]]/[[emBIOS]]/[[iBugger]]) which was exploiting other vulnerabilities and was a lead-up to a port of Rockbox, but it&#039;s mostly abandoned.&lt;br /&gt;
&lt;br /&gt;
=== What can I do with my iPod Nano 6/7? ===&lt;br /&gt;
&lt;br /&gt;
Nothing, other than helping us find vulnerabilities to get code execution on them.&lt;br /&gt;
&lt;br /&gt;
== Getting an account ==&lt;br /&gt;
&lt;br /&gt;
Due to spambots, registration is closed. For an account contact [[User:User890104|User890104]] or [[User:Q3k|q3k]].&lt;br /&gt;
&lt;br /&gt;
==Updates==&lt;br /&gt;
* {{#dateformat:2023-01-07}} - [https://social.hackerspace.pl/@q3k/109655916469636189 A preliminary U-Boot port to the Nano 5G has been developed.]&lt;br /&gt;
* {{#dateformat:2022-01-04}} - The bootrom of iPod Nano 5G was successfully dumped, and is in the process of being reverse-engineered!&lt;br /&gt;
* {{#dateformat:2021-12-31}} - An exploit named wInd3x, which exploits the latest vulnerability, is being prepared for Nano 4G and Nano 5G.&lt;br /&gt;
* {{#dateformat:2021-12-27}} - A new vulnerability was discovered in iPod Nano 4G and Nano 5G bootrom, which allows arbitrary code execution!&lt;br /&gt;
* {{#dateformat:2018-08-25}} - The website software has been updated to MediaWiki 1.31 after about 2 months of downtime.&lt;br /&gt;
&amp;lt;!--&lt;br /&gt;
* {{#dateformat:2016-06-17}} - The freemyipod project is becoming deprecated, as parts of the code is slowly being integrated in Rockbox. It is likely that no future development on the freemyipod project will take place. Essential parts of emCORE helped building a Rockbox bootloader for iPod Classic, and any future development will take place in the Rockbox project.&lt;br /&gt;
* {{#dateformat:2014-03-26}} - A bug that prevented [[emCORE]] installations on certain Windows configurations (getting stuck on &amp;quot;Booting UBI file...&amp;quot;), has been finally fixed! If the installation has failed for you before, you can retry it using the updated version of our tool (use the iTunes method for now).&lt;br /&gt;
* {{#dateformat:2012-01-02}} - There have been some problems with the latest release. A hotfix release ([[EmCORE_Releases/r859|r859]]) has been published to fix some of these problems. iPod nano 2g users are advised to upgrade.  See the [[EmCORE_Releases/r859|release details page]] for more information.&lt;br /&gt;
* {{#dateformat:2012-01-01}} - A new release &amp;lt;s&amp;gt;([[EmCORE_Releases/r855|r855]])&amp;lt;/s&amp;gt; is out! It includes a couple of new features, several bugfixes and a new bootmenu theme! More information on the &amp;lt;s&amp;gt;[[EmCORE_Releases/r855|release details page]]&amp;lt;/s&amp;gt;.&lt;br /&gt;
* {{#dateformat:2011-04-25}} - The [[emCORE]] kernel now runs on the iPod Touch 2G as well, thanks to the help of kleemajo. This is of course not a fully functional port yet, but we&#039;ll see how it continues. It&#039;s about the same state as the iPod Nano 4G now. /7&lt;br /&gt;
* {{#dateformat:2011-03-25}} - [[emCORE]] is replacing [[emBIOS]] completely now. Therefore [[emBIOS]] will be deprecated software as of now! All emBIOS users are advised to upgrade to emCORE including people using iLoader 0.2.2 or less. More detailed update instructions will follow!&lt;br /&gt;
* {{#dateformat:2011-01-08}} - The Rockbox port for the iPod Classic is slowly getting usable. Most of the blocking issues have been fixed. The  first-generation 160GB model still doesn&#039;t work, and some people are experiencing slightly garbled display contents.&lt;br /&gt;
* {{#dateformat:2011-01-04}} - There is an early Rockbox port for the iPod Classic! It still isn&#039;t quite usable, playback stutters etc., but if you want to play around with it, here are some quick&#039;n&#039;dirty notes on the installation procedure: [[IPod Classic iLoader Installation]]&lt;br /&gt;
* {{#dateformat:2010-11-22}} - We now have emBIOS support for the iPod classic 1g, the others might follow soon&lt;br /&gt;
* {{#dateformat:2010-08-29}} - We&#039;re proud to announce the release of [[emBIOS]] v0.1.0 and [[iLoader]] v0.2.0!&lt;br /&gt;
* {{#dateformat:2010-08-26}} - [[iLoader]], its installer and uninstaller all have been fully ported to [[emBIOS]] now. A beta release will be coming soon!&lt;br /&gt;
* {{#dateformat:2010-08-13}} - [[emBIOS]] is continually being improved and the next step is porting tools like [[iLoader]] to use it.&lt;br /&gt;
* {{#dateformat:2010-08-06}} - The wiki has now been moved to www.freemyipod.org&lt;br /&gt;
* {{#dateformat:2010-08-05}} - Recently we&#039;ve been working on a hardware abstraction project called [[emBIOS]]. Follow development [http://websvn.freemyipod.org/listing.php?repname=freemyipod&amp;amp;path=/embios/ here]&lt;br /&gt;
* {{#dateformat:2010-08-03}} - We can now access the Nano 4G accelerometer.&lt;br /&gt;
* {{#dateformat:2010-08-02}} - serpilliere managed to decrypt the NOR flash on the [[Nano 3G]].&lt;br /&gt;
* {{#dateformat:2010-08-01}} - serpilliere managed to access and dump the NOR flash on the [[Nano 3G]]. This code could possibly work on the Classics.&lt;br /&gt;
* {{#dateformat:2010-07-27}} - The server got zapped by lightning but a new one was up and running within a day.&lt;br /&gt;
* {{#dateformat:2010-02-23}} - We can now execute code on everything besides the [[Nano 5G]]! Minimalistic iBugger working on [[Nano 3G]]!&lt;br /&gt;
* {{#dateformat:2009-11-01}} - iBugger core v0.1 successfully running on [[Nano 4G]]! [http://img217.imageshack.us/img217/4122/img0969.jpg]&lt;br /&gt;
--&amp;gt;&lt;br /&gt;
Follow [http://twitter.com/freemyipod our Twitter feed] to get status updates automatically. See the [[Status]] page for more detailed information. Check our [[ Special:Code/freemyipod|SVN activity ]] page for the latest changes to our source code.&lt;br /&gt;
&lt;br /&gt;
{| cellspacing=&amp;quot;3&amp;quot; width=&amp;quot;100%&amp;quot;&lt;br /&gt;
|- valign=&amp;quot;top&amp;quot;&lt;br /&gt;
|style=&amp;quot;border: 1px dashed #c6c9ff; background-color: #f0f0ff&amp;quot;|&lt;br /&gt;
===Project info===&lt;br /&gt;
* [[ Status ]]&lt;br /&gt;
* [[ Contact ]]&lt;br /&gt;
* [[ Contributing ]]&lt;br /&gt;
&lt;br /&gt;
===Released Software===&lt;br /&gt;
* [[wInd3x]]&lt;br /&gt;
* [[U-Boot|U-Boot port]]&lt;br /&gt;
* [[Linux|Linux port]]&lt;br /&gt;
* Legacy:&lt;br /&gt;
** [[iBugger]]&lt;br /&gt;
** [[iLoader]]&lt;br /&gt;
** [[emCORE]]&lt;br /&gt;
&lt;br /&gt;
|style=&amp;quot;border: 1px dashed #c6c9ff; background-color: #f0f0ff&amp;quot;|&lt;br /&gt;
&lt;br /&gt;
===Basic skills===&lt;br /&gt;
* [[Working with binaries]]&lt;br /&gt;
* [[Dumping firmware]]&lt;br /&gt;
* [[Extracting firmware]]&lt;br /&gt;
* [[Firmware downgrading]]&lt;br /&gt;
* [[Troubleshooting]]&lt;br /&gt;
&lt;br /&gt;
===Reverse engineering results===&lt;br /&gt;
* [[Firmware]]&lt;br /&gt;
** [[Bootrom]]&lt;br /&gt;
** [[Boot Process]]&lt;br /&gt;
** [[Firmware decryption]]&lt;br /&gt;
** [[FTL|Flash Translation Layer]]&lt;br /&gt;
** [[RetailOS]]&lt;br /&gt;
*** [[RetailOS Options]]&lt;br /&gt;
* [[GUID table]]&lt;br /&gt;
* [[JTAG]]&lt;br /&gt;
* Nano 2G&lt;br /&gt;
** [[Nano2G clock gates‎]]&lt;br /&gt;
** [[Nano2G LCD init]]&lt;br /&gt;
** [[Nano2G HW analysis]]&lt;br /&gt;
** [[S5L8701 analysis]]&lt;br /&gt;
* Nano 4G&lt;br /&gt;
** [[Nano4G firmware upgrade process]]&lt;br /&gt;
* Nano 5G&lt;br /&gt;
** [[Nano 5G|General]]&lt;br /&gt;
&lt;br /&gt;
===Other guides===&lt;br /&gt;
* [[Modes]]&lt;br /&gt;
|style=&amp;quot;border: 1px dashed #c6c9ff; background-color: #f0f0ff&amp;quot;|&lt;br /&gt;
===Hardware===&lt;br /&gt;
* [[Hardware]]&lt;br /&gt;
** [[Nano 1G]]&lt;br /&gt;
** [[Nano 2G]]&lt;br /&gt;
** [[Nano 3G]]&lt;br /&gt;
** [[Nano 4G]]&lt;br /&gt;
*** [[920-0614-03]]&lt;br /&gt;
** [[Nano 5G]]&lt;br /&gt;
** [[Nano 6G]]&lt;br /&gt;
** [[Classic 1G]]&lt;br /&gt;
** [[Classic 2G]]&lt;br /&gt;
** [[Classic 3G]]&lt;br /&gt;
* [[Chronology]]&lt;br /&gt;
* [[S5L8700 datasheet]]&lt;br /&gt;
&lt;br /&gt;
===Exploiting===&lt;br /&gt;
* [[wInd3x]]&lt;br /&gt;
* [[Pwnage 2.0]]&lt;br /&gt;
* [[Notes vulnerability]]&lt;br /&gt;
** [[Address bruteforcing]]&lt;br /&gt;
** [[Nanotron 3000]]&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22063</id>
		<title>920-0614-03</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22063"/>
		<updated>2023-10-27T16:56:48Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;The 920-0614-03 is seemingly a development/prototype iPod Nano 4G (or possibly iPod Touch 2G board?). It appeared on a bunch of eBay auctions around September 2023.&lt;br /&gt;
&lt;br /&gt;
== Specs ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;SoC&#039;&#039;&#039;: S5L8729&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Flash&#039;&#039;&#039;: Usually desoldered&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;DRAM&#039;&#039;&#039;: To be checked&lt;br /&gt;
&lt;br /&gt;
== UART ==&lt;br /&gt;
&lt;br /&gt;
The boards has at least two ways to access UART:&lt;br /&gt;
&lt;br /&gt;
# Over DE9 connector.&lt;br /&gt;
&lt;br /&gt;
# Over USB/Serial bridge.&lt;br /&gt;
&lt;br /&gt;
# Over 30-pin connector.&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;TODO&#039;&#039;&#039;: Figure out which serial is which, and document reanimating DE9/USB.&lt;br /&gt;
&lt;br /&gt;
== Power ==&lt;br /&gt;
&lt;br /&gt;
The board runs from either the 30-pin connector by itself (although it can sometimes be unstable) or from 5V over a DC power jack (which provides a 4v-ish supply which simulates the devices&#039; battery).&lt;br /&gt;
&lt;br /&gt;
== JTAG ==&lt;br /&gt;
&lt;br /&gt;
[[JTAG]] is available over the 30 pin connector, but is also seemingly locked out as on production devices.&lt;br /&gt;
&lt;br /&gt;
== Getting code to run ==&lt;br /&gt;
&lt;br /&gt;
[[wInd3x]] works on the device. On devices without Flash attempting to run the standard WTF causes a reset.&lt;br /&gt;
&lt;br /&gt;
== Differences from production device ==&lt;br /&gt;
&lt;br /&gt;
=== CHIPID ===&lt;br /&gt;
&lt;br /&gt;
Different CHIPIDL/H values are present in the CHIPID peripheral:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! SoC !! CHIPIDL (&amp;lt;code&amp;gt;0x3d100_0004&amp;lt;/code&amp;gt;) !! CHIPIDH (&amp;lt;code&amp;gt;0x3d100_0008&amp;lt;/code&amp;gt;)&lt;br /&gt;
|-&lt;br /&gt;
| Nano 4G || &amp;lt;code&amp;gt;19000011&amp;lt;/code&amp;gt; || &amp;lt;code&amp;gt;8720000f&amp;lt;/code&amp;gt;&lt;br /&gt;
|-&lt;br /&gt;
| 920-0614-03 || &amp;lt;code&amp;gt;11000001&amp;lt;/code&amp;gt; || &amp;lt;code&amp;gt;8720180f&amp;lt;/code&amp;gt;&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
Effects:&lt;br /&gt;
&lt;br /&gt;
# &amp;lt;code&amp;gt;CHIPIDL &amp;amp; 0x10 == 0&amp;lt;/code&amp;gt;: The BootROM accepts an additional top-level serial: 0x01 0xFB &#039;&#039;&#039;0x00&#039;&#039;&#039; 0xFB in addition to the standard 0x01 0xFB &#039;&#039;&#039;0x01&#039;&#039;&#039; 0xFB&lt;br /&gt;
# &amp;lt;code&amp;gt;CHIPIDL &amp;amp; (1 &amp;lt;&amp;lt; 27) == 0&amp;lt;/code&amp;gt;: The WTF&#039;s ChipID[2] function returns 2 instead of 3 in *second argument.&lt;br /&gt;
&lt;br /&gt;
== Pins ==&lt;br /&gt;
&lt;br /&gt;
As the board has clearly labeled and accessible GPIO pins / configuration straps, it&#039;s a good candidate to reverse engineer pin functionality as used in the production device.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! S5L8720 GPIO !! Function on board&lt;br /&gt;
|-&lt;br /&gt;
| 91 || &#039;DFU&#039; button&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
== Case ==&lt;br /&gt;
&lt;br /&gt;
Protective case design: https://www.printables.com/model/628404-920-0614-03-ipod-nano-4g-prototype-case&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22062</id>
		<title>920-0614-03</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22062"/>
		<updated>2023-10-27T15:49:41Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* Differences from production device */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;The 920-0614-03 is seemingly a development/prototype iPod Nano 4G (or possibly iPod Touch 2G board?). It appeared on a bunch of eBay auctions around September 2023.&lt;br /&gt;
&lt;br /&gt;
== Specs ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;SoC&#039;&#039;&#039;: S5L8729&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Flash&#039;&#039;&#039;: Usually desoldered&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;DRAM&#039;&#039;&#039;: To be checked&lt;br /&gt;
&lt;br /&gt;
== UART ==&lt;br /&gt;
&lt;br /&gt;
The boards has at least two ways to access UART:&lt;br /&gt;
&lt;br /&gt;
# Over DE9 connector.&lt;br /&gt;
&lt;br /&gt;
# Over USB/Serial bridge.&lt;br /&gt;
&lt;br /&gt;
# Over 30-pin connector.&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;TODO&#039;&#039;&#039;: Figure out which serial is which, and document reanimating DE9/USB.&lt;br /&gt;
&lt;br /&gt;
== Power ==&lt;br /&gt;
&lt;br /&gt;
The board runs from either the 30-pin connector by itself (although it can sometimes be unstable) or from 5V over a DC power jack (which provides a 4v-ish supply which simulates the devices&#039; battery).&lt;br /&gt;
&lt;br /&gt;
== JTAG ==&lt;br /&gt;
&lt;br /&gt;
[[JTAG]] is available over the 30 pin connector, but is also seemingly locked out as on production devices.&lt;br /&gt;
&lt;br /&gt;
== Getting code to run ==&lt;br /&gt;
&lt;br /&gt;
[[wInd3x]] works on the device. On devices without Flash attempting to run the standard WTF causes a reset.&lt;br /&gt;
&lt;br /&gt;
== Differences from production device ==&lt;br /&gt;
&lt;br /&gt;
=== CHIPID ===&lt;br /&gt;
&lt;br /&gt;
Different CHIPIDL/H values are present in the CHIPID peripheral:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! SoC !! CHIPIDL (&amp;lt;code&amp;gt;0x3d100_0004&amp;lt;/code&amp;gt;) !! CHIPIDH (&amp;lt;code&amp;gt;0x3d100_0008&amp;lt;/code&amp;gt;)&lt;br /&gt;
|-&lt;br /&gt;
| Nano 4G || &amp;lt;code&amp;gt;19000011&amp;lt;/code&amp;gt; || &amp;lt;code&amp;gt;8720000f&amp;lt;/code&amp;gt;&lt;br /&gt;
|-&lt;br /&gt;
| 920-0614-03 || &amp;lt;code&amp;gt;11000001&amp;lt;/code&amp;gt; || &amp;lt;code&amp;gt;8720180f&amp;lt;/code&amp;gt;&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
Effects:&lt;br /&gt;
&lt;br /&gt;
# &amp;lt;code&amp;gt;CHIPIDL &amp;amp; 0x10 == 0&amp;lt;/code&amp;gt;: The BootROM accepts an additional top-level serial: 0x01 0xFB &#039;&#039;&#039;0x00&#039;&#039;&#039; 0xFB in addition to the standard 0x01 0xFB &#039;&#039;&#039;0x01&#039;&#039;&#039; 0xFB&lt;br /&gt;
# &amp;lt;code&amp;gt;CHIPIDL &amp;amp; (1 &amp;lt;&amp;lt; 27) == 0&amp;lt;/code&amp;gt;: The WTF&#039;s ChipID[2] function returns 2 instead of 3 in *second argument.&lt;br /&gt;
&lt;br /&gt;
== Pins ==&lt;br /&gt;
&lt;br /&gt;
As the board has clearly labeled and accessible GPIO pins / configuration straps, it&#039;s a good candidate to reverse engineer pin functionality as used in the production device.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! S5L8720 GPIO !! Function on board&lt;br /&gt;
|-&lt;br /&gt;
| 91 || &#039;DFU&#039; button&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22061</id>
		<title>920-0614-03</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22061"/>
		<updated>2023-10-27T15:47:16Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* Differences from production device */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;The 920-0614-03 is seemingly a development/prototype iPod Nano 4G (or possibly iPod Touch 2G board?). It appeared on a bunch of eBay auctions around September 2023.&lt;br /&gt;
&lt;br /&gt;
== Specs ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;SoC&#039;&#039;&#039;: S5L8729&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Flash&#039;&#039;&#039;: Usually desoldered&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;DRAM&#039;&#039;&#039;: To be checked&lt;br /&gt;
&lt;br /&gt;
== UART ==&lt;br /&gt;
&lt;br /&gt;
The boards has at least two ways to access UART:&lt;br /&gt;
&lt;br /&gt;
# Over DE9 connector.&lt;br /&gt;
&lt;br /&gt;
# Over USB/Serial bridge.&lt;br /&gt;
&lt;br /&gt;
# Over 30-pin connector.&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;TODO&#039;&#039;&#039;: Figure out which serial is which, and document reanimating DE9/USB.&lt;br /&gt;
&lt;br /&gt;
== Power ==&lt;br /&gt;
&lt;br /&gt;
The board runs from either the 30-pin connector by itself (although it can sometimes be unstable) or from 5V over a DC power jack (which provides a 4v-ish supply which simulates the devices&#039; battery).&lt;br /&gt;
&lt;br /&gt;
== JTAG ==&lt;br /&gt;
&lt;br /&gt;
[[JTAG]] is available over the 30 pin connector, but is also seemingly locked out as on production devices.&lt;br /&gt;
&lt;br /&gt;
== Getting code to run ==&lt;br /&gt;
&lt;br /&gt;
[[wInd3x]] works on the device. On devices without Flash attempting to run the standard WTF causes a reset.&lt;br /&gt;
&lt;br /&gt;
== Differences from production device ==&lt;br /&gt;
&lt;br /&gt;
=== CHIPID ===&lt;br /&gt;
&lt;br /&gt;
Different CHIPIDL/H values are present in the CHIPID peripheral:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! SoC !! CHIPIDL (&amp;lt;code&amp;gt;0x3d100_0004&amp;lt;/code&amp;gt;) !! CHIPIDH (&amp;lt;code&amp;gt;0x3d100_0008&amp;lt;/code&amp;gt;)&lt;br /&gt;
|-&lt;br /&gt;
| Nano 4G || &amp;lt;code&amp;gt;19000011&amp;lt;/code&amp;gt; || &amp;lt;code&amp;gt;8720000f&amp;lt;/code&amp;gt;&lt;br /&gt;
|-&lt;br /&gt;
| 920-0614-03 || &amp;lt;code&amp;gt;11000001&amp;lt;/code&amp;gt; || &amp;lt;code&amp;gt;8720180f&amp;lt;/code&amp;gt;&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
Effects:&lt;br /&gt;
&lt;br /&gt;
# &amp;lt;code&amp;gt;CHIPIDL &amp;amp; 0x10 == 0&amp;lt;/code&amp;gt;: The BootROM accepts an additional top-level serial: 0x01 0xFB &#039;&#039;&#039;0x00&#039;&#039;&#039; 0xFB in addition to the standard 0x01 0xFB &#039;&#039;&#039;0x01&#039;&#039;&#039; 0xFB&lt;br /&gt;
# &amp;lt;code&amp;gt;CHIPIDL &amp;amp; (1 &amp;lt;&amp;lt; 27) == 1&amp;lt;/code&amp;gt;: The WTF&#039;s ChipID[2] function returns 3 instead of 2 in *second argument.&lt;br /&gt;
&lt;br /&gt;
== Pins ==&lt;br /&gt;
&lt;br /&gt;
As the board has clearly labeled and accessible GPIO pins / configuration straps, it&#039;s a good candidate to reverse engineer pin functionality as used in the production device.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! S5L8720 GPIO !! Function on board&lt;br /&gt;
|-&lt;br /&gt;
| 91 || &#039;DFU&#039; button&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22060</id>
		<title>920-0614-03</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22060"/>
		<updated>2023-10-27T15:26:03Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;The 920-0614-03 is seemingly a development/prototype iPod Nano 4G (or possibly iPod Touch 2G board?). It appeared on a bunch of eBay auctions around September 2023.&lt;br /&gt;
&lt;br /&gt;
== Specs ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;SoC&#039;&#039;&#039;: S5L8729&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Flash&#039;&#039;&#039;: Usually desoldered&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;DRAM&#039;&#039;&#039;: To be checked&lt;br /&gt;
&lt;br /&gt;
== UART ==&lt;br /&gt;
&lt;br /&gt;
The boards has at least two ways to access UART:&lt;br /&gt;
&lt;br /&gt;
# Over DE9 connector.&lt;br /&gt;
&lt;br /&gt;
# Over USB/Serial bridge.&lt;br /&gt;
&lt;br /&gt;
# Over 30-pin connector.&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;TODO&#039;&#039;&#039;: Figure out which serial is which, and document reanimating DE9/USB.&lt;br /&gt;
&lt;br /&gt;
== Power ==&lt;br /&gt;
&lt;br /&gt;
The board runs from either the 30-pin connector by itself (although it can sometimes be unstable) or from 5V over a DC power jack (which provides a 4v-ish supply which simulates the devices&#039; battery).&lt;br /&gt;
&lt;br /&gt;
== JTAG ==&lt;br /&gt;
&lt;br /&gt;
[[JTAG]] is available over the 30 pin connector, but is also seemingly locked out as on production devices.&lt;br /&gt;
&lt;br /&gt;
== Getting code to run ==&lt;br /&gt;
&lt;br /&gt;
[[wInd3x]] works on the device. On devices without Flash attempting to run the standard WTF causes a reset.&lt;br /&gt;
&lt;br /&gt;
== Differences from production device ==&lt;br /&gt;
&lt;br /&gt;
=== CHIPID ===&lt;br /&gt;
&lt;br /&gt;
Different CHIPIDL/H values are present in the CHIPID peripheral:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! SoC !! CHIPIDL (&amp;lt;code&amp;gt;0x3d100_0004&amp;lt;/code&amp;gt;) !! CHIPIDH (&amp;lt;code&amp;gt;0x3d100_0008&amp;lt;/code&amp;gt;)&lt;br /&gt;
|-&lt;br /&gt;
| Nano 4G || &amp;lt;code&amp;gt;19000011&amp;lt;/code&amp;gt; || &amp;lt;code&amp;gt;8720000f&amp;lt;/code&amp;gt;&lt;br /&gt;
|-&lt;br /&gt;
| 920-0614-03 || &amp;lt;code&amp;gt;11000001&amp;lt;/code&amp;gt; || &amp;lt;code&amp;gt;8720180f&amp;lt;/code&amp;gt;&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
Effects:&lt;br /&gt;
&lt;br /&gt;
# &amp;lt;code&amp;gt;CHIPIDL &amp;amp; 10 == 0&amp;lt;/code&amp;gt;: The BootROM accepts an additional top-level serial: 0x01 0xFB &#039;&#039;&#039;0x00&#039;&#039;&#039; 0xFB in addition to the standard 0x01 0xFB &#039;&#039;&#039;0x01&#039;&#039;&#039; 0xFB&lt;br /&gt;
&lt;br /&gt;
== Pins ==&lt;br /&gt;
&lt;br /&gt;
As the board has clearly labeled and accessible GPIO pins / configuration straps, it&#039;s a good candidate to reverse engineer pin functionality as used in the production device.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! S5L8720 GPIO !! Function on board&lt;br /&gt;
|-&lt;br /&gt;
| 91 || &#039;DFU&#039; button&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=RetailOS&amp;diff=22059</id>
		<title>RetailOS</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=RetailOS&amp;diff=22059"/>
		<updated>2023-10-22T13:38:13Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;The stock operating system running on non-iOS iPods. It runs everything from device drivers to the clickwheel user interface.&lt;br /&gt;
&lt;br /&gt;
== Naming ==&lt;br /&gt;
&lt;br /&gt;
The only &#039;official&#039; name seems to be &#039;retailOS&#039;, found in the [[Nano 3G]] WTF. It is also referred to as &#039;osos&#039; per the file name in the resource partition of the firmware bundle.&lt;br /&gt;
&lt;br /&gt;
== Architecture ==&lt;br /&gt;
&lt;br /&gt;
retailOS is a small, embedded, single-user, single-binary, real time operating system. With time it acquire more and more complex functionality, like PowerVR drivers and being able to load external applications (&#039;eApps&#039;) which are used for games.&lt;br /&gt;
&lt;br /&gt;
The core of the system is based on RTXC 3.2, with the end-user interface based on intellectual property from a company called Pixo. &amp;lt;ref&amp;gt;https://twitter.com/johnwhitley/status/1451952369248264201&amp;lt;/ref&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Security ==&lt;br /&gt;
&lt;br /&gt;
As evidenced by the success of the [[Notes vulnerability]], at least up to Nano 4G there was no kind of security hardening, and in fact all processes, including games, seem to be running in ARM system mode. This should make exploitation of newer retailOS bugs trivial.&lt;br /&gt;
&lt;br /&gt;
=== Boot chain ===&lt;br /&gt;
&lt;br /&gt;
retailOS is loaded by the second-stage bootloader (stored on NOR/NAND depending on the device generation), from NAND into DRAM.&lt;br /&gt;
&lt;br /&gt;
While other stages of the boot chain (eg. the bootloader, WTF mode in newer devices, the diagnostics tool) are based around EFI firmware volumes and an EFI runtime, retailOS is a single binary blob without any built-in modularity.&lt;br /&gt;
&lt;br /&gt;
=== eApp Signing ===&lt;br /&gt;
&lt;br /&gt;
Not yet documented fully. Each game seems to ship with a Manifest.plist.p7p which is a PKCS#7 signature for the main Manifest.plist.&lt;br /&gt;
&lt;br /&gt;
== Options ==&lt;br /&gt;
&lt;br /&gt;
We have found some &#039;secret&#039; options that can be set by creating specially named files. See [[RetailOS_Options|Options]].&lt;br /&gt;
&lt;br /&gt;
== Analysis / Memory Layout ==&lt;br /&gt;
&lt;br /&gt;
Loading RetailOS correctly into a decompiler/disassembler is tricky, as the contents of the IMG1 image are a binary blob which self-relocates to the correct places in memory.&lt;br /&gt;
&lt;br /&gt;
These are the memory segments within RetailOS that we know of (at least on Nano 5G):&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Name !! Marker !! Location in memory !! Description&lt;br /&gt;
|-&lt;br /&gt;
| sram.text || n/a || SRAM 0x22000000 || SRAM-resident code, most of RTXC lives here.&lt;br /&gt;
|-&lt;br /&gt;
| sram.bss || n/a || SRAM 0x22030000 || SRAM-resident zero data.&lt;br /&gt;
|-&lt;br /&gt;
| sram.data || n/a || SRAM 0x22030000 + sram_bss_size || SRAM-resident data.&lt;br /&gt;
|-&lt;br /&gt;
| dram.textdata || hibe || DRAM 0x08000000 || Combined .text and .data which lives in DRAM. Bulk of code lives here.&lt;br /&gt;
|-&lt;br /&gt;
| dram.frameworks || miscTBD || DRAM 0x08000000 + dram_textdata_size || &#039;Framework&#039; system of some kind, interfaces used by eApps.&lt;br /&gt;
|-&lt;br /&gt;
| dram.bss || n/a || DRAM 0x08000000 + dram_textdata_size + dram_frameworks_size || DRAM-resident zero data.&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
And here&#039;s how the segments are built up within the RetailOS binary blob:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Address !! Name !! Size&lt;br /&gt;
|-&lt;br /&gt;
| Start || sram.text || sram_text_size&lt;br /&gt;
|-&lt;br /&gt;
| || sram.bss || sram_bss_size&lt;br /&gt;
|-&lt;br /&gt;
| || sram.data || sram_data_size&lt;br /&gt;
|-&lt;br /&gt;
| || dram.text || dram_text_size&lt;br /&gt;
|-&lt;br /&gt;
| End || dram.frameworks || dram_frameworks_size&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
(yes, the firmware blob ships a sram.bss physically in the file)&lt;br /&gt;
&lt;br /&gt;
So the goal to be able to load the binary is to figure out the segment sizes and then load them into a decompiler/disassembler. &lt;br /&gt;
&lt;br /&gt;
Here, we&#039;ll show how to figure out the segment sizes for N5G. First, load the RetailOS body (without the header!) at 0x22000000 in a decompiler. We load it there (intead of into DRAM as it is done on the device) as the stub relocates to this address first by performing the SRAM .text/.data copies very early in the process, and the code is position independent for only a short time.&lt;br /&gt;
&lt;br /&gt;
Then, look at the start function (follow the reset vector):&lt;br /&gt;
&lt;br /&gt;
&amp;lt;pre&amp;gt;&lt;br /&gt;
void start(void) { // 0x2200505c&lt;br /&gt;
    offs = relocation_offset();&lt;br /&gt;
    /* ... peeks/pokes to bus matrix periph at 0x3ff00000 ... */&lt;br /&gt;
    if (offs != 0) {&lt;br /&gt;
        relocate(offs);&lt;br /&gt;
    }&lt;br /&gt;
    (*0x22000000) = 0xea000007;&lt;br /&gt;
    zero_bss();&lt;br /&gt;
}&lt;br /&gt;
&amp;lt;/pre&amp;gt;&lt;br /&gt;
&lt;br /&gt;
relocation_offset will return 0 if the stub is already at 0x22000000, so will return 0 for the way we&#039;ve loaded it. On a real device, this will be 0x22000000 - 0x08000000 ==&lt;br /&gt;
0x1a000000, as the real device loads RetailOS into DRAM first. Thus, relocate() will be called:&lt;br /&gt;
&lt;br /&gt;
&amp;lt;pre&amp;gt;&lt;br /&gt;
void relocate(int offs) { // 0x22005ec8&lt;br /&gt;
  int iVar1 = -offs;&lt;br /&gt;
  void *blob_start = iVar1 + 0x22000000;&lt;br /&gt;
  memmove(0x22000000, blob_start, 0xe27c); // copy sram.text&lt;br /&gt;
  memzero(0x22000000 + 0xe27c, 0xbc4); // zero out sram.bss within blob&lt;br /&gt;
  memmove(0x22030000, 0x22000000 + 0xe27c + iVar1, 0x20000); // copy sram.bss + sram.data&lt;br /&gt;
  jump_offset(offs);&lt;br /&gt;
  memmove(0x08000000, 0x22000000 + 0xe27c + 0x20000 + iVar1, 0x6c3768); // copy dram.textdata&lt;br /&gt;
  memmove(0x08000000 + 0x6c3768, iVar1 + 0x22000000 + 0xe27c + 0x20000 + 0x6c3768), 0xc40); // copy dram.frameworks&lt;br /&gt;
  start();&lt;br /&gt;
  return;&lt;br /&gt;
}&lt;br /&gt;
&amp;lt;/pre&amp;gt;&lt;br /&gt;
&lt;br /&gt;
The above listing shows reconstituted address calculations - in a plain decompilation, all the additions will of course be simplified to a single constant. But you should be able to figure out the following:&lt;br /&gt;
&lt;br /&gt;
# sram_text_size is 0xe27c&lt;br /&gt;
# sram_bss_size is 0xbc4&lt;br /&gt;
# sram_bss_size + sram_data_size is 0x20000&lt;br /&gt;
# dram_textdata_size is 0x6c3768&lt;br /&gt;
# dram_frameworks_size is 0xc40&lt;br /&gt;
&lt;br /&gt;
Then, in zero_bss we can find the size of dram.bss:&lt;br /&gt;
&lt;br /&gt;
&amp;lt;pre&amp;gt;&lt;br /&gt;
void zero_bss(void) { // 0x22005fec&lt;br /&gt;
    memzero(0x2200e27c, 0xbc4); // zero out sram.bss&lt;br /&gt;
    // inlined memzero:&lt;br /&gt;
    void *start = 0x08000000 + 0x6c3768 + 0xc40;&lt;br /&gt;
    int size = 0x790a84;&lt;br /&gt;
    // ...&lt;br /&gt;
}&lt;br /&gt;
&amp;lt;/pre&amp;gt;&lt;br /&gt;
&lt;br /&gt;
From which we can figure out that the dram.bss segment size is 0x790a84.&lt;br /&gt;
&lt;br /&gt;
Thus we can load the file like so (combining sram.bss and sram.data) into a &#039;clean&#039; decompiler/disassembler session:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Name !! Memory Address !! File Offset&lt;br /&gt;
|-&lt;br /&gt;
| sram.text || 0x22000000 || 0x00000000&lt;br /&gt;
|-&lt;br /&gt;
| sram.bssdata || 0x22030000 || 0x0000e27c&lt;br /&gt;
|-&lt;br /&gt;
| dram.textdata || 0x08000000 || 0x0002e27c (0xe27c + 0x20000)&lt;br /&gt;
|-&lt;br /&gt;
| dram.frameworks || 0x086c3768 || 0x006f19e4 (0xe27c + 0x20000 + 0x6c3768)&lt;br /&gt;
|-&lt;br /&gt;
| dram.bss || 0x086c43a || n/a (0x790a84 zeroes)&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
Writing an automated converter into ELF from arbitrary RetailOS blobs is an exercise left to the reader.&lt;br /&gt;
&lt;br /&gt;
== RTXC == &lt;br /&gt;
&lt;br /&gt;
=== Documentation ===&lt;br /&gt;
&lt;br /&gt;
This seems to be the best public document available about RTXC 3.2: [https://web.archive.org/web/20230218212424/https://datasheet.datasheetarchive.com/originals/library/Datasheets-AS2/DSAAXSA0003458.pdf DSAAXSA0003458.pdf]. It contains example code for most services, but unfortunately is still missing any structure definitions.&lt;br /&gt;
&lt;br /&gt;
There&#039;s also some training slides available: [https://ia801800.us.archive.org/26/items/manualzilla-id-5752851/5752851.pdf 5752851.pdf]. These introduce the general architecture and concept of RTXC 3.2. &lt;br /&gt;
&lt;br /&gt;
=== Services / Syscalls ===&lt;br /&gt;
&lt;br /&gt;
While RTXC documentation speaks mostly of &#039;kernel services&#039; (which are defined as C function signatures/symbols), we like to talk about &#039;syscalls&#039; and &#039;syscall numbers&#039; when reverse engineering retailOS. All service functions go through a central dispatch function and that&#039;s the easiest point to start reverse engineering the kernel service interface.&lt;br /&gt;
&lt;br /&gt;
The dispatcher receives a saved caller state which contains a pointer to a serialized syscall request in its saved R0. The syscall request is a trivial structure containing a syscall number and arguments. The dispatcher is executed with interrupts enabled (and thus is non-preemptable) and performs actual work on kernel structures. There is no privilege-granting &#039;gate&#039; mechanism, all caller code is just as privileged as the kernel code.&lt;br /&gt;
&lt;br /&gt;
Service functions in turn prepare the syscall request structure (including syscall number), and then call an intermediary state saving function which then calls the dispatcher after disabling interrupts. Some syscall numbers are used by multiple service functions, with some extra arguments in the request being used to decide on the behaviour of the service call (eg. blocking/nonblocking).&lt;br /&gt;
&lt;br /&gt;
The following table comes from cross-referencing retailOS, publicly available RTXC PDFs and publicly availble RTXC binaries with debug symbols.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Name !! Number !! Description&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_pend(SEMA sema)&amp;lt;/code&amp;gt; || 0x03 || Semaphore DONE -&amp;gt; PENDING.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;RTXCMSG *KS_receive(MBOX mailbox, TASK  task)&amp;lt;/code&amp;gt; || 0x05 || Receive from mailbox.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;KSRC KS_enqueue[w](QUEUE queue, void *entry)&amp;lt;/code&amp;gt; || 0x0c || Push into FIFO (and block if full with &#039;w&#039; variant).&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_dequeue[w](QUEUE queue, void *dest)&amp;lt;/code&amp;gt; || 0x0d || Pop from FIFO (and block if empty with &#039;w&#039; variant).&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;KSRC KS_lock(RESOURCE resource)&amp;lt;/code&amp;gt; || 0x0e || Lock a resource.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;KSRC KS_lockt(RESOURCE resource, TICKS timoeut)&amp;lt;/code&amp;gt; || 0x0e || Lock a resource with timeout.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;KSRC KS_unlock(RESOURCE resource)&amp;lt;/code&amp;gt; || 0x0f || Unlock an owned resource.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;CLKBLK *KS_alloc_timer(void)&amp;lt;/code&amp;gt; || 0x10 || Allocate next free timer from pool.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;CLKBLK *KS_start_timer(CLKBLK *timer, TICKS initial_period, TICKS cycle_time, SEMA sema)&amp;lt;/code&amp;gt; || 0x12 || Start timer.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;KSRC KS_stop_timer(CLKBLK *timer)&amp;lt;/code&amp;gt; || 0x13 || Stop timer.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_delay(TASK task, TICKS period)&amp;lt;/code&amp;gt; || 0x14 || Block specified task for a period of time.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_execute(TASK task)&amp;lt;/code&amp;gt; || 0x15 || Start a task from its beginning address.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;KSRC KS_deftask(TASK task, PRIORITY priority, char *stack, size_t stacksize, void (*entry)(void))&amp;lt;/code&amp;gt; || 0x16 || Define the attributes of an inactive task.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;TASK KS_alloc_task(void)&amp;lt;/code&amp;gt; || 0x17 || Allocate the next available Task Control Block from the pool of free TCBs. &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_terminate(TASK task)&amp;lt;/code&amp;gt; || 0x18 || Stop a task by setting it to INACTIVE.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_suspend(TASK task)&amp;lt;/code&amp;gt; || 0x19 || Suspend a task until resumed or re-executed.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_defpriority(TASK task, PRIORITY priority)&amp;lt;/code&amp;gt; || 0x1b || Define or set priority of task.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_yield(void)&amp;lt;/code&amp;gt; || 0x1c || Voluntary release of control to any other task of the same priority.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;SEMA KS_waitm(SEMA *semalist)&amp;lt;/code&amp;gt; || 0x22 || Wait on multiple semaphores.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;time_t KS_inqtime(void)&amp;lt;/code&amp;gt; || 0x24 || Get current time-of-day.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_deftime(time_t time)&amp;lt;/code&amp;gt; || 0x25 || Set current time-of-day.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;TASK KS_inqres(RESOURCE resource)&amp;lt;/code&amp;gt; || 0x26 || Get owner of resource.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;KSRC KS_defres(RESOURCE resource, RESATTR condition)&amp;lt;/code&amp;gt; || 0x27 || Define priority inversion on resource.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void *KS_inqtask_arg(TASK task)&amp;lt;/code&amp;gt; || 0x28 || Get environment arguments of task.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_deftask_arg(TASK task, void *arg)&amp;lt;/code&amp;gt; || 0x29 || Set environment arguments for task.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;KSRC KS_defqueue(QUEUE queue, size_t width, int depth, void *body, int currsize)&amp;lt;/code&amp;gt; || 0x2e || Define queue.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;int KS_user(int (*func) (void *), void *arg)&amp;lt;/code&amp;gt; || 0x30 || Execute function as if it were kernel service.&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
The RTXC memory allocation facilities (&amp;lt;code&amp;gt;KS_alloc/free/create_part/alloc_part/defpart/free_part&amp;lt;/code&amp;gt;) are &#039;&#039;not&#039;&#039; used by retailOS and not built into the service dispatcher, at least on [[Nano 5G]].&lt;br /&gt;
&lt;br /&gt;
=== Semaphores ===&lt;br /&gt;
&lt;br /&gt;
The following semaphores are defined in the [[Nano 3G]] retailOS:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Number !! Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x01 || &amp;lt;code&amp;gt;S_FW_PWR_CHANGE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x02 || &amp;lt;code&amp;gt;S_BAT_PWR_CHANGE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x03 || &amp;lt;code&amp;gt;S_USB_PWR_CHANGE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x04 || &amp;lt;code&amp;gt;S_CNA_CHANGE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x05 || &amp;lt;code&amp;gt;S_WHEEL_CHANGE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x06 || &amp;lt;code&amp;gt;S_DISKMGRQ&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x07 || &amp;lt;code&amp;gt;S_TOPPLUG_SWITCH&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x08 || &amp;lt;code&amp;gt;S_RTCTIMERMGR&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x09 || &amp;lt;code&amp;gt;S_ALARM_01&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x0a || &amp;lt;code&amp;gt;S_ALARM_02&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x0b || &amp;lt;code&amp;gt;S_ALARM_03&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x0c || &amp;lt;code&amp;gt;S_WATCHDOG&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x0d || &amp;lt;code&amp;gt;S_CPUMGRQ&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x0e || &amp;lt;code&amp;gt;S_PCFPOWERMGR&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x0f || &amp;lt;code&amp;gt;S_POWER_STATE_AC&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x10 || &amp;lt;code&amp;gt;S_CGR_STATE_TMR&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x11 || &amp;lt;code&amp;gt;S_DEEPSLEEP&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x12 || &amp;lt;code&amp;gt;S_ALARM_DONE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x13 || &amp;lt;code&amp;gt;S_PIEZOMGR&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x14 || &amp;lt;code&amp;gt;S_PIEZOMGRSNDR&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x15 || &amp;lt;code&amp;gt;S_PIEZODONE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x16 || &amp;lt;code&amp;gt;S_ACCPOWER&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x17 || &amp;lt;code&amp;gt;S_ACC_REINIT&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x18 || &amp;lt;code&amp;gt;S_TOPPLUGSENSER&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x19 || &amp;lt;code&amp;gt;S_TOPPLUGCHANGE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x1a || &amp;lt;code&amp;gt;S_BTMCONNECT&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x1b || &amp;lt;code&amp;gt;S_BTMPLUGCHANGE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x1c || &amp;lt;code&amp;gt;S_BTMREVERIFY&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x1d || &amp;lt;code&amp;gt;S_BTMREVERTIMED&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x1e || &amp;lt;code&amp;gt;S_BTMVERCOMP&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x1f || &amp;lt;code&amp;gt;S_TOPACCPKTRCVD&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x20 || &amp;lt;code&amp;gt;S_BTMACCPKTRCVD&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x21 || &amp;lt;code&amp;gt;S_SERIALIDRCVD&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x22 || &amp;lt;code&amp;gt;S_UARTATXEMPTY&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x23 || &amp;lt;code&amp;gt;S_UARTBTXEMPTY&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x24 || &amp;lt;code&amp;gt;S_HDDSCANCOMP&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x25 || &amp;lt;code&amp;gt;S_BL_ON&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x26 || &amp;lt;code&amp;gt;S_BL_OFF&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x27 || &amp;lt;code&amp;gt;S_BL_RAMPDOWN&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x28 || &amp;lt;code&amp;gt;S_BL_RAMPUP&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x29 || &amp;lt;code&amp;gt;S_BL_TIMESUP&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x2a || &amp;lt;code&amp;gt;S_BATT_TIMESUP&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x2b || &amp;lt;code&amp;gt;S_BATT_AC_PWR&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x2c || &amp;lt;code&amp;gt;S_BATT_TMR_RST&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x2d || &amp;lt;code&amp;gt;S_GRAPHMGR&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x2e || &amp;lt;code&amp;gt;S_VBL&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x2f || &amp;lt;code&amp;gt;S_DTVRECOVERY&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x30 || &amp;lt;code&amp;gt;S_CM_HEADPHONE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x31 || &amp;lt;code&amp;gt;S_CM_EXTPOWER&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x32 || &amp;lt;code&amp;gt;S_CM_ACCATTACHED&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x33 || &amp;lt;code&amp;gt;S_CM_DAC_SETUP&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x34 || &amp;lt;code&amp;gt;S_ATAWRKLPRDY&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x35 || &amp;lt;code&amp;gt;S_RTXCBUG&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x36 || &amp;lt;code&amp;gt;S_BLOCKDEVICE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x37 || &amp;lt;code&amp;gt;S_BLOCKDEVICEQ&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x38 || &amp;lt;code&amp;gt;S_DISPLAY&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x39 || &amp;lt;code&amp;gt;S_ARB_READY&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x3a || &amp;lt;code&amp;gt;S_I2C_DONE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x3b || &amp;lt;code&amp;gt;S_VSYNC&amp;lt;/code&amp;gt; || &lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
There are three more semaphores (0x3c, 0x3d, 0x3e) that have no name defined and are likely unused. Anything 0x3f and up is a &#039;Dynamic&#039; semaphore defined at runtime (which we haven&#039;t reversed yet).&lt;br /&gt;
&lt;br /&gt;
=== Queues ===&lt;br /&gt;
&lt;br /&gt;
The following queues are defined in the [[Nano 3G]] retailOS:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Number !! Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x01 || PIXORESQ ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x02 || PIXOSEMAQ ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x03 || POSIXRESQ ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x04 || POSIXSEMAQ ||&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
=== Mailboxes ===&lt;br /&gt;
&lt;br /&gt;
The following mailboxes are defined in the [[Nano 3G]] retailOS:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Number !! Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x01 || M_DISKMGR ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x02 || M_PIEZOMGR ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x03 || M_GRAPHMGR ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x04 || M_BLOCKDEVICE ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x05 || M_DISPLAY ||&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
=== Resources ===&lt;br /&gt;
&lt;br /&gt;
The following lockable resources are defined in the [[Nano 3G]] retailOS:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Number !! Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x01 || GPIO_REG_WRITE ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x02 || GPIO_INT_INIT ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x03 || RTC_TIME_ADJUST ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x04 || RTC_ALARM_ADJUST ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x05 || I2C_MASTER ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x06 || USB_GRANT ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x07 || USB_RESP_INIT ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x08 || USB_RESPONDER ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x09 || DISKPWRMGRSEND ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x0a || PIEZOMGRSEND ||&lt;br /&gt;
|- &lt;br /&gt;
| 0x0b || SERIALVERIFIER ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x0c || RESISTORVERIFIER ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x0d || FW_IRAM ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x0e || ACCPOWER ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x0f || UARTA ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x10 || UARGB ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x11 || PMU_LOCK ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x12 || ADC_LOCK ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x13 || DTV_ENC_INIT ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x14 || BACKLIGHT ||&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
== External links ==&lt;br /&gt;
&lt;br /&gt;
* [https://web.archive.org/web/19990220054659/http://www.rtxc.com/Products/RTXC/Services.htm RTXC Kernel Services (1999)]&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22058</id>
		<title>920-0614-03</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22058"/>
		<updated>2023-10-18T22:25:35Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;The 920-0614-03 is seemingly a development/prototype iPod Nano 4G (or possibly iPod Touch 2G board?). It appeared on a bunch of eBay auctions around September 2023.&lt;br /&gt;
&lt;br /&gt;
== Specs ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;SoC&#039;&#039;&#039;: S5L8729&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Flash&#039;&#039;&#039;: Usually desoldered&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;DRAM&#039;&#039;&#039;: To be checked&lt;br /&gt;
&lt;br /&gt;
== UART ==&lt;br /&gt;
&lt;br /&gt;
The boards has at least two ways to access UART:&lt;br /&gt;
&lt;br /&gt;
# Over DE9 connector.&lt;br /&gt;
&lt;br /&gt;
# Over USB/Serial bridge.&lt;br /&gt;
&lt;br /&gt;
# Over 30-pin connector.&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;TODO&#039;&#039;&#039;: Figure out which serial is which, and document reanimating DE9/USB.&lt;br /&gt;
&lt;br /&gt;
== Power ==&lt;br /&gt;
&lt;br /&gt;
The board runs from either the 30-pin connector by itself (although it can sometimes be unstable) or from 5V over a DC power jack (which provides a 4v-ish supply which simulates the devices&#039; battery).&lt;br /&gt;
&lt;br /&gt;
== JTAG ==&lt;br /&gt;
&lt;br /&gt;
[[JTAG]] is available over the 30 pin connector, but is also seemingly locked out as on production devices.&lt;br /&gt;
&lt;br /&gt;
== Getting code to run ==&lt;br /&gt;
&lt;br /&gt;
[[wInd3x]] works on the device. On devices without Flash attempting to run the standard WTF causes a reset.&lt;br /&gt;
&lt;br /&gt;
== Differences from production device ==&lt;br /&gt;
&lt;br /&gt;
So far, it seems like the SoC present on the board is no different from production SoCs.&lt;br /&gt;
&lt;br /&gt;
=== CHIPID ===&lt;br /&gt;
&lt;br /&gt;
Seems like a perfectly standard S5L8720:&lt;br /&gt;
&lt;br /&gt;
&amp;lt;pre&amp;gt;&lt;br /&gt;
3d100000: 0100 0000 0100 0011 0f18 2087 104f 6d76  .......... ..Omv&lt;br /&gt;
3d100010: d700 0000 0300 0000 0000 0000 0000 0000  ................&lt;br /&gt;
&amp;lt;/pre&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Pins ==&lt;br /&gt;
&lt;br /&gt;
As the board has clearly labeled and accessible GPIO pins / configuration straps, it&#039;s a good candidate to reverse engineer pin functionality as used in the production device.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! S5L8720 GPIO !! Function on board&lt;br /&gt;
|-&lt;br /&gt;
| 91 || &#039;DFU&#039; button&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22057</id>
		<title>920-0614-03</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=920-0614-03&amp;diff=22057"/>
		<updated>2023-10-18T22:23:27Z</updated>

		<summary type="html">&lt;p&gt;Q3k: Created page with &amp;quot;The 920-0614-03 is seemingly a development/prototype iPod Nano 4G (or possibly iPod Touch 2G board?). It appeared on a bunch of eBay auctions around September 2023.  == Specs...&amp;quot;&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;The 920-0614-03 is seemingly a development/prototype iPod Nano 4G (or possibly iPod Touch 2G board?). It appeared on a bunch of eBay auctions around September 2023.&lt;br /&gt;
&lt;br /&gt;
== Specs ==&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;SoC&#039;&#039;&#039;: S5L8729&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Flash&#039;&#039;&#039;: Usually desoldered&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;DRAM&#039;&#039;&#039;: To be checked&lt;br /&gt;
&lt;br /&gt;
== UART ==&lt;br /&gt;
&lt;br /&gt;
The boards has at least two ways to access UART:&lt;br /&gt;
&lt;br /&gt;
# Over DE9 connector.&lt;br /&gt;
&lt;br /&gt;
# Over USB/Serial bridge.&lt;br /&gt;
&lt;br /&gt;
# Over 30-pin connector.&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;TODO&#039;&#039;&#039;: Figure out which serial is which, and document reanimating DE9/USB.&lt;br /&gt;
&lt;br /&gt;
== Power ==&lt;br /&gt;
&lt;br /&gt;
The board runs from either the 30-pin connector by itself (although it can sometimes be unstable) or from 5V over a DC power jack (which provides a 4v-ish supply which simulates the devices&#039; battery).&lt;br /&gt;
&lt;br /&gt;
== JTAG ==&lt;br /&gt;
&lt;br /&gt;
[[JTAG]] is available over the 30 pin connector, but is also seemingly locked out as on production devices.&lt;br /&gt;
&lt;br /&gt;
== Getting code to run ==&lt;br /&gt;
&lt;br /&gt;
[[wInd3x]] works on the device. On devices without Flash attempting to run the standard WTF causes a reset.&lt;br /&gt;
&lt;br /&gt;
== Differences from production device ==&lt;br /&gt;
&lt;br /&gt;
So far, it seems like the SoC present on the board is no different from production SoCs.&lt;br /&gt;
&lt;br /&gt;
== Pins ==&lt;br /&gt;
&lt;br /&gt;
As the board has clearly labeled and accessible GPIO pins / configuration straps, it&#039;s a good candidate to reverse engineer pin functionality as used in the production device.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! S5L8720 GPIO !! Function on board&lt;br /&gt;
|-&lt;br /&gt;
| 91 || &#039;DFU&#039; button&lt;br /&gt;
|}&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=FMSS&amp;diff=22051</id>
		<title>FMSS</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=FMSS&amp;diff=22051"/>
		<updated>2023-10-11T00:57:44Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* CS (Code Sequencer) */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;FMSS is seemingly the name of the flash memory controller on the S5L8702, S5L8710, S5L8720 and S5L8730.&lt;br /&gt;
&lt;br /&gt;
There is no publicly available information about it, and the following has been gathered from reverse engineering [[RetailOS]] and iOS builds for the S5L8720 (iPod touch). A very similar controller is present in the S5L8700X datasheet.&lt;br /&gt;
&lt;br /&gt;
== Subsystems ==&lt;br /&gt;
&lt;br /&gt;
=== FMC (Flash Memory Controller) ===&lt;br /&gt;
&lt;br /&gt;
This is the component responsible for the actual bus transfers on the NAND bus.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Offset !! Register Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x000 || FMCTRL0 || General control register.&lt;br /&gt;
* Bit 0: Enable&lt;br /&gt;
* Bits [1..8]: CE/Bank number&lt;br /&gt;
* Bit 10: DMA enable?&lt;br /&gt;
* Bits [12..14]: Hold clocks&lt;br /&gt;
* Bits [16..18]: Setup clocks&lt;br /&gt;
* Bits [28..30]: EDO clocks&lt;br /&gt;
|-&lt;br /&gt;
| 0x004 || FMCTRL1 || Transfer control register.&lt;br /&gt;
* Bit 0: Start address transfer.&lt;br /&gt;
* Bit 1: Start read transfer.&lt;br /&gt;
* Bit 2: Start write transfer.&lt;br /&gt;
* Bit 4: ???&lt;br /&gt;
* Bit 5: Clear ???&lt;br /&gt;
* Bit 6: Clear write FIFO&lt;br /&gt;
* Bit 7: Clear read FIFO&lt;br /&gt;
|-&lt;br /&gt;
| 0x008 || FMCMD || NAND command number. Eg. 0x90: read NAND ID. Documented in JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x00C || FMADDR0 || Lower bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x010 || FMADDR1 || Higher bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x02C || FMANUM || Number of bytes to transfer during address transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x030 || FMDNUM || Number of bytes to transfer during data transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x048 || FMSTAT || Controller status.&lt;br /&gt;
* Bit 0: flash busy?&lt;br /&gt;
* Bit 1: command done. Write to clear.&lt;br /&gt;
* Bit 2: address done. Write to clear.&lt;br /&gt;
* Bit 3: transfer done. Write to clear.&lt;br /&gt;
* Bit 23: flash has become busy? Write to clear.&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
To be documented fully.&lt;br /&gt;
&lt;br /&gt;
=== ECC (Error Correction Code) ===&lt;br /&gt;
&lt;br /&gt;
To be documented.&lt;br /&gt;
&lt;br /&gt;
=== CS (Code Sequencer) ===&lt;br /&gt;
&lt;br /&gt;
A little custom core that executes a custom bytecode. 9 32-bit general purpose registers. Controlled by the host CPU. It has access to the host memory and the rest of the FMSS peripherals, and operates by performing accesses to the FMC and ECC subsystems.&lt;br /&gt;
&lt;br /&gt;
The bytecode is documented at [https://github.com/lemonjesus/S5L8702-FMISS-Tools lemonjesus/S5L8702-FMISS-Tools].&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Offset !! Register Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0xC04 || CS_IP || Sequencer&#039;s instruction pointer.&lt;br /&gt;
|-&lt;br /&gt;
| 0xC08 || CS_STATUS ||&lt;br /&gt;
|-&lt;br /&gt;
| 0xC0C || CS_IRQ ||&lt;br /&gt;
|-&lt;br /&gt;
| 0xC60 || CS_BUF_RST ||&lt;br /&gt;
|-&lt;br /&gt;
| 0xC64 || CS_BUF_RST_OK ||&lt;br /&gt;
|-&lt;br /&gt;
| 0xC6C || CS_BUF_START || &lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
== Other devices / SoCs ==&lt;br /&gt;
&lt;br /&gt;
=== S5L8700X (non-Apple) and S5L8900 ===&lt;br /&gt;
&lt;br /&gt;
A similar controller is present, called simply the FMC. It has no code sequencing functionality.&lt;br /&gt;
&lt;br /&gt;
On the S5L8900 the built-in CalmRISC16e core that&#039;s part of the ADM (Audio DSP Module) is used as a code sequencer in iOS.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=FMSS&amp;diff=22050</id>
		<title>FMSS</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=FMSS&amp;diff=22050"/>
		<updated>2023-10-11T00:57:36Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* CS (Code Sequencer) */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;FMSS is seemingly the name of the flash memory controller on the S5L8702, S5L8710, S5L8720 and S5L8730.&lt;br /&gt;
&lt;br /&gt;
There is no publicly available information about it, and the following has been gathered from reverse engineering [[RetailOS]] and iOS builds for the S5L8720 (iPod touch). A very similar controller is present in the S5L8700X datasheet.&lt;br /&gt;
&lt;br /&gt;
== Subsystems ==&lt;br /&gt;
&lt;br /&gt;
=== FMC (Flash Memory Controller) ===&lt;br /&gt;
&lt;br /&gt;
This is the component responsible for the actual bus transfers on the NAND bus.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Offset !! Register Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x000 || FMCTRL0 || General control register.&lt;br /&gt;
* Bit 0: Enable&lt;br /&gt;
* Bits [1..8]: CE/Bank number&lt;br /&gt;
* Bit 10: DMA enable?&lt;br /&gt;
* Bits [12..14]: Hold clocks&lt;br /&gt;
* Bits [16..18]: Setup clocks&lt;br /&gt;
* Bits [28..30]: EDO clocks&lt;br /&gt;
|-&lt;br /&gt;
| 0x004 || FMCTRL1 || Transfer control register.&lt;br /&gt;
* Bit 0: Start address transfer.&lt;br /&gt;
* Bit 1: Start read transfer.&lt;br /&gt;
* Bit 2: Start write transfer.&lt;br /&gt;
* Bit 4: ???&lt;br /&gt;
* Bit 5: Clear ???&lt;br /&gt;
* Bit 6: Clear write FIFO&lt;br /&gt;
* Bit 7: Clear read FIFO&lt;br /&gt;
|-&lt;br /&gt;
| 0x008 || FMCMD || NAND command number. Eg. 0x90: read NAND ID. Documented in JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x00C || FMADDR0 || Lower bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x010 || FMADDR1 || Higher bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x02C || FMANUM || Number of bytes to transfer during address transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x030 || FMDNUM || Number of bytes to transfer during data transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x048 || FMSTAT || Controller status.&lt;br /&gt;
* Bit 0: flash busy?&lt;br /&gt;
* Bit 1: command done. Write to clear.&lt;br /&gt;
* Bit 2: address done. Write to clear.&lt;br /&gt;
* Bit 3: transfer done. Write to clear.&lt;br /&gt;
* Bit 23: flash has become busy? Write to clear.&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
To be documented fully.&lt;br /&gt;
&lt;br /&gt;
=== ECC (Error Correction Code) ===&lt;br /&gt;
&lt;br /&gt;
To be documented.&lt;br /&gt;
&lt;br /&gt;
=== CS (Code Sequencer) ===&lt;br /&gt;
&lt;br /&gt;
A little custom core that executes a custom bytecode. 9 32-bit general purpose registers. Controlled by the host CPU. It has access to the host memory and the rest of the FMSS peripherals, and operates by performing accesses to the FMC and ECC subsystems.&lt;br /&gt;
&lt;br /&gt;
The bytecode is documented at [https://github.com/lemonjesus/S5L8702-FMISS-Tools lemonjesus/S5L8702-FMISS-Tools].&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Offset !! Register Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
|-&lt;br /&gt;
| 0xC04 || CS_IP || Sequencer&#039;s instruction pointer.&lt;br /&gt;
| 0xC08 || CS_STATUS ||&lt;br /&gt;
|-&lt;br /&gt;
| 0xC0C || CS_IRQ ||&lt;br /&gt;
|-&lt;br /&gt;
| 0xC60 || CS_BUF_RST ||&lt;br /&gt;
|-&lt;br /&gt;
| 0xC64 || CS_BUF_RST_OK ||&lt;br /&gt;
|-&lt;br /&gt;
| 0xC6C || CS_BUF_START || &lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
== Other devices / SoCs ==&lt;br /&gt;
&lt;br /&gt;
=== S5L8700X (non-Apple) and S5L8900 ===&lt;br /&gt;
&lt;br /&gt;
A similar controller is present, called simply the FMC. It has no code sequencing functionality.&lt;br /&gt;
&lt;br /&gt;
On the S5L8900 the built-in CalmRISC16e core that&#039;s part of the ADM (Audio DSP Module) is used as a code sequencer in iOS.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=FMSS&amp;diff=22049</id>
		<title>FMSS</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=FMSS&amp;diff=22049"/>
		<updated>2023-10-11T00:54:16Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* CS (Code Sequencer) */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;FMSS is seemingly the name of the flash memory controller on the S5L8702, S5L8710, S5L8720 and S5L8730.&lt;br /&gt;
&lt;br /&gt;
There is no publicly available information about it, and the following has been gathered from reverse engineering [[RetailOS]] and iOS builds for the S5L8720 (iPod touch). A very similar controller is present in the S5L8700X datasheet.&lt;br /&gt;
&lt;br /&gt;
== Subsystems ==&lt;br /&gt;
&lt;br /&gt;
=== FMC (Flash Memory Controller) ===&lt;br /&gt;
&lt;br /&gt;
This is the component responsible for the actual bus transfers on the NAND bus.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Offset !! Register Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x000 || FMCTRL0 || General control register.&lt;br /&gt;
* Bit 0: Enable&lt;br /&gt;
* Bits [1..8]: CE/Bank number&lt;br /&gt;
* Bit 10: DMA enable?&lt;br /&gt;
* Bits [12..14]: Hold clocks&lt;br /&gt;
* Bits [16..18]: Setup clocks&lt;br /&gt;
* Bits [28..30]: EDO clocks&lt;br /&gt;
|-&lt;br /&gt;
| 0x004 || FMCTRL1 || Transfer control register.&lt;br /&gt;
* Bit 0: Start address transfer.&lt;br /&gt;
* Bit 1: Start read transfer.&lt;br /&gt;
* Bit 2: Start write transfer.&lt;br /&gt;
* Bit 4: ???&lt;br /&gt;
* Bit 5: Clear ???&lt;br /&gt;
* Bit 6: Clear write FIFO&lt;br /&gt;
* Bit 7: Clear read FIFO&lt;br /&gt;
|-&lt;br /&gt;
| 0x008 || FMCMD || NAND command number. Eg. 0x90: read NAND ID. Documented in JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x00C || FMADDR0 || Lower bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x010 || FMADDR1 || Higher bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x02C || FMANUM || Number of bytes to transfer during address transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x030 || FMDNUM || Number of bytes to transfer during data transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x048 || FMSTAT || Controller status.&lt;br /&gt;
* Bit 0: flash busy?&lt;br /&gt;
* Bit 1: command done. Write to clear.&lt;br /&gt;
* Bit 2: address done. Write to clear.&lt;br /&gt;
* Bit 3: transfer done. Write to clear.&lt;br /&gt;
* Bit 23: flash has become busy? Write to clear.&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
To be documented fully.&lt;br /&gt;
&lt;br /&gt;
=== ECC (Error Correction Code) ===&lt;br /&gt;
&lt;br /&gt;
To be documented.&lt;br /&gt;
&lt;br /&gt;
=== CS (Code Sequencer) ===&lt;br /&gt;
&lt;br /&gt;
A little custom core that executes a custom bytecode. 9 32-bit general purpose registers. Controlled by the host CPU. It has access to the host memory and the rest of the FMSS peripherals, and operates by performing accesses to the FMC and ECC subsystems.&lt;br /&gt;
&lt;br /&gt;
The bytecode is documented at [https://github.com/lemonjesus/S5L8702-FMISS-Tools lemonjesus/S5L8702-FMISS-Tools].&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Offset !! Register Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0xC08 || CS_STATUS ||&lt;br /&gt;
|-&lt;br /&gt;
| 0xC0C || CS_IRQ ||&lt;br /&gt;
|-&lt;br /&gt;
| 0xC60 || CS_BUF_RST ||&lt;br /&gt;
|-&lt;br /&gt;
| 0xC64 || CS_BUF_RST_OK ||&lt;br /&gt;
|-&lt;br /&gt;
| 0xC6C || CS_BUF_START || &lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
== Other devices / SoCs ==&lt;br /&gt;
&lt;br /&gt;
=== S5L8700X (non-Apple) and S5L8900 ===&lt;br /&gt;
&lt;br /&gt;
A similar controller is present, called simply the FMC. It has no code sequencing functionality.&lt;br /&gt;
&lt;br /&gt;
On the S5L8900 the built-in CalmRISC16e core that&#039;s part of the ADM (Audio DSP Module) is used as a code sequencer in iOS.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=FMSS&amp;diff=22048</id>
		<title>FMSS</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=FMSS&amp;diff=22048"/>
		<updated>2023-10-11T00:53:19Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;FMSS is seemingly the name of the flash memory controller on the S5L8702, S5L8710, S5L8720 and S5L8730.&lt;br /&gt;
&lt;br /&gt;
There is no publicly available information about it, and the following has been gathered from reverse engineering [[RetailOS]] and iOS builds for the S5L8720 (iPod touch). A very similar controller is present in the S5L8700X datasheet.&lt;br /&gt;
&lt;br /&gt;
== Subsystems ==&lt;br /&gt;
&lt;br /&gt;
=== FMC (Flash Memory Controller) ===&lt;br /&gt;
&lt;br /&gt;
This is the component responsible for the actual bus transfers on the NAND bus.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Offset !! Register Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x000 || FMCTRL0 || General control register.&lt;br /&gt;
* Bit 0: Enable&lt;br /&gt;
* Bits [1..8]: CE/Bank number&lt;br /&gt;
* Bit 10: DMA enable?&lt;br /&gt;
* Bits [12..14]: Hold clocks&lt;br /&gt;
* Bits [16..18]: Setup clocks&lt;br /&gt;
* Bits [28..30]: EDO clocks&lt;br /&gt;
|-&lt;br /&gt;
| 0x004 || FMCTRL1 || Transfer control register.&lt;br /&gt;
* Bit 0: Start address transfer.&lt;br /&gt;
* Bit 1: Start read transfer.&lt;br /&gt;
* Bit 2: Start write transfer.&lt;br /&gt;
* Bit 4: ???&lt;br /&gt;
* Bit 5: Clear ???&lt;br /&gt;
* Bit 6: Clear write FIFO&lt;br /&gt;
* Bit 7: Clear read FIFO&lt;br /&gt;
|-&lt;br /&gt;
| 0x008 || FMCMD || NAND command number. Eg. 0x90: read NAND ID. Documented in JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x00C || FMADDR0 || Lower bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x010 || FMADDR1 || Higher bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x02C || FMANUM || Number of bytes to transfer during address transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x030 || FMDNUM || Number of bytes to transfer during data transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x048 || FMSTAT || Controller status.&lt;br /&gt;
* Bit 0: flash busy?&lt;br /&gt;
* Bit 1: command done. Write to clear.&lt;br /&gt;
* Bit 2: address done. Write to clear.&lt;br /&gt;
* Bit 3: transfer done. Write to clear.&lt;br /&gt;
* Bit 23: flash has become busy? Write to clear.&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
To be documented fully.&lt;br /&gt;
&lt;br /&gt;
=== ECC (Error Correction Code) ===&lt;br /&gt;
&lt;br /&gt;
To be documented.&lt;br /&gt;
&lt;br /&gt;
=== CS (Code Sequencer) ===&lt;br /&gt;
&lt;br /&gt;
A little custom core that executes a custom bytecode. 9 32-bit general purpose registers. Controlled by the host CPU. It has access to the host memory and the rest of the FMSS peripherals, and operates by performing accesses to the FMC and ECC subsystems.&lt;br /&gt;
&lt;br /&gt;
The bytecode is documented at [https://github.com/lemonjesus/S5L8702-FMISS-Tools lemonjesus/S5L8702-FMISS-Tools].&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Offset !! Register Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0xC08 || CS_STATUS ||&lt;br /&gt;
|-&lt;br /&gt;
| 0xC60 || CS_BUF_RST ||&lt;br /&gt;
|-&lt;br /&gt;
| 0xC64 || CS_BUF_RST_OK ||&lt;br /&gt;
|-&lt;br /&gt;
| 0xC6C || CS_BUF_START || &lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
== Other devices / SoCs ==&lt;br /&gt;
&lt;br /&gt;
=== S5L8700X (non-Apple) and S5L8900 ===&lt;br /&gt;
&lt;br /&gt;
A similar controller is present, called simply the FMC. It has no code sequencing functionality.&lt;br /&gt;
&lt;br /&gt;
On the S5L8900 the built-in CalmRISC16e core that&#039;s part of the ADM (Audio DSP Module) is used as a code sequencer in iOS.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=FMSS&amp;diff=22035</id>
		<title>FMSS</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=FMSS&amp;diff=22035"/>
		<updated>2023-03-17T18:15:18Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* Other devices / SoCs */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;FMSS is seemingly the name of the flash memory controller on the S5L8702, S5L8710, S5L8720 and S5L8730.&lt;br /&gt;
&lt;br /&gt;
There is no publicly available information about it, and the following has been gathered from reverse engineering [[RetailOS]] and iOS builds for the S5L8720 (iPod touch). A very similar controller is present in the S5L8700X datasheet.&lt;br /&gt;
&lt;br /&gt;
== Subsystems ==&lt;br /&gt;
&lt;br /&gt;
=== FMC (Flash Memory Controller) ===&lt;br /&gt;
&lt;br /&gt;
This is the component responsible for the actual bus transfers on the NAND bus.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Offset !! Register Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x000 || FMCTRL0 || General control register.&lt;br /&gt;
* Bit 0: Enable&lt;br /&gt;
* Bits [1..8]: CE/Bank number&lt;br /&gt;
* Bit 10: DMA enable?&lt;br /&gt;
* Bits [12..14]: Hold clocks&lt;br /&gt;
* Bits [16..18]: Setup clocks&lt;br /&gt;
* Bits [28..30]: EDO clocks&lt;br /&gt;
|-&lt;br /&gt;
| 0x004 || FMCTRL1 || Transfer control register.&lt;br /&gt;
* Bit 0: Start address transfer.&lt;br /&gt;
* Bit 1: Start read transfer.&lt;br /&gt;
* Bit 2: Start write transfer.&lt;br /&gt;
* Bit 4: ???&lt;br /&gt;
* Bit 5: Clear ???&lt;br /&gt;
* Bit 6: Clear write FIFO&lt;br /&gt;
* Bit 7: Clear read FIFO&lt;br /&gt;
|-&lt;br /&gt;
| 0x008 || FMCMD || NAND command number. Eg. 0x90: read NAND ID. Documented in JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x00C || FMADDR0 || Lower bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x010 || FMADDR1 || Higher bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x02C || FMANUM || Number of bytes to transfer during address transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x030 || FMDNUM || Number of bytes to transfer during data transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x048 || FMSTAT || Controller status.&lt;br /&gt;
* Bit 0: flash busy?&lt;br /&gt;
* Bit 1: command done. Write to clear.&lt;br /&gt;
* Bit 2: address done. Write to clear.&lt;br /&gt;
* Bit 3: transfer done. Write to clear.&lt;br /&gt;
* Bit 23: flash has become busy? Write to clear.&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
To be documented fully.&lt;br /&gt;
&lt;br /&gt;
=== ECC (Error Correction Code) ===&lt;br /&gt;
&lt;br /&gt;
To be documented.&lt;br /&gt;
&lt;br /&gt;
=== CS (Code Sequencer) ===&lt;br /&gt;
&lt;br /&gt;
A little custom core that executes a custom bytecode. 9 32-bit general purpose registers. Controlled by the host CPU. It has access to the host memory and the rest of the FMSS peripherals, and operates by performing accesses to the FMC and ECC subsystems.&lt;br /&gt;
&lt;br /&gt;
The bytecode is documented at [https://github.com/lemonjesus/S5L8702-FMISS-Tools lemonjesus/S5L8702-FMISS-Tools].&lt;br /&gt;
&lt;br /&gt;
== Other devices / SoCs ==&lt;br /&gt;
&lt;br /&gt;
=== S5L8700X (non-Apple) and S5L8900 ===&lt;br /&gt;
&lt;br /&gt;
A similar controller is present, called simply the FMC. It has no code sequencing functionality.&lt;br /&gt;
&lt;br /&gt;
On the S5L8900 the built-in CalmRISC16e core that&#039;s part of the ADM (Audio DSP Module) is used as a code sequencer in iOS.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=FMSS&amp;diff=22034</id>
		<title>FMSS</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=FMSS&amp;diff=22034"/>
		<updated>2023-03-17T18:06:20Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* FMC (Flash Memory Controller) */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;FMSS is seemingly the name of the flash memory controller on the S5L8702, S5L8710, S5L8720 and S5L8730.&lt;br /&gt;
&lt;br /&gt;
There is no publicly available information about it, and the following has been gathered from reverse engineering [[RetailOS]] and iOS builds for the S5L8720 (iPod touch). A very similar controller is present in the S5L8700X datasheet.&lt;br /&gt;
&lt;br /&gt;
== Subsystems ==&lt;br /&gt;
&lt;br /&gt;
=== FMC (Flash Memory Controller) ===&lt;br /&gt;
&lt;br /&gt;
This is the component responsible for the actual bus transfers on the NAND bus.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Offset !! Register Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x000 || FMCTRL0 || General control register.&lt;br /&gt;
* Bit 0: Enable&lt;br /&gt;
* Bits [1..8]: CE/Bank number&lt;br /&gt;
* Bit 10: DMA enable?&lt;br /&gt;
* Bits [12..14]: Hold clocks&lt;br /&gt;
* Bits [16..18]: Setup clocks&lt;br /&gt;
* Bits [28..30]: EDO clocks&lt;br /&gt;
|-&lt;br /&gt;
| 0x004 || FMCTRL1 || Transfer control register.&lt;br /&gt;
* Bit 0: Start address transfer.&lt;br /&gt;
* Bit 1: Start read transfer.&lt;br /&gt;
* Bit 2: Start write transfer.&lt;br /&gt;
* Bit 4: ???&lt;br /&gt;
* Bit 5: Clear ???&lt;br /&gt;
* Bit 6: Clear write FIFO&lt;br /&gt;
* Bit 7: Clear read FIFO&lt;br /&gt;
|-&lt;br /&gt;
| 0x008 || FMCMD || NAND command number. Eg. 0x90: read NAND ID. Documented in JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x00C || FMADDR0 || Lower bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x010 || FMADDR1 || Higher bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x02C || FMANUM || Number of bytes to transfer during address transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x030 || FMDNUM || Number of bytes to transfer during data transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x048 || FMSTAT || Controller status.&lt;br /&gt;
* Bit 0: flash busy?&lt;br /&gt;
* Bit 1: command done. Write to clear.&lt;br /&gt;
* Bit 2: address done. Write to clear.&lt;br /&gt;
* Bit 3: transfer done. Write to clear.&lt;br /&gt;
* Bit 23: flash has become busy? Write to clear.&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
To be documented fully.&lt;br /&gt;
&lt;br /&gt;
=== ECC (Error Correction Code) ===&lt;br /&gt;
&lt;br /&gt;
To be documented.&lt;br /&gt;
&lt;br /&gt;
=== CS (Code Sequencer) ===&lt;br /&gt;
&lt;br /&gt;
A little custom core that executes a custom bytecode. 9 32-bit general purpose registers. Controlled by the host CPU. It has access to the host memory and the rest of the FMSS peripherals, and operates by performing accesses to the FMC and ECC subsystems.&lt;br /&gt;
&lt;br /&gt;
The bytecode is documented at [https://github.com/lemonjesus/S5L8702-FMISS-Tools lemonjesus/S5L8702-FMISS-Tools].&lt;br /&gt;
&lt;br /&gt;
== Other devices / SoCs ==&lt;br /&gt;
&lt;br /&gt;
=== S5L8700X (non-Apple) and S5L8900 ===&lt;br /&gt;
&lt;br /&gt;
A similar controller is present, called simply the FMC. It has no code sequencing functionality.&lt;br /&gt;
&lt;br /&gt;
On the S5L8900 the built-in CalmRISC16e core that&#039;s part of the ADM (Audio DSP Module) is used as a code sequencer in iOS.&lt;br /&gt;
&lt;br /&gt;
=== S5L8950 / A6 ===&lt;br /&gt;
&lt;br /&gt;
The controller is called &#039;PPNFMSS&#039; and seems to use the same CS bytecode, and a generally similar register layout.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=FMSS&amp;diff=22033</id>
		<title>FMSS</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=FMSS&amp;diff=22033"/>
		<updated>2023-03-17T17:59:09Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* FMC (Flash Memory Controller) */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;FMSS is seemingly the name of the flash memory controller on the S5L8702, S5L8710, S5L8720 and S5L8730.&lt;br /&gt;
&lt;br /&gt;
There is no publicly available information about it, and the following has been gathered from reverse engineering [[RetailOS]] and iOS builds for the S5L8720 (iPod touch). A very similar controller is present in the S5L8700X datasheet.&lt;br /&gt;
&lt;br /&gt;
== Subsystems ==&lt;br /&gt;
&lt;br /&gt;
=== FMC (Flash Memory Controller) ===&lt;br /&gt;
&lt;br /&gt;
This is the component responsible for the actual bus transfers on the NAND bus.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Offset !! Register Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x000 || FMCTRL0 || General control register.&lt;br /&gt;
* Bit 0: Enable&lt;br /&gt;
* Bits [1..8]: CE/Bank number&lt;br /&gt;
* Bit 10: DMA enable?&lt;br /&gt;
* Bits [12..14]: Hold clocks&lt;br /&gt;
* Bits [16..18]: Setup clocks&lt;br /&gt;
* Bits [28..30]: EDO clocks&lt;br /&gt;
|-&lt;br /&gt;
| 0x004 || FMCTRL1 || Transfer control register.&lt;br /&gt;
* Bit 0: Start address transfer.&lt;br /&gt;
* Bit 1: Start read transfer.&lt;br /&gt;
* Bit 2: Start write transfer.&lt;br /&gt;
* Bit 4: ???&lt;br /&gt;
* Bit 5: Clear ???&lt;br /&gt;
* Bit 6: Clear write FIFO&lt;br /&gt;
* Bit 7: Clear read FIFO&lt;br /&gt;
|-&lt;br /&gt;
| 0x008 || FMCMD || NAND command number. Eg. 0x90: read NAND ID. Documented in JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x00C || FMADDR0 || Lower bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x010 || FMADDR1 || Higher bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x02C || FMANUM || Number of bytes to transfer during address transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x030 || FMDNUM || Number of bytes to transfer during data transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x048 || FMSTAT || Controller status.&lt;br /&gt;
* Bit 1: command done. Write to clear.&lt;br /&gt;
* Bit 2: address done. Write to clear.&lt;br /&gt;
* Bit 3: transfer done. Write to clear.&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
To be documented fully.&lt;br /&gt;
&lt;br /&gt;
=== ECC (Error Correction Code) ===&lt;br /&gt;
&lt;br /&gt;
To be documented.&lt;br /&gt;
&lt;br /&gt;
=== CS (Code Sequencer) ===&lt;br /&gt;
&lt;br /&gt;
A little custom core that executes a custom bytecode. 9 32-bit general purpose registers. Controlled by the host CPU. It has access to the host memory and the rest of the FMSS peripherals, and operates by performing accesses to the FMC and ECC subsystems.&lt;br /&gt;
&lt;br /&gt;
The bytecode is documented at [https://github.com/lemonjesus/S5L8702-FMISS-Tools lemonjesus/S5L8702-FMISS-Tools].&lt;br /&gt;
&lt;br /&gt;
== Other devices / SoCs ==&lt;br /&gt;
&lt;br /&gt;
=== S5L8700X (non-Apple) and S5L8900 ===&lt;br /&gt;
&lt;br /&gt;
A similar controller is present, called simply the FMC. It has no code sequencing functionality.&lt;br /&gt;
&lt;br /&gt;
On the S5L8900 the built-in CalmRISC16e core that&#039;s part of the ADM (Audio DSP Module) is used as a code sequencer in iOS.&lt;br /&gt;
&lt;br /&gt;
=== S5L8950 / A6 ===&lt;br /&gt;
&lt;br /&gt;
The controller is called &#039;PPNFMSS&#039; and seems to use the same CS bytecode, and a generally similar register layout.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=FMSS&amp;diff=22032</id>
		<title>FMSS</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=FMSS&amp;diff=22032"/>
		<updated>2023-03-17T17:54:34Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* FMC (Flash Memory Controller) */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;FMSS is seemingly the name of the flash memory controller on the S5L8702, S5L8710, S5L8720 and S5L8730.&lt;br /&gt;
&lt;br /&gt;
There is no publicly available information about it, and the following has been gathered from reverse engineering [[RetailOS]] and iOS builds for the S5L8720 (iPod touch). A very similar controller is present in the S5L8700X datasheet.&lt;br /&gt;
&lt;br /&gt;
== Subsystems ==&lt;br /&gt;
&lt;br /&gt;
=== FMC (Flash Memory Controller) ===&lt;br /&gt;
&lt;br /&gt;
This is the component responsible for the actual bus transfers on the NAND bus.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Offset !! Register Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x000 || FMCTRL0 || General control register.&lt;br /&gt;
* Bit 0: Enable&lt;br /&gt;
* Bits [1..8]: CE/Bank number&lt;br /&gt;
* Bit 10: DMA enable?&lt;br /&gt;
* Bits [12..14]: Hold clocks&lt;br /&gt;
* Bits [16..18]: Setup clocks&lt;br /&gt;
* Bits [28..30]: EDO clocks&lt;br /&gt;
|-&lt;br /&gt;
| 0x004 || FMCTRL1 || Transfer control register.&lt;br /&gt;
* Bit 0: Start address transfer.&lt;br /&gt;
* Bit 1: Start read transfer.&lt;br /&gt;
* Bit 2: Start write transfer.&lt;br /&gt;
* Bit 4: ???&lt;br /&gt;
* Bit 5: Clear ???&lt;br /&gt;
* Bit 6: Clear write FIFO&lt;br /&gt;
* Bit 7: Clear read FIFO&lt;br /&gt;
|-&lt;br /&gt;
| 0x008 || FMCMD || NAND command number. Eg. 0x90: read NAND ID. Documented in JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x00C || FMADDR0 || Lower bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x010 || FMADDR1 || Higher bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x02C || FMANUM || Number of bytes to transfer during address transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x030 || FMDNUM || Number of bytes to transfer during data transfer minus one (ie. countdown counter).&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
To be documented fully.&lt;br /&gt;
&lt;br /&gt;
=== ECC (Error Correction Code) ===&lt;br /&gt;
&lt;br /&gt;
To be documented.&lt;br /&gt;
&lt;br /&gt;
=== CS (Code Sequencer) ===&lt;br /&gt;
&lt;br /&gt;
A little custom core that executes a custom bytecode. 9 32-bit general purpose registers. Controlled by the host CPU. It has access to the host memory and the rest of the FMSS peripherals, and operates by performing accesses to the FMC and ECC subsystems.&lt;br /&gt;
&lt;br /&gt;
The bytecode is documented at [https://github.com/lemonjesus/S5L8702-FMISS-Tools lemonjesus/S5L8702-FMISS-Tools].&lt;br /&gt;
&lt;br /&gt;
== Other devices / SoCs ==&lt;br /&gt;
&lt;br /&gt;
=== S5L8700X (non-Apple) and S5L8900 ===&lt;br /&gt;
&lt;br /&gt;
A similar controller is present, called simply the FMC. It has no code sequencing functionality.&lt;br /&gt;
&lt;br /&gt;
On the S5L8900 the built-in CalmRISC16e core that&#039;s part of the ADM (Audio DSP Module) is used as a code sequencer in iOS.&lt;br /&gt;
&lt;br /&gt;
=== S5L8950 / A6 ===&lt;br /&gt;
&lt;br /&gt;
The controller is called &#039;PPNFMSS&#039; and seems to use the same CS bytecode, and a generally similar register layout.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=FMSS&amp;diff=22031</id>
		<title>FMSS</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=FMSS&amp;diff=22031"/>
		<updated>2023-03-17T17:51:09Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* FMC (Flash Memory Controller) */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;FMSS is seemingly the name of the flash memory controller on the S5L8702, S5L8710, S5L8720 and S5L8730.&lt;br /&gt;
&lt;br /&gt;
There is no publicly available information about it, and the following has been gathered from reverse engineering [[RetailOS]] and iOS builds for the S5L8720 (iPod touch). A very similar controller is present in the S5L8700X datasheet.&lt;br /&gt;
&lt;br /&gt;
== Subsystems ==&lt;br /&gt;
&lt;br /&gt;
=== FMC (Flash Memory Controller) ===&lt;br /&gt;
&lt;br /&gt;
This is the component responsible for the actual bus transfers on the NAND bus.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Offset !! Register Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x000 || FMCTRL0 || General control register.&lt;br /&gt;
* Bit 0: Enable&lt;br /&gt;
* Bits [1..8]: CE/Bank number&lt;br /&gt;
* Bit 10: DMA enable?&lt;br /&gt;
* Bits [12..14]: Hold clocks&lt;br /&gt;
* Bits [16..18]: Setup clocks&lt;br /&gt;
* Bits [28..30]: EDO clocks&lt;br /&gt;
|-&lt;br /&gt;
| 0x004 || FMCTRL1 || Control register used to start transfers. Bit 0: DOADDR, Bit 1: DORXDAT, Bit2: DOTXDAT.&lt;br /&gt;
|-&lt;br /&gt;
| 0x008 || FMCMD || NAND command number. Eg. 0x90: read NAND ID. Documented in JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x00C || FMADDR0 || Lower bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x010 || FMADDR1 || Higher bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x02C || FMANUM || Number of bytes to transfer during address transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x030 || FMDNUM || Number of bytes to transfer during data transfer minus one (ie. countdown counter).&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
To be documented fully.&lt;br /&gt;
&lt;br /&gt;
=== ECC (Error Correction Code) ===&lt;br /&gt;
&lt;br /&gt;
To be documented.&lt;br /&gt;
&lt;br /&gt;
=== CS (Code Sequencer) ===&lt;br /&gt;
&lt;br /&gt;
A little custom core that executes a custom bytecode. 9 32-bit general purpose registers. Controlled by the host CPU. It has access to the host memory and the rest of the FMSS peripherals, and operates by performing accesses to the FMC and ECC subsystems.&lt;br /&gt;
&lt;br /&gt;
The bytecode is documented at [https://github.com/lemonjesus/S5L8702-FMISS-Tools lemonjesus/S5L8702-FMISS-Tools].&lt;br /&gt;
&lt;br /&gt;
== Other devices / SoCs ==&lt;br /&gt;
&lt;br /&gt;
=== S5L8700X (non-Apple) and S5L8900 ===&lt;br /&gt;
&lt;br /&gt;
A similar controller is present, called simply the FMC. It has no code sequencing functionality.&lt;br /&gt;
&lt;br /&gt;
On the S5L8900 the built-in CalmRISC16e core that&#039;s part of the ADM (Audio DSP Module) is used as a code sequencer in iOS.&lt;br /&gt;
&lt;br /&gt;
=== S5L8950 / A6 ===&lt;br /&gt;
&lt;br /&gt;
The controller is called &#039;PPNFMSS&#039; and seems to use the same CS bytecode, and a generally similar register layout.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=FMSS&amp;diff=22030</id>
		<title>FMSS</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=FMSS&amp;diff=22030"/>
		<updated>2023-03-17T17:41:28Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* CS (Code Sequencer) */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;FMSS is seemingly the name of the flash memory controller on the S5L8702, S5L8710, S5L8720 and S5L8730.&lt;br /&gt;
&lt;br /&gt;
There is no publicly available information about it, and the following has been gathered from reverse engineering [[RetailOS]] and iOS builds for the S5L8720 (iPod touch). A very similar controller is present in the S5L8700X datasheet.&lt;br /&gt;
&lt;br /&gt;
== Subsystems ==&lt;br /&gt;
&lt;br /&gt;
=== FMC (Flash Memory Controller) ===&lt;br /&gt;
&lt;br /&gt;
This is the component responsible for the actual bus transfers on the NAND bus.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Offset !! Register Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x000 || FMCTRL0 || General control register. Bit 10: MASTER_EN, bit 24: DMA_EN.&lt;br /&gt;
|-&lt;br /&gt;
| 0x004 || FMCTRL1 || Control register used to start transfers. Bit 0: DOADDR, Bit 1: DORXDAT, Bit2: DOTXDAT.&lt;br /&gt;
|-&lt;br /&gt;
| 0x008 || FMCMD || NAND command number. Eg. 0x90: read NAND ID. Documented in JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x00C || FMADDR0 || Lower bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x010 || FMADDR1 || Higher bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x02C || FMANUM || Number of bytes to transfer during address transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x030 || FMDNUM || Number of bytes to transfer during data transfer minus one (ie. countdown counter).&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
To be documented fully.&lt;br /&gt;
&lt;br /&gt;
=== ECC (Error Correction Code) ===&lt;br /&gt;
&lt;br /&gt;
To be documented.&lt;br /&gt;
&lt;br /&gt;
=== CS (Code Sequencer) ===&lt;br /&gt;
&lt;br /&gt;
A little custom core that executes a custom bytecode. 9 32-bit general purpose registers. Controlled by the host CPU. It has access to the host memory and the rest of the FMSS peripherals, and operates by performing accesses to the FMC and ECC subsystems.&lt;br /&gt;
&lt;br /&gt;
The bytecode is documented at [https://github.com/lemonjesus/S5L8702-FMISS-Tools lemonjesus/S5L8702-FMISS-Tools].&lt;br /&gt;
&lt;br /&gt;
== Other devices / SoCs ==&lt;br /&gt;
&lt;br /&gt;
=== S5L8700X (non-Apple) and S5L8900 ===&lt;br /&gt;
&lt;br /&gt;
A similar controller is present, called simply the FMC. It has no code sequencing functionality.&lt;br /&gt;
&lt;br /&gt;
On the S5L8900 the built-in CalmRISC16e core that&#039;s part of the ADM (Audio DSP Module) is used as a code sequencer in iOS.&lt;br /&gt;
&lt;br /&gt;
=== S5L8950 / A6 ===&lt;br /&gt;
&lt;br /&gt;
The controller is called &#039;PPNFMSS&#039; and seems to use the same CS bytecode, and a generally similar register layout.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=FMSS&amp;diff=22029</id>
		<title>FMSS</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=FMSS&amp;diff=22029"/>
		<updated>2023-03-17T17:40:26Z</updated>

		<summary type="html">&lt;p&gt;Q3k: Created page with &amp;quot;FMSS is seemingly the name of the flash memory controller on the S5L8702, S5L8710, S5L8720 and S5L8730.  There is no publicly available information about it, and the following...&amp;quot;&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;FMSS is seemingly the name of the flash memory controller on the S5L8702, S5L8710, S5L8720 and S5L8730.&lt;br /&gt;
&lt;br /&gt;
There is no publicly available information about it, and the following has been gathered from reverse engineering [[RetailOS]] and iOS builds for the S5L8720 (iPod touch). A very similar controller is present in the S5L8700X datasheet.&lt;br /&gt;
&lt;br /&gt;
== Subsystems ==&lt;br /&gt;
&lt;br /&gt;
=== FMC (Flash Memory Controller) ===&lt;br /&gt;
&lt;br /&gt;
This is the component responsible for the actual bus transfers on the NAND bus.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Offset !! Register Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x000 || FMCTRL0 || General control register. Bit 10: MASTER_EN, bit 24: DMA_EN.&lt;br /&gt;
|-&lt;br /&gt;
| 0x004 || FMCTRL1 || Control register used to start transfers. Bit 0: DOADDR, Bit 1: DORXDAT, Bit2: DOTXDAT.&lt;br /&gt;
|-&lt;br /&gt;
| 0x008 || FMCMD || NAND command number. Eg. 0x90: read NAND ID. Documented in JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x00C || FMADDR0 || Lower bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x010 || FMADDR1 || Higher bits of address to be written in NAND address transfer. See JEDEC docs and NAND chip datasheets.&lt;br /&gt;
|-&lt;br /&gt;
| 0x02C || FMANUM || Number of bytes to transfer during address transfer minus one (ie. countdown counter).&lt;br /&gt;
|-&lt;br /&gt;
| 0x030 || FMDNUM || Number of bytes to transfer during data transfer minus one (ie. countdown counter).&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
To be documented fully.&lt;br /&gt;
&lt;br /&gt;
=== ECC (Error Correction Code) ===&lt;br /&gt;
&lt;br /&gt;
To be documented.&lt;br /&gt;
&lt;br /&gt;
=== CS (Code Sequencer) ===&lt;br /&gt;
&lt;br /&gt;
A little custom core that executes a custom bytecode. 9 32-bit general purpose registers. Controlled by the host CPU.&lt;br /&gt;
&lt;br /&gt;
The bytecode is documented at [https://github.com/lemonjesus/S5L8702-FMISS-Tools lemonjesus/S5L8702-FMISS-Tools].&lt;br /&gt;
&lt;br /&gt;
== Other devices / SoCs ==&lt;br /&gt;
&lt;br /&gt;
=== S5L8700X (non-Apple) and S5L8900 ===&lt;br /&gt;
&lt;br /&gt;
A similar controller is present, called simply the FMC. It has no code sequencing functionality.&lt;br /&gt;
&lt;br /&gt;
On the S5L8900 the built-in CalmRISC16e core that&#039;s part of the ADM (Audio DSP Module) is used as a code sequencer in iOS.&lt;br /&gt;
&lt;br /&gt;
=== S5L8950 / A6 ===&lt;br /&gt;
&lt;br /&gt;
The controller is called &#039;PPNFMSS&#039; and seems to use the same CS bytecode, and a generally similar register layout.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=JTAG&amp;diff=22028</id>
		<title>JTAG</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=JTAG&amp;diff=22028"/>
		<updated>2023-03-08T18:25:54Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* &amp;#039;Memory locked out&amp;#039; JTAG */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;Some iPods seemingly have the ability to be debugged over JTAG. Here&#039;s some documentation on getting started.&lt;br /&gt;
&lt;br /&gt;
== Devices ==&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Device !! Protocol !! Location&lt;br /&gt;
|-&lt;br /&gt;
| Nano 2G || JTAG (memory locked out) || 30-pin connector, needs jumpers&lt;br /&gt;
|-&lt;br /&gt;
| Nano 5G || JTAG (memory locked out) || 30-pin connector, needs jumpers&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
=== Nano 2G ===&lt;br /&gt;
&lt;br /&gt;
The following pins carry &#039;classic&#039; multi-wire JTAG on the Dock Connector:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Pin Number !! Function&lt;br /&gt;
|-&lt;br /&gt;
| 17 || TMS&lt;br /&gt;
|-&lt;br /&gt;
| 21 || TDI&lt;br /&gt;
|-&lt;br /&gt;
| 22 || TDO&lt;br /&gt;
|-&lt;br /&gt;
| 23 || TCK&lt;br /&gt;
|-&lt;br /&gt;
| 24 || nTRST&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
In addition, the following pads need to be bridged on the logic board:&lt;br /&gt;
&lt;br /&gt;
[[Image:Top_annote.jpg|500px]]&lt;br /&gt;
&lt;br /&gt;
=== Nano 5G ===&lt;br /&gt;
&lt;br /&gt;
The following pins carry &#039;classic&#039; multi-wire JTAG on the Dock Connector:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Pin Number !! Function&lt;br /&gt;
|-&lt;br /&gt;
| 3 || RTCK (optional)&lt;br /&gt;
|-&lt;br /&gt;
| 5 || TDO&lt;br /&gt;
|-&lt;br /&gt;
| 9 || TDI&lt;br /&gt;
|-&lt;br /&gt;
| 14 || TCK&lt;br /&gt;
|-&lt;br /&gt;
| 17 || TMS&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
In addition, the following 01005 footprints need to be populated with 0 ohm resistors (or bridged with a wire) on the logic board:&lt;br /&gt;
&lt;br /&gt;
[[Image:Nano5G JTAG.png|500px]]&lt;br /&gt;
&lt;br /&gt;
== &#039;Memory locked out&#039; JTAG ==&lt;br /&gt;
&lt;br /&gt;
Even though JTAG is accessible on the N2G/N5G, and the CPU core can be controlled over it, no memory is accessible anymore. In fact, it seems like the CPU core gets fully disconnected from the AHB bus any time JTAG is enabled. During the [[Nano2G_HW_analysis|Nano 2G initial reverse engineering process]] low-level access to Dcache was used to dump memory. However, no method of re-establishing full memory access has yet been found.&lt;br /&gt;
&lt;br /&gt;
[[Image:Nano5G Broken JTAG.png|300px]]&lt;br /&gt;
&lt;br /&gt;
The above listing shows OpenOCD/GDB connected to a Nano 5G a while after it has been first scanned via JTAG. It seems to be stuck in a permanent &#039;data abort&#039; handler loop, with some pretty trashed register values (although some of them are still in valid range for running the BootROM).&lt;br /&gt;
&lt;br /&gt;
What has been attempted so far:&lt;br /&gt;
# Making sure the WDT isn&#039;t running.&lt;br /&gt;
# Opening all clock gates&lt;br /&gt;
# Writing to CHIPID in an attempt to &#039;demote&#039; the devices à la iOS.&lt;br /&gt;
# Connecting while the device is in the BootROM.&lt;br /&gt;
# Using a fancy JTAG probe (Lauterbach)&lt;br /&gt;
# Writing to 0x3970_0104 (which seems to have three security write-only bits, two of which disable built-in AES keys, the third being unknown)&lt;br /&gt;
&lt;br /&gt;
Other observations:&lt;br /&gt;
# The &#039;memory bus disconnection&#039; seems to happen immediately after a JTAG chain scan, so this might be implemented as extra logic somewhere in the SoC that needs some magic TDI bits to be fed so it doesn&#039;t lock out the AHB bus (or whatever it does).&lt;br /&gt;
# This might just be a bug in openocd ARM11, or some quirk of the ARM1176 core (or SoC) in which caches break during debug access, but that seems unlikely.&lt;br /&gt;
# The implementation might be Samsung&#039;s &#039;SecureJTAG&#039;, as used in eg. the [https://web.archive.org/web/20230308173730/http://www.fdi.ucm.es/profesor/mendias/psyd/docs/S5PC100.pdf S5PC100]. However, the S5L87xx does not seem to have eFUSE registers that would hold a key as described in this datasheet - or such a register hasn&#039;t yet been found. It is also unknown, given the key, how to actually send it over JTAG to unlock it.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=JTAG&amp;diff=22027</id>
		<title>JTAG</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=JTAG&amp;diff=22027"/>
		<updated>2023-03-08T17:40:16Z</updated>

		<summary type="html">&lt;p&gt;Q3k: /* &amp;#039;Memory locked out&amp;#039; JTAG */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;Some iPods seemingly have the ability to be debugged over JTAG. Here&#039;s some documentation on getting started.&lt;br /&gt;
&lt;br /&gt;
== Devices ==&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Device !! Protocol !! Location&lt;br /&gt;
|-&lt;br /&gt;
| Nano 2G || JTAG (memory locked out) || 30-pin connector, needs jumpers&lt;br /&gt;
|-&lt;br /&gt;
| Nano 5G || JTAG (memory locked out) || 30-pin connector, needs jumpers&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
=== Nano 2G ===&lt;br /&gt;
&lt;br /&gt;
The following pins carry &#039;classic&#039; multi-wire JTAG on the Dock Connector:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Pin Number !! Function&lt;br /&gt;
|-&lt;br /&gt;
| 17 || TMS&lt;br /&gt;
|-&lt;br /&gt;
| 21 || TDI&lt;br /&gt;
|-&lt;br /&gt;
| 22 || TDO&lt;br /&gt;
|-&lt;br /&gt;
| 23 || TCK&lt;br /&gt;
|-&lt;br /&gt;
| 24 || nTRST&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
In addition, the following pads need to be bridged on the logic board:&lt;br /&gt;
&lt;br /&gt;
[[Image:Top_annote.jpg|500px]]&lt;br /&gt;
&lt;br /&gt;
=== Nano 5G ===&lt;br /&gt;
&lt;br /&gt;
The following pins carry &#039;classic&#039; multi-wire JTAG on the Dock Connector:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Pin Number !! Function&lt;br /&gt;
|-&lt;br /&gt;
| 3 || RTCK (optional)&lt;br /&gt;
|-&lt;br /&gt;
| 5 || TDO&lt;br /&gt;
|-&lt;br /&gt;
| 9 || TDI&lt;br /&gt;
|-&lt;br /&gt;
| 14 || TCK&lt;br /&gt;
|-&lt;br /&gt;
| 17 || TMS&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
In addition, the following 01005 footprints need to be populated with 0 ohm resistors (or bridged with a wire) on the logic board:&lt;br /&gt;
&lt;br /&gt;
[[Image:Nano5G JTAG.png|500px]]&lt;br /&gt;
&lt;br /&gt;
== &#039;Memory locked out&#039; JTAG ==&lt;br /&gt;
&lt;br /&gt;
Even though JTAG is accessible on the N2G/N5G, and the CPU core can be controlled over it, no memory is accessible anymore. In fact, it seems like the CPU core gets fully disconnected from the AHB bus any time JTAG is enabled. During the [[Nano2G_HW_analysis|Nano 2G initial reverse engineering process]] low-level access to Dcache was used to dump memory. However, no method of re-establishing full memory access has yet been found.&lt;br /&gt;
&lt;br /&gt;
[[Image:Nano5G Broken JTAG.png|300px]]&lt;br /&gt;
&lt;br /&gt;
The above listing shows OpenOCD/GDB connected to a Nano 5G a while after it has been first scanned via JTAG. It seems to be stuck in a permanent &#039;data abort&#039; handler loop, with some pretty trashed register values (although some of them are still in valid range for running the BootROM).&lt;br /&gt;
&lt;br /&gt;
What has been attempted so far:&lt;br /&gt;
# Making sure the WDT isn&#039;t running.&lt;br /&gt;
# Writing to CHIPID in an attempt to &#039;demote&#039; the devices à la iOS.&lt;br /&gt;
# Connecting while the device is in the BootROM.&lt;br /&gt;
# Using a fancy JTAG probe (Lauterbach)&lt;br /&gt;
# Writing to 0x3970_0104 (which seems to have three security write-only bits, two of which disable built-in AES keys, the third being unknown)&lt;br /&gt;
&lt;br /&gt;
Other observations:&lt;br /&gt;
# The &#039;memory bus disconnection&#039; seems to happen immediately after a JTAG chain scan, so this might be implemented as extra logic somewhere in the SoC that needs some magic TDI bits to be fed so it doesn&#039;t lock out the AHB bus (or whatever it does).&lt;br /&gt;
# This might just be a bug in openocd ARM11, or some quirk of the ARM1176 core (or SoC) in which caches break during debug access, but that seems unlikely.&lt;br /&gt;
# The implementation might be Samsung&#039;s &#039;SecureJTAG&#039;, as used in eg. the [https://web.archive.org/web/20230308173730/http://www.fdi.ucm.es/profesor/mendias/psyd/docs/S5PC100.pdf S5PC100]. However, the S5L87xx does not seem to have eFUSE registers that would hold a key as described in this datasheet - or such a register hasn&#039;t yet been found. It is also unknown, given the key, how to actually send it over JTAG to unlock it.&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Nano_4G&amp;diff=22026</id>
		<title>Nano 4G</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Nano_4G&amp;diff=22026"/>
		<updated>2023-03-08T14:31:06Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Image:nano_4g_frt_a.png|500px]]&lt;br /&gt;
[[Image:nano_4g_bck_a.png|500px]]&lt;br /&gt;
==Components==&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Label !! Component !! Part !! Markings !! Notes&lt;br /&gt;
|-&lt;br /&gt;
| 2&lt;br /&gt;
| CPU&lt;br /&gt;
| Samsung S5L8720&lt;br /&gt;
| 339S0049 ARM, K4X56323PI-KGC4, YWE025QH 825, APL0278A00, N1B2HOP 0831&lt;br /&gt;
| ARM1176JZF-S processor. It is definitely worth knowing that this is the exact same processor used in the iTouch 2G. This could mean that some of the same exploits for that could possibly be used. [http://theiphonewiki.com/wiki/index.php?title=S5L8720_(Hardware) Here] is a very interesting page about the S5L8720 processor.&lt;br /&gt;
|-&lt;br /&gt;
| &lt;br /&gt;
| SDRAM&lt;br /&gt;
| &lt;br /&gt;
|&lt;br /&gt;
| 32MB, probably MDDR. Integrated into the processor, similar to the iPod Touch and iPhone lines.&lt;br /&gt;
|-&lt;br /&gt;
| 4&lt;br /&gt;
| Accelerometer&lt;br /&gt;
| [http://www.st.com/stonline/products/literature/ds/12726.pdf LIS302DL]&lt;br /&gt;
| 33DL, 2827&lt;br /&gt;
| The newer Touch&#039;s, iPhone&#039;s, and even the iPad have similar accelerometers, and I&#039;ve discovered a pattern in the chip names.&lt;br /&gt;
|-&lt;br /&gt;
| 6&lt;br /&gt;
| NAND Flash&lt;br /&gt;
| Varies&lt;br /&gt;
| TH58NVG6D1DLA87, U20516, JAPAN, 0826MAE&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
| 5&lt;br /&gt;
| Audio codec&lt;br /&gt;
| [http://www.cirrus.com/en/pubs/proDatasheet/CS42L55_F1.pdf CS42L58]&lt;br /&gt;
| 338S055C, 189N0824, SGP&lt;br /&gt;
| I determined this because the [[Nano 5G]] has a similar chip, which we are sure of the identity. One person lifted this chip and found that the pins connect to the LCD connector. Not much info was given, and it could just be a common ground, but the identity of this chip is still up in the air.&lt;br /&gt;
|-&lt;br /&gt;
| 1&lt;br /&gt;
| Power manager&lt;br /&gt;
| Dialog D1759&lt;br /&gt;
| 338S0687-AC, 08288HBB&lt;br /&gt;
| &lt;br /&gt;
|-&lt;br /&gt;
| 3&lt;br /&gt;
| &lt;br /&gt;
| &lt;br /&gt;
|&lt;br /&gt;
| &lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
== Bootrom ==&lt;br /&gt;
&lt;br /&gt;
See [[S5L8720 Bootrom]]. Different from the S5L8720 bootrom used in the iPod Touch 2G (which is iBoot-based, a.k.a. SecureROM).&lt;br /&gt;
&lt;br /&gt;
== Memory Map ==&lt;br /&gt;
&lt;br /&gt;
See [https://www.theiphonewiki.com/wiki/S5L8720_(Hardware)] and [https://code.google.com/archive/p/chronicdev/wikis/N72APDevTree.wiki].&lt;br /&gt;
&lt;br /&gt;
In addition to the above, a few extra memory regions have been found while reverse engineering the [[S5L8720 Bootrom]]:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Name !! Address !! Notes&lt;br /&gt;
|-&lt;br /&gt;
| Mystery DMA&lt;br /&gt;
| 0x3880_0000&lt;br /&gt;
| A PL080-like DMA engine, but with slightly different MMIO register structure. Used by the [[S5L8720 Bootrom|bootrom]] to copy the DFU payload from 0x2200_0600 to 0x2200_0000 after decryption and verification. Or maybe that&#039;s actually doing the decryption? To be investigated.&lt;br /&gt;
|-&lt;br /&gt;
| Mystery Interrupt Thing&lt;br /&gt;
| 0x39a0_0000&lt;br /&gt;
| Not the VICs (0x38e0_0000, 0x38e0_1000), not the EdgeIC (0x38e0_2000). Seems to hold 7 different 32-bit registers for interrupt status at 0xa0, and 7 different 32-bit registers for interrupt mask at 0xc0. The 7 different registers correspond to 7 &#039;modes&#039; of ISRs set up in the bootrom. Not much is known about what it does, and what these &#039;modes&#039; are. To be investigated.&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
==Reverse Engineering Results==&lt;br /&gt;
Timers: These clockgates have been found to be related to timers: 37, 55, 56, 57, 58, 59, 60, 69, 70, 128, 129, 130, 131, 132, 133, 134, 150 and 151.&lt;br /&gt;
&lt;br /&gt;
==Status registers==&lt;br /&gt;
We dumped all c0 coprocessor registers:&lt;br /&gt;
&lt;br /&gt;
===c0,c0===&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x410FB764&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; ARM1176 rev. 4&lt;br /&gt;
===c0,c1===&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x1D152152&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; DCache/ICache 16KB each, 4 way associative, 32 bytes line size&lt;br /&gt;
===c0,c2===&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x00000000&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; No TCM&lt;br /&gt;
===c0,c3===&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x00000800&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; Unified TLB, 8 lockable entries&lt;br /&gt;
===c1,c0===&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x00000111&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; ARM/Thumb1/Jazelle support, no Thumb2 support&lt;br /&gt;
===c1,c1===&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x00000011&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; Trustzone v1&lt;br /&gt;
===c1,c2===&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x00000033&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; Supports debug model v6.1, both applications processor and secure&lt;br /&gt;
===c1,c3===&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x00000000&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; No auxiliary features&lt;br /&gt;
===c1,c4===&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x01130003&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; FCSE, Auxiliary Control register, ARMv6 TCM/DMA, no DMA cache coherency, no multicore cache coherency, VMSA v7&lt;br /&gt;
===c1,c5===&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x10030302&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; Branch target buffer, Harvard architecture, various cache operations supported (see TRM)&lt;br /&gt;
===c1,c6===&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x01222100&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; WFI, Data synchronization barrier, Prefetch flush, Data memory barrier, various TLB/cache operations supported (see TRM), no prefetch cache range operation&lt;br /&gt;
&lt;br /&gt;
===c1,c7===&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x00000000&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; No hierarchical cache maintenance support&lt;br /&gt;
===c2,c0===&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x00140011&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; Supports BKPT, CDP, CDP2, LDC, LDC2, MCD, MCD2, MRC, MRC2, STC, STC2, MCRR, MCRR2, MRRC, MRRC2, CLZ, SWP and SWPB, doesn&#039;t support division, combined compare and branch or bitfield instructions&lt;br /&gt;
===c2,c1===&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x12002111&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; Supports BXJ, BX, BLX, PC loads have BX behavior, supports SXTB, SXTAB, SXTB16, SXTAB16, SXTH, SXTAH, UXTB, &lt;br /&gt;
UXTAB, UXTB16, UXTAB16, UXTH, UXTAH, SRS, RFE, CPS, LDM(2), LDM(3), STM(2) and SETEND&lt;br /&gt;
===c2,c2===&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x11231121&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; Supports REV, REV16, REVSH, MRS, MSR, UMULL, UMLAL, UMAAL, SMULL, SMLAL, SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, SMUSDX, MLA, restartable LDM/STM, PLD, LDRD, STRD and Q bit in PSRs&lt;br /&gt;
===c2,c3===&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x01102131&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; Supports true NOP, Thumb MOV(3)/CPU, LDREX, STREX, LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX, SVC, PKHBT, PKHTB, QADD16, QADD8, QADDSUBX, QSUB16, QSUB8, QSUBADDX, SADD16, SADD8, SADDSUBX, SEL, SHADD16, SHADD8, SHADDSUBX, SHSUB16, SHSUB8, SHSUBADDX, SSAT, SSAT16, SSUB16, SSUB8, SSUBADDX, SXTAB16, SXTB16, UADD16, UADD8, UADDSUBX, UHADD16, UHADD8, UHADDSUBX, UHSUB16, UHSUB8, UHSUBADDX, UQADD16, UQADD8, UQADDSUBX, UQSUB16, UQSUB8, UQSUBADDX, USAD8, USADA8, USAT, USAT16, USUB16, USUB8, USUBADDX, UXTAB16, UXTB16, QADD, QDADD, QDSUB, QSUB, and the Q and GE[3:0] bits in the PSRs. Does nut support branch table and Thumb2 instructions.&lt;br /&gt;
===c2,c4===&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x00001141&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; Supports SMC, writeback instructions, shift of loads and stores by 0-3 bits to the left, constant shift options, register controlled shift options, LDRBT, LDRT, STRBT and STRT. No barrier instructions support.&lt;br /&gt;
===c2,c5===&lt;br /&gt;
&#039;&#039;&#039;Value:&#039;&#039;&#039; 0x00000000&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Interpretation:&#039;&#039;&#039; No additional implementation defined instruction set extensions&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Teardowns:&lt;br /&gt;
*http://www.ifixit.com/Guide/First-Look/iPod-Nano-4th-Generation/584/1&lt;br /&gt;
Other:&lt;br /&gt;
*http://theiphonewiki.com/wiki/index.php?title=S5L8720_(Hardware)&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Hardware&amp;diff=22025</id>
		<title>Hardware</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Hardware&amp;diff=22025"/>
		<updated>2023-02-25T22:37:04Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;This is just a basic comparison of each generation&#039;s main components. For a detailed hardware analysis of a generation, click on it&#039;s link.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Generation !! SoC !! RAM !! NOR/Utility Flash !! Codename !! UpdaterFamilyID&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 1G]]&lt;br /&gt;
|PP5021C-TDF&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41856 SST39WF400A] (512KiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 2G]]&lt;br /&gt;
|S5L8701&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41422 SST39WF800A] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
| N46&lt;br /&gt;
| 26&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 4G]]&lt;br /&gt;
|S5L8720&lt;br /&gt;
|Integrated (32MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N58&lt;br /&gt;
| 31&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 5G]]&lt;br /&gt;
|S5L8730&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N33&lt;br /&gt;
| 34&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 6G|Nano 6G]]&lt;br /&gt;
|S5L8723&lt;br /&gt;
|Integrated&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N20&lt;br /&gt;
| 36&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 7G|Nano 7G]]&lt;br /&gt;
|S5L8740&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N31&lt;br /&gt;
| 37&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 1G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 2G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X51163PE] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
Concerning the detailed generation pages: If you can prove or disprove any of these chip names, please let us know: [[Contact]]&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Chip analyses&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPod_Touch-whatsinside-57.aspx&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPhone-whatsinside-4.aspx&lt;br /&gt;
Additional information&lt;br /&gt;
*http://dendrites.blog.163.com/blog/static/165376178201082112922174/&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Hardware&amp;diff=22024</id>
		<title>Hardware</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Hardware&amp;diff=22024"/>
		<updated>2023-02-25T20:31:37Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;This is just a basic comparison of each generation&#039;s main components. For a detailed hardware analysis of a generation, click on it&#039;s link.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Generation !! CPU !! RAM !! NOR/Utility Flash !! Codename !! UpdaterFamilyID&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 1G]]&lt;br /&gt;
|PP5021C-TDF&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41856 SST39WF400A] (512KiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 2G]]&lt;br /&gt;
|S5L8701&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41422 SST39WF800A] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
| N46&lt;br /&gt;
| 26&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 4G]]&lt;br /&gt;
|S5L8720&lt;br /&gt;
|Integrated (32MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N58&lt;br /&gt;
| 31&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 5G]]&lt;br /&gt;
|S5L8730&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N33&lt;br /&gt;
| 34&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 6G|Nano 6G]]&lt;br /&gt;
|S5L8723&lt;br /&gt;
|Integrated&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N20&lt;br /&gt;
| 36&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 7G|Nano 7G]]&lt;br /&gt;
|S5L8740&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N31&lt;br /&gt;
| 37&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 1G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 2G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X51163PE] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
Concerning the detailed generation pages: If you can prove or disprove any of these chip names, please let us know: [[Contact]]&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Chip analyses&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPod_Touch-whatsinside-57.aspx&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPhone-whatsinside-4.aspx&lt;br /&gt;
Additional information&lt;br /&gt;
*http://dendrites.blog.163.com/blog/static/165376178201082112922174/&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Hardware&amp;diff=22023</id>
		<title>Hardware</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Hardware&amp;diff=22023"/>
		<updated>2023-02-25T20:30:02Z</updated>

		<summary type="html">&lt;p&gt;Q3k: Add UpdaterFamilyID&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;This is just a basic comparison of each generation&#039;s main components. For a detailed hardware analysis of a generation, click on it&#039;s link.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Generation !! CPU !! RAM !! NOR/Utility Flash !! Codename !! UpdaterFamilyID&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 1G]]&lt;br /&gt;
|PP5021C-TDF&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41856 SST39WF400A] (512KiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 2G]]&lt;br /&gt;
|S5L8701&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41422 SST39WF800A] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
| N46&lt;br /&gt;
| 26&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 4G]]&lt;br /&gt;
|S5L8720&lt;br /&gt;
|Integrated (32MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N58&lt;br /&gt;
| 31&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 5G]]&lt;br /&gt;
|S5L8730&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N33&lt;br /&gt;
| 34&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 6G|Nano 6G]]&lt;br /&gt;
|S5L8723&lt;br /&gt;
|Integrated&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N20&lt;br /&gt;
| 36&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 7G|Nano 7G]]&lt;br /&gt;
|S5L8740&lt;br /&gt;
|Integrated&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N31&lt;br /&gt;
| 37&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 1G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 2G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X51163PE] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
Concerning the detailed generation pages: If you can prove or disprove any of these chip names, please let us know: [[Contact]]&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Chip analyses&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPod_Touch-whatsinside-57.aspx&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPhone-whatsinside-4.aspx&lt;br /&gt;
Additional information&lt;br /&gt;
*http://dendrites.blog.163.com/blog/static/165376178201082112922174/&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=RetailOS&amp;diff=22022</id>
		<title>RetailOS</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=RetailOS&amp;diff=22022"/>
		<updated>2023-02-25T09:58:24Z</updated>

		<summary type="html">&lt;p&gt;Q3k: RetailOS -&amp;gt; retailOS&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;The stock operating system running on non-iOS iPods. It runs everything from device drivers to the clickwheel user interface.&lt;br /&gt;
&lt;br /&gt;
== Naming ==&lt;br /&gt;
&lt;br /&gt;
The only &#039;official&#039; name seems to be &#039;retailOS&#039;, found in the [[Nano 3G]] WTF. It is also referred to as &#039;osos&#039; per the file name in the resource partition of the firmware bundle.&lt;br /&gt;
&lt;br /&gt;
== Architecture ==&lt;br /&gt;
&lt;br /&gt;
retailOS is a small, embedded, single-user, single-binary, real time operating system. With time it acquire more and more complex functionality, like PowerVR drivers and being able to load external applications (&#039;eApps&#039;) which are used for games.&lt;br /&gt;
&lt;br /&gt;
The core of the system is based on RTXC 3.2, with the end-user interface based on intellectual property from a company called Pixo. &amp;lt;ref&amp;gt;https://twitter.com/johnwhitley/status/1451952369248264201&amp;lt;/ref&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Security ==&lt;br /&gt;
&lt;br /&gt;
As evidenced by the success of the [[Notes vulnerability]], at least up to Nano 4G there was no kind of security hardening, and in fact all processes, including games, seem to be running in ARM system mode. This should make exploitation of newer retailOS bugs trivial.&lt;br /&gt;
&lt;br /&gt;
=== Boot chain ===&lt;br /&gt;
&lt;br /&gt;
retailOS is loaded by the second-stage bootloader (stored on NOR/NAND depending on the device generation), from NAND into DRAM.&lt;br /&gt;
&lt;br /&gt;
While other stages of the boot chain (eg. the bootloader, WTF mode in newer devices, the diagnostics tool) are based around EFI firmware volumes and an EFI runtime, retailOS is a single binary blob without any built-in modularity.&lt;br /&gt;
&lt;br /&gt;
=== eApp Signing ===&lt;br /&gt;
&lt;br /&gt;
Not yet documented fully. Each game seems to ship with a Manifest.plist.p7p which is a PKCS#7 signature for the main Manifest.plist.&lt;br /&gt;
&lt;br /&gt;
== Options ==&lt;br /&gt;
&lt;br /&gt;
We have found some &#039;secret&#039; options that can be set by creating specially named files. See [[RetailOS_Options|Options]].&lt;br /&gt;
&lt;br /&gt;
== RTXC == &lt;br /&gt;
&lt;br /&gt;
=== Documentation ===&lt;br /&gt;
&lt;br /&gt;
This seems to be the best public document available about RTXC 3.2: [https://web.archive.org/web/20230218212424/https://datasheet.datasheetarchive.com/originals/library/Datasheets-AS2/DSAAXSA0003458.pdf DSAAXSA0003458.pdf]. It contains example code for most services, but unfortunately is still missing any structure definitions.&lt;br /&gt;
&lt;br /&gt;
There&#039;s also some training slides available: [https://ia801800.us.archive.org/26/items/manualzilla-id-5752851/5752851.pdf 5752851.pdf]. These introduce the general architecture and concept of RTXC 3.2. &lt;br /&gt;
&lt;br /&gt;
=== Services / Syscalls ===&lt;br /&gt;
&lt;br /&gt;
While RTXC documentation speaks mostly of &#039;kernel services&#039; (which are defined as C function signatures/symbols), we like to talk about &#039;syscalls&#039; and &#039;syscall numbers&#039; when reverse engineering retailOS. All service functions go through a central dispatch function and that&#039;s the easiest point to start reverse engineering the kernel service interface.&lt;br /&gt;
&lt;br /&gt;
The dispatcher receives a saved caller state which contains a pointer to a serialized syscall request in its saved R0. The syscall request is a trivial structure containing a syscall number and arguments. The dispatcher is executed with interrupts enabled (and thus is non-preemptable) and performs actual work on kernel structures. There is no privilege-granting &#039;gate&#039; mechanism, all caller code is just as privileged as the kernel code.&lt;br /&gt;
&lt;br /&gt;
Service functions in turn prepare the syscall request structure (including syscall number), and then call an intermediary state saving function which then calls the dispatcher after disabling interrupts. Some syscall numbers are used by multiple service functions, with some extra arguments in the request being used to decide on the behaviour of the service call (eg. blocking/nonblocking).&lt;br /&gt;
&lt;br /&gt;
The following table comes from cross-referencing retailOS, publicly available RTXC PDFs and publicly availble RTXC binaries with debug symbols.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Name !! Number !! Description&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_pend(SEMA sema)&amp;lt;/code&amp;gt; || 0x03 || Semaphore DONE -&amp;gt; PENDING.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;RTXCMSG *KS_receive(MBOX mailbox, TASK  task)&amp;lt;/code&amp;gt; || 0x05 || Receive from mailbox.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;KSRC KS_enqueue[w](QUEUE queue, void *entry)&amp;lt;/code&amp;gt; || 0x0c || Push into FIFO (and block if full with &#039;w&#039; variant).&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_dequeue[w](QUEUE queue, void *dest)&amp;lt;/code&amp;gt; || 0x0d || Pop from FIFO (and block if empty with &#039;w&#039; variant).&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;KSRC KS_lock(RESOURCE resource)&amp;lt;/code&amp;gt; || 0x0e || Lock a resource.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;KSRC KS_lockt(RESOURCE resource, TICKS timoeut)&amp;lt;/code&amp;gt; || 0x0e || Lock a resource with timeout.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;KSRC KS_unlock(RESOURCE resource)&amp;lt;/code&amp;gt; || 0x0f || Unlock an owned resource.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;CLKBLK *KS_alloc_timer(void)&amp;lt;/code&amp;gt; || 0x10 || Allocate next free timer from pool.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;CLKBLK *KS_start_timer(CLKBLK *timer, TICKS initial_period, TICKS cycle_time, SEMA sema)&amp;lt;/code&amp;gt; || 0x12 || Start timer.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;KSRC KS_stop_timer(CLKBLK *timer)&amp;lt;/code&amp;gt; || 0x13 || Stop timer.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_delay(TASK task, TICKS period)&amp;lt;/code&amp;gt; || 0x14 || Block specified task for a period of time.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_execute(TASK task)&amp;lt;/code&amp;gt; || 0x15 || Start a task from its beginning address.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;KSRC KS_deftask(TASK task, PRIORITY priority, char *stack, size_t stacksize, void (*entry)(void))&amp;lt;/code&amp;gt; || 0x16 || Define the attributes of an inactive task.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;TASK KS_alloc_task(void)&amp;lt;/code&amp;gt; || 0x17 || Allocate the next available Task Control Block from the pool of free TCBs. &lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_terminate(TASK task)&amp;lt;/code&amp;gt; || 0x18 || Stop a task by setting it to INACTIVE.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_suspend(TASK task)&amp;lt;/code&amp;gt; || 0x19 || Suspend a task until resumed or re-executed.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_defpriority(TASK task, PRIORITY priority)&amp;lt;/code&amp;gt; || 0x1b || Define or set priority of task.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_yield(void)&amp;lt;/code&amp;gt; || 0x1c || Voluntary release of control to any other task of the same priority.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;SEMA KS_waitm(SEMA *semalist)&amp;lt;/code&amp;gt; || 0x22 || Wait on multiple semaphores.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;time_t KS_inqtime(void)&amp;lt;/code&amp;gt; || 0x24 || Get current time-of-day.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_deftime(time_t time)&amp;lt;/code&amp;gt; || 0x25 || Set current time-of-day.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;TASK KS_inqres(RESOURCE resource)&amp;lt;/code&amp;gt; || 0x26 || Get owner of resource.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;KSRC KS_defres(RESOURCE resource, RESATTR condition)&amp;lt;/code&amp;gt; || 0x27 || Define priority inversion on resource.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void *KS_inqtask_arg(TASK task)&amp;lt;/code&amp;gt; || 0x28 || Get environment arguments of task.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;void KS_deftask_arg(TASK task, void *arg)&amp;lt;/code&amp;gt; || 0x29 || Set environment arguments for task.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;KSRC KS_defqueue(QUEUE queue, size_t width, int depth, void *body, int currsize)&amp;lt;/code&amp;gt; || 0x2e || Define queue.&lt;br /&gt;
|-&lt;br /&gt;
| &amp;lt;code&amp;gt;int KS_user(int (*func) (void *), void *arg)&amp;lt;/code&amp;gt; || 0x30 || Execute function as if it were kernel service.&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
The RTXC memory allocation facilities (&amp;lt;code&amp;gt;KS_alloc/free/create_part/alloc_part/defpart/free_part&amp;lt;/code&amp;gt;) are &#039;&#039;not&#039;&#039; used by retailOS and not built into the service dispatcher, at least on [[Nano 5G]].&lt;br /&gt;
&lt;br /&gt;
=== Semaphores ===&lt;br /&gt;
&lt;br /&gt;
The following semaphores are defined in the [[Nano 3G]] retailOS:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Number !! Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x01 || &amp;lt;code&amp;gt;S_FW_PWR_CHANGE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x02 || &amp;lt;code&amp;gt;S_BAT_PWR_CHANGE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x03 || &amp;lt;code&amp;gt;S_USB_PWR_CHANGE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x04 || &amp;lt;code&amp;gt;S_CNA_CHANGE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x05 || &amp;lt;code&amp;gt;S_WHEEL_CHANGE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x06 || &amp;lt;code&amp;gt;S_DISKMGRQ&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x07 || &amp;lt;code&amp;gt;S_TOPPLUG_SWITCH&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x08 || &amp;lt;code&amp;gt;S_RTCTIMERMGR&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x09 || &amp;lt;code&amp;gt;S_ALARM_01&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x0a || &amp;lt;code&amp;gt;S_ALARM_02&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x0b || &amp;lt;code&amp;gt;S_ALARM_03&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x0c || &amp;lt;code&amp;gt;S_WATCHDOG&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x0d || &amp;lt;code&amp;gt;S_CPUMGRQ&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x0e || &amp;lt;code&amp;gt;S_PCFPOWERMGR&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x0f || &amp;lt;code&amp;gt;S_POWER_STATE_AC&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x10 || &amp;lt;code&amp;gt;S_CGR_STATE_TMR&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x11 || &amp;lt;code&amp;gt;S_DEEPSLEEP&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x12 || &amp;lt;code&amp;gt;S_ALARM_DONE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x13 || &amp;lt;code&amp;gt;S_PIEZOMGR&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x14 || &amp;lt;code&amp;gt;S_PIEZOMGRSNDR&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x15 || &amp;lt;code&amp;gt;S_PIEZODONE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x16 || &amp;lt;code&amp;gt;S_ACCPOWER&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x17 || &amp;lt;code&amp;gt;S_ACC_REINIT&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x18 || &amp;lt;code&amp;gt;S_TOPPLUGSENSER&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x19 || &amp;lt;code&amp;gt;S_TOPPLUGCHANGE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x1a || &amp;lt;code&amp;gt;S_BTMCONNECT&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x1b || &amp;lt;code&amp;gt;S_BTMPLUGCHANGE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x1c || &amp;lt;code&amp;gt;S_BTMREVERIFY&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x1d || &amp;lt;code&amp;gt;S_BTMREVERTIMED&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x1e || &amp;lt;code&amp;gt;S_BTMVERCOMP&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x1f || &amp;lt;code&amp;gt;S_TOPACCPKTRCVD&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x20 || &amp;lt;code&amp;gt;S_BTMACCPKTRCVD&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x21 || &amp;lt;code&amp;gt;S_SERIALIDRCVD&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x22 || &amp;lt;code&amp;gt;S_UARTATXEMPTY&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x23 || &amp;lt;code&amp;gt;S_UARTBTXEMPTY&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x24 || &amp;lt;code&amp;gt;S_HDDSCANCOMP&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x25 || &amp;lt;code&amp;gt;S_BL_ON&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x26 || &amp;lt;code&amp;gt;S_BL_OFF&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x27 || &amp;lt;code&amp;gt;S_BL_RAMPDOWN&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x28 || &amp;lt;code&amp;gt;S_BL_RAMPUP&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x29 || &amp;lt;code&amp;gt;S_BL_TIMESUP&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x2a || &amp;lt;code&amp;gt;S_BATT_TIMESUP&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x2b || &amp;lt;code&amp;gt;S_BATT_AC_PWR&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x2c || &amp;lt;code&amp;gt;S_BATT_TMR_RST&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x2d || &amp;lt;code&amp;gt;S_GRAPHMGR&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x2e || &amp;lt;code&amp;gt;S_VBL&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x2f || &amp;lt;code&amp;gt;S_DTVRECOVERY&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x30 || &amp;lt;code&amp;gt;S_CM_HEADPHONE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x31 || &amp;lt;code&amp;gt;S_CM_EXTPOWER&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x32 || &amp;lt;code&amp;gt;S_CM_ACCATTACHED&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x33 || &amp;lt;code&amp;gt;S_CM_DAC_SETUP&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x34 || &amp;lt;code&amp;gt;S_ATAWRKLPRDY&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x35 || &amp;lt;code&amp;gt;S_RTXCBUG&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x36 || &amp;lt;code&amp;gt;S_BLOCKDEVICE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x37 || &amp;lt;code&amp;gt;S_BLOCKDEVICEQ&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x38 || &amp;lt;code&amp;gt;S_DISPLAY&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x39 || &amp;lt;code&amp;gt;S_ARB_READY&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x3a || &amp;lt;code&amp;gt;S_I2C_DONE&amp;lt;/code&amp;gt; || &lt;br /&gt;
|-&lt;br /&gt;
| 0x3b || &amp;lt;code&amp;gt;S_VSYNC&amp;lt;/code&amp;gt; || &lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
There are three more semaphores (0x3c, 0x3d, 0x3e) that have no name defined and are likely unused. Anything 0x3f and up is a &#039;Dynamic&#039; semaphore defined at runtime (which we haven&#039;t reversed yet).&lt;br /&gt;
&lt;br /&gt;
=== Queues ===&lt;br /&gt;
&lt;br /&gt;
The following queues are defined in the [[Nano 3G]] retailOS:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Number !! Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x01 || PIXORESQ ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x02 || PIXOSEMAQ ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x03 || POSIXRESQ ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x04 || POSIXSEMAQ ||&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
=== Mailboxes ===&lt;br /&gt;
&lt;br /&gt;
The following mailboxes are defined in the [[Nano 3G]] retailOS:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Number !! Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x01 || M_DISKMGR ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x02 || M_PIEZOMGR ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x03 || M_GRAPHMGR ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x04 || M_BLOCKDEVICE ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x05 || M_DISPLAY ||&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
=== Resources ===&lt;br /&gt;
&lt;br /&gt;
The following lockable resources are defined in the [[Nano 3G]] retailOS:&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
|-&lt;br /&gt;
! Number !! Name !! Description&lt;br /&gt;
|-&lt;br /&gt;
| 0x01 || GPIO_REG_WRITE ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x02 || GPIO_INT_INIT ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x03 || RTC_TIME_ADJUST ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x04 || RTC_ALARM_ADJUST ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x05 || I2C_MASTER ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x06 || USB_GRANT ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x07 || USB_RESP_INIT ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x08 || USB_RESPONDER ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x09 || DISKPWRMGRSEND ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x0a || PIEZOMGRSEND ||&lt;br /&gt;
|- &lt;br /&gt;
| 0x0b || SERIALVERIFIER ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x0c || RESISTORVERIFIER ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x0d || FW_IRAM ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x0e || ACCPOWER ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x0f || UARTA ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x10 || UARGB ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x11 || PMU_LOCK ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x12 || ADC_LOCK ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x13 || DTV_ENC_INIT ||&lt;br /&gt;
|-&lt;br /&gt;
| 0x14 || BACKLIGHT ||&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
== External links ==&lt;br /&gt;
&lt;br /&gt;
* [https://web.archive.org/web/19990220054659/http://www.rtxc.com/Products/RTXC/Services.htm RTXC Kernel Services (1999)]&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
	<entry>
		<id>https://freemyipod.org/index.php?title=Hardware&amp;diff=22021</id>
		<title>Hardware</title>
		<link rel="alternate" type="text/html" href="https://freemyipod.org/index.php?title=Hardware&amp;diff=22021"/>
		<updated>2023-02-23T17:32:12Z</updated>

		<summary type="html">&lt;p&gt;Q3k: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;This is just a basic comparison of each generation&#039;s main components. For a detailed hardware analysis of a generation, click on it&#039;s link.&lt;br /&gt;
&lt;br /&gt;
{| class=&amp;quot;wikitable&amp;quot;&lt;br /&gt;
! Generation !! CPU !! RAM !! NOR/Utility Flash !! Codename&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 1G]]&lt;br /&gt;
|PP5021C-TDF&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41856 SST39WF400A] (512KiB)&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 2G]]&lt;br /&gt;
|S5L8701&lt;br /&gt;
|[http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=753&amp;amp;partnum=K4M56163PG K4M56163PG] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41422 SST39WF800A] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (32MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
| N46&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 4G]]&lt;br /&gt;
|S5L8720&lt;br /&gt;
|Integrated (32MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N58&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 5G]]&lt;br /&gt;
|S5L8730&lt;br /&gt;
|Integrated (64MiB)&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N33&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 6G|Nano 6G]]&lt;br /&gt;
|S5L8723&lt;br /&gt;
|Integrated&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N20&lt;br /&gt;
|-&lt;br /&gt;
|[[Nano 7G|Nano 7G]]&lt;br /&gt;
|S5L8740&lt;br /&gt;
|Integrated&lt;br /&gt;
| &#039;&#039;none&#039;&#039;&lt;br /&gt;
| N31&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 1G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 2G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X56163PI] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|-&lt;br /&gt;
|[[Classic 3G]]&lt;br /&gt;
|S5L8702&lt;br /&gt;
|[http://www.samsung.com/global/system/business/semiconductor/product/2007/11/13/236652ds_k4x56163pi.pdf K4X51163PE] (64MiB)&lt;br /&gt;
|[http://www.sst.com/products/?inode=41340 SST25VF080B] (1MiB)&lt;br /&gt;
|&lt;br /&gt;
|}&lt;br /&gt;
&lt;br /&gt;
Concerning the detailed generation pages: If you can prove or disprove any of these chip names, please let us know: [[Contact]]&lt;br /&gt;
&lt;br /&gt;
==Helpful pages==&lt;br /&gt;
Chip analyses&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPod_Touch-whatsinside-57.aspx&lt;br /&gt;
*http://www2.electronicproducts.com/Apple_iPhone-whatsinside-4.aspx&lt;br /&gt;
Additional information&lt;br /&gt;
*http://dendrites.blog.163.com/blog/static/165376178201082112922174/&lt;/div&gt;</summary>
		<author><name>Q3k</name></author>
	</entry>
</feed>