freemyipod - User contributions [en]

S5L8702

2023-09-11T23:09:19Z

Iscle: /* USB */

== Introduction ==
This page provides details on the Samsung S5L8702 System on Chip (SoC).<br>
'''NOTE:''' All information provided here has been obtained by reverse engineering and is not guaranteed to be accurate.

== Peripherals ==
An overview of the peripherals of the SoC, describing the base address and registers for each one.

=== SPI ===
{| class="wikitable"
|-
! SPI !! Base address
|-
| SPI0 || 0x3c300000
|-
| SPI1 || 0x3ce00000
|-
| SPI2 || 0x3d200000
|}

==== Registers ====
{| class="wikitable"
! Register Name
! Offset
! Description
! Note
|-
| SPICTRL
| 0x00
|
|
|-
| SPISETUP
| 0x04
|
|
|-
| SPISTATUS
| 0x08
|
|
|-
| SPIPIN
| 0x0c
|
|
|-
| SPITXDATA
| 0x10
|
|
|-
| SPIRXDATA
| 0x20
|
|
|-
| SPICLKDIV
| 0x30
|
|
|-
| SPIRXLIMIT
| 0x34
|
|
|}

==== SPICTRL ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| Unk2
| 1
| R/W?
|
| Gets checked by the bootloader after clearing/setting ''Unk1''
|-
| Unk1
| 0
| R?/W
|
| Gets cleared/set by the bootloader
|}

==== SPISETUP ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| RW
| 0
| R?/W
|
| 0 = TX<br>1 = RX
|}

==== SPISTATUS ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|}

==== SPIPIN ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|}

==== SPITXDATA ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| DATA
| 7:0
| R?/W
| Data to be sent by the SPI peripheral
|
|}

==== SPIRXDATA ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| DATA
| 7:0
| R/W?
| Data received by the SPI peripheral
|
|}

==== SPICLKDIV ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| CLKDIV
| 10:0
| R?/W
|
|
|}

==== SPIRXLIMIT ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|}

=== Chip ID ===
Base address: 0x3d100000

=== JPEG Decoder ===
Base address: 0x39600000

=== ATA ===
Base address: 0x38700000

=== GPIO ===
Base address: 0x3cf00000

=== System Controller ===
Base address: 0x3c500000

=== WatchDog ===
Base address: 0x3c800000

=== MIU ===
Base address: 0x38100000

=== TIMER ===
Base address: 0x3c700000

=== USB ===
OTG base address: 0x38400000<br>
PHY base address: 0x3c400000

S5L8702

2023-09-11T23:09:10Z

Iscle: /* JPEG Decoder */

S5L8702

2023-09-11T23:01:28Z

Iscle:

Classic 3G

2023-09-11T21:57:13Z

Iscle: /* Components */

[[Image:Front_3g.jpg|500px]]
[[Image:Back_3g.jpg|500px]]

iPod classic MC293, 160GB, silver

No better teardown pictures of the Classic 3G have been found or made by us yet. There is, however, [http://www.ilounge.com/index.php/news/comments/ipod-classic-160gb-changes-new-firmware-engraving/ a basic guide of the non-electronic differences] by iLounge. Since the model number is the same as the [[Classic 2G]], there probably aren't any worthwhile (if any) in the hardware.

==Terminology==
By iPod classic 3g we mean the re-introduced 160GB version of the classic which was announced on September 9 2009. It is the same size as the [[Classic 2G]].

==Components==
{| class="wikitable"
! Label !! Component !! Part !! Markings !! Notes
|-
| 3
| CPU
| [https://freemyipod.org/wiki/S5L8702 Samsung S5L8702]
|337S3526 8702 N26P9U4 1011 ARM
| ARM926EJ-S processor. The package itself is Apple-branded and marked 337S3473 8702. Same as on the Nano 3G
|-
| 2
| SDRAM
| K4X51163PE
|
|
|-
| 5
| Utility Flash
| [http://www.sst.com/products/?inode=41340 SST25VF080B]
|
| Same as on the Nano 3G
|-
| 4
| Audio codec
| [http://www.cirrus.com/en/pubs/proDatasheet/CS42L55_F1.pdf Cirrus Logic CS42L55]
| APPLE 338S0394 AICK0952 MAL
|
|-
| 1
| Power manager
| NXP PCF50635
| APPLE 338S0445 78030 82 D780113
|
|-
| 6
| USB charging
| LTC4066
|4066T 84453
|
|}

S5L8702

2023-09-11T21:56:35Z

Iscle: /* SPISETUP */

S5L8702

2023-09-11T21:54:23Z

Iscle:

== Introduction ==
This page provides details on the Samsung S5L8702 System on Chip (SoC).<br>
'''NOTE:''' All information provided here has been obtained by reverse engineering and is not guaranteed to be accurate.

== Peripherals ==
An overview of the peripherals of the SoC, describing the base address and registers for each one.

=== SPI ===
{| class="wikitable"
|-
! SPI !! Base address
|-
| SPI0 || 0x3c300000
|-
| SPI1 || 0x3ce00000
|-
| SPI2 || 0x3d200000
|}

==== Registers ====
{| class="wikitable"
! Register Name
! Offset
! Description
! Note
|-
| SPICTRL
| 0x00
|
|
|-
| SPISETUP
| 0x04
|
|
|-
| SPISTATUS
| 0x08
|
|
|-
| SPIPIN
| 0x0c
|
|
|-
| SPITXDATA
| 0x10
|
|
|-
| SPIRXDATA
| 0x20
|
|
|-
| SPICLKDIV
| 0x30
|
|
|-
| SPIRXLIMIT
| 0x34
|
|
|}

==== SPICTRL ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| Unk2
| 1
| R/W?
|
| Gets checked by the bootloader after clearing/setting ''Unk1''
|-
| Unk1
| 0
| R?/W
|
| Gets cleared/set by the bootloader
|}

==== SPISETUP ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| RW
| 0
| R?/W
|
| Set to 1 for RX, 0 for TX
|}

==== SPISTATUS ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|}

==== SPIPIN ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|}

==== SPITXDATA ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| DATA
| 7:0
| R?/W
| Data to be sent by the SPI peripheral
|
|}

==== SPIRXDATA ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| DATA
| 7:0
| R/W?
| Data received by the SPI peripheral
|
|}

==== SPICLKDIV ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| CLKDIV
| 10:0
| R?/W
|
|
|}

==== SPIRXLIMIT ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|}

S5L8702

2023-09-11T21:53:24Z

Iscle:

== Introduction ==
This page provides details on the Samsung S5L8702 System on Chip (SoC).

== Peripherals ==
An overview of the peripherals of the SoC, describing the base address and registers for each one.

=== SPI ===
{| class="wikitable"
|-
! SPI !! Base address
|-
| SPI0 || 0x3c300000
|-
| SPI1 || 0x3ce00000
|-
| SPI2 || 0x3d200000
|}

==== Registers ====
{| class="wikitable"
! Register Name
! Offset
! Description
! Note
|-
| SPICTRL
| 0x00
|
|
|-
| SPISETUP
| 0x04
|
|
|-
| SPISTATUS
| 0x08
|
|
|-
| SPIPIN
| 0x0c
|
|
|-
| SPITXDATA
| 0x10
|
|
|-
| SPIRXDATA
| 0x20
|
|
|-
| SPICLKDIV
| 0x30
|
|
|-
| SPIRXLIMIT
| 0x34
|
|
|}

==== SPICTRL ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| Unk2
| 1
| R/W?
|
| Gets checked by the bootloader after clearing/setting ''Unk1''
|-
| Unk1
| 0
| R?/W
|
| Gets cleared/set by the bootloader
|}

==== SPISETUP ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| RW
| 0
| R?/W
|
| Set to 1 for RX, 0 for TX
|}

==== SPISTATUS ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|}

==== SPIPIN ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|}

==== SPITXDATA ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| DATA
| 7:0
| R?/W
| Data to be sent by the SPI peripheral
|
|}

==== SPIRXDATA ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| DATA
| 7:0
| R/W?
| Data received by the SPI peripheral
|
|}

==== SPICLKDIV ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| CLKDIV
| 10:0
| R?/W
|
|
|}

==== SPIRXLIMIT ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|}

S5L8702

2023-09-11T21:51:19Z

Iscle:

== Introduction ==
This page provides details on the Samsung S5L8702 System on Chip (SoC).

== Peripherals ==
An overview of the peripherals of the SoC, describing the base address and registers for each one.

=== SPI ===
{| class="wikitable"
|-
! SPI !! Base address
|-
| SPI0 || 0x3c300000
|-
| SPI1 || 0x3ce00000
|-
| SPI2 || 0x3d200000
|}

==== Registers ====
{| class="wikitable"
! Register Name
! Offset
! Description
! Note
|-
| SPICTRL
| 0x00
|
|
|-
| SPISETUP
| 0x04
|
|
|-
| SPISTATUS
| 0x08
|
|
|-
| SPIPIN
| 0x0c
|
|
|-
| SPITXDATA
| 0x10
|
|
|-
| SPIRXDATA
| 0x20
|
|
|-
| SPICLKDIV
| 0x30
|
|
|-
| SPIRXLIMIT
| 0x34
|
|
|}

==== SPICTRL ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| Unk2
| 1
| R/W?
|
| Gets checked by the bootloader after clearing/setting ''Unk1''
|-
| Unk1
| 0
| R?/W
|
| Gets cleared/set by the bootloader
|}

==== SPISETUP ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| Unk2
| 1
| R/W?
|
| Gets checked by the bootloader after clearing/setting ''Unk1''
|-
| Unk1
| 0
| R?/W
|
| Gets cleared/set by the bootloader
|}

==== SPISTATUS ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|}

==== SPIPIN ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|}

==== SPITXDATA ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| DATA
| 7:0
| R?/W
| Data to be sent by the SPI peripheral
|
|}

==== SPIRXDATA ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| DATA
| 7:0
| R/W?
| Data received by the SPI peripheral
|
|}

==== SPICLKDIV ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|-
| CLKDIV
| 10:0
| R?/W
|
|
|}

==== SPIRXLIMIT ====
{| class="wikitable"
! Name
! Bit
! Type
! Description
! Note
|}

S5L8702

2023-09-11T21:45:16Z

Iscle:

S5L8702

2023-09-11T21:44:55Z

Iscle: Created page with "== Introduction == This page provides details on the Samsung S5L8702 System on Chip (SoC). == Peripherals == An overview of the peripherals of the SoC, describing the base ad..."